Yamaha SPX990 Service Manual page 11

SPX990
LSI
PIN
DESCRIPTION
®
HD63B03YP-N
(XD245A00} CPU
PIN
NO,
NAME
I/O
FUNCTION
PIN
NO
NAME
1/0
FUNCTION
*
1
Vss
Ground
33 Vcc
DC
Supply
(
+
5V)
2
XTAL
1
}
Clock
34
A15 0
3
EXTAL
1
35
A14 0
4
5
MPO
MP1
1
1
1
Mode
program
36
37
A13
A12
0
0
Address bus
6
RES
1
Reset
38 All
0
7
STBY
1
Stand-by
mode
signal
39
A10 0
8
NMI
1
Non-maskable
interrupt
40 A9 0
9
P20
I/O
41
A8
0
10 P21
I/O
42 Vss Ground
11
P22
I/O
43 A7
0
12
P23
I/O
Port 2
44
A6 0
13 P24
I/O
45 A5 0
14
P25
I/O
46
A4 0
Address bus
15
P26
I/O
47
A3 0
16
P27
I/O
48
A2 0
17
P50
I/O
49 A1 0
18
P51
I/O
50
AO 0
19
P52
I/O
51
D7
I/O
20 P53
I/O
Port 5
52
06
I/O
21
P54
I/O
53 05
I/O
22
P55
I/O
54 04
I/O
Data bus
23
P56
I/O
55
03
I/O
24 P57
I/O
56 02
I/O
25
P60
I/O
57 01
I/O
26 P61
I/O
58
DO
I/O
27
P62
I/O
59 BA 0
Bus
available
28 P63
I/O
Port
6
60
OR
0
Load
instruction register
29
P64
I/O
61
R/W
0
Read/Write
control
30 P65
I/O
62
wR
0
Write
control
31
P66
I/O
63 RD
0
Read
control
32
P67
I/O
64
E
0
Enable
o
HD63B50P
(IG
147300)
ACIA
(Asynchronous Communication
Interface
Adaptor)
PIN
NO.
NAME
I/O
FUNCTION
PIN
NO-
NAME
I/O
FUNCTION
1
Vss Ground
13
R/W
Read/Write
2 Rx Data Receive data
14 E
1
Enable
3 Rx
CLK
Receive clock
15
07
1/0
4 Tx CLK
0
Transmit
clock 16
06
I/O
5
RTS
I/O
Request
to
send
17
05
I/O
6
Tx Data
0
Transmit
data
18
04
I/O
Data bus
7
IRQ
Interrup request
19
03
I/O
8
CSO
]
20
02
I/O
9
CS2
}
Chip
select
21
01
I/O
10
CS1
i
1
22
DO
1/0
11
RS
1
Resist select 23
DCD
1
Data
carrier
detect
12 Vcc
1
Power supply I+5V)
24
CIS
1
Clear
to
send
® YIV16104
(XE788A00)
DEQ2
(Digital Equalizer)
PIN
NO,
NAME
I/O
FUNCTION
PIN
NO
NAME
I/O
FUNCTION
1
Vcc
i
+ 5V
12
2
XMD
[
Alteration of
Sync (-» -h5V)
or
Asynch
13,14
SiO, S11
INPUT
for Serial
data
signal
l-OV)
for
CD!
input terminal (Synch:
15,16
SO0.SO1 0
OUTPUT
for Serial
data
signal
CRS
1:1),
Asynch:
16:1)
17
OVP 0
3
1
Initialized
Serial
Control Interface
18
TEST
1
For
test-
Normally connecting
to
+ 5V
4 CDI
1
Inputs of
|i
PGM,
Para,
Ser.
Cont
Data of Control Reg.
19
C2
O
Output
is
delayed Data
of
2nd
bit
of
5
CDO
0
Outputs
of
p
PGM,
Para, Ser Cont-
Data of Control
Reg,.
20 Cl 0
Output
is
delayed Data
of 1st
bit
of
6
XCLK
1
In/Out clock
for
CDI&
CDO
21
CO 0
Output
is
delayed Data
of
0
bit
of
7
1
Hli
i
Determins
transmit
timming
of
PARA
8
ESL
1
to
Para Reg. from
T
BFR
Timming
determination of data
for
22
CEMD
1
f5V:
It's
necessory
to input
2 Byte
ELD
External
at
Ext
Shift
CLK
9
1
Timming
determination of data
for
CE
to
CDI
10
ECLK
inner at Ext. Shift
CLK
23
TC
1
1
Input Shift
CLK
of
IN/OUT SR
at
Ext
Shift
CLK
24
Sync
I
Synchro
signal
for
system
11
CLK
System Clock
14
SPX990