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4.9.2.1.
GDiscrete1
The backplane busses this signal to all slots.
The single-ended impedance is 50 Ohms.
470 Ohm +-5% resistors terminate the signal at both end of the backplane to 3.3V_AUX.
4.9.2.2.
SYS_CON*
Slot number 1 (leftmost) has this pin connected to ground.
To allow for ambiguity in the specification, all slots have provision for connecting this pin to ground.
4.9.2.3.
UD
These pins are application specific and not defined. Note that these are strictly pass-through to the
associated RTMs.
4.9.2.4.
MaskableReset*
This pin is application specific and not defined. It could be bussed or individually routed to a
connection point. This backplane busses the signal and routes it to P22 and P23.
4.9.2.5.
P1-VBAT
The backplane busses this signal to all slots and to P26. Refer to Section 3.3.1.2.
4.9.3.
J2- SIGNALS
Table 4-7 displays the assignment of signals on J2. Note that these are strictly pass-through to the
associated RTMs.
© 2 018
Table 4-7 J2-J6 Pin Assignment
3U V P X 8 SL OT P O WE R/ G RO UN D
P AG E 19
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