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VSC7227 Evaluation Board User Guide VPPD-03088 Revision 2.0 June 2013 Vitesse Proprietary and Confidential...
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Vitesse product in such an application without express written consent of an officer of Vitesse does so at their own risk, and agrees to fully indemnify Vitesse for any damages that may result from such use or sale.
User Guide Introduction The VSC7227 device is a 12-channel uni-directional lane adaptive channel extender with a CRU. This device offers input equalization, clock/data recovery, and output de- emphasis. It supports all data rates from 1 Gbps to 14.5 Gbps. The device is available in a 13 mm x 13 mm, 144 pin, flip chip ball grid array (FCBGA), and operates on a single supply of 1.2 Volts.
Figure 2. VSC7227 Evaluation Board The VSC7227 can be used with or without an external microcontroller. In pin strap mode, various control pins can be set to configure the device for certain standalone applications. For access to all of the features of the device, the external microcontroller is used to configure internal device registers via an I2C bus.
A pattern generator, error detector, oscilloscope and PC are the basic instruments needed to evaluate the VSC7227 device. Simply connect the wall AC adaptor into the evaluation board and the wall socket. SW4 acts as the power on/off switch. Connect the USB cable to the evaluation board and to a PC.
Section 6.1, and 6.2. When the “Load Init. File” is run, the evaluation board will be configured for 10.3125 Gbps traffic. Figure 3. VSC7227 Basic Test Setup Power Supply Options There are two methods to supply power to this evaluation board.
External Reference Clock The VSC7227 device also supports an external clock source to be its reference clock. Changing the placement of R1, a 0 ohm resistor, to the adjacent location will route the reference clock input to an SMA input, J18, where the user can provide an external clock source.
In the case when the circle for VSC7227 Connected turns red, check the power supply. It could be that the current is limited or the VSC7227 VDD does not reach 1.2V. J34 header can be used as a checkpoint for the 1.2V rail.
A or B. These items are highlighted with red arrows. Figure 6. VSC7227 GUI – Main Page First of all, it is recommended to load the initialization script, which can be accessed by clicking Device on the top menu, and choose “Load Init. File”, as shown in Figure 7.
Power Down boxes. The VSC7227 also features an adjacent channel crossover, which is equivalent to a 2 x 2 crosspoint switch. The two adjacent channel pairs are channel n and channel n+1, where n is an even number.
6.4.3 Serial Data Rates Less Than 7.5 Gbps There are 3 VCOs (VCO0, VCO1, and VCO2) in the VSC7227, and the VCO2’s lower limit is at ~7.5Gbps. Therefore, for serial data rates that is lower than 7.5 Gbps the device will treat it as a sub-rate, and use the VCO divider. For example, a serial data rate of 5 Gbps uses VCO1 and VCODIVSEL of divide-by-2.
VSC7227 Evaluation Board User Guide Figure 9. VSC7227 GUI – Advanced Clocking Page Optimizing the Input Stage In this page, the user can adjust the VGA, Input EQ, EQVGA, DFE, and DC offset settings for each channel. Each one has an Adaptation mode and a Manual mode.
For most applications, this would not be necessary. The blue arrows in Figure 11 indicate the sliders or controls that are commonly used. Here are some of the steps to further optimize the VSC7227 receiver when error free operation is not achieved: •...
Adjust VGA Target to further optimize. This VGA block sets the amplitude of the signal going into the EQ block. Figure 11. VSC7227 Rev. A GUI – Advanced Input Stage and DFE Control Page Revision 2.0 Vitesse Proprietary and Confidential...
VSC7227 Evaluation Board User Guide Figure 12. VSC7227 Rev. B GUI – Advanced Input Stage and DFE Control Page • If error free operation is still not achieved, sometimes it is helpful to set the input EQ in the EQ Table mode. The default EQ Table value is 8, which means the 6 EQ stages are at 2/2/1/1/1/1.
The Data Rate Detect feature allows users to switch from one data rate to another, and the VSC7227 device will configure itself on the fly. For each channel, there are 4 look-up tables that are used to configure the VSC7227 to the known incoming data rates.
10.3125 Gbps, and FSYN1 is configured for 8 Gbps as shown in Figure 14. Figure 14. VSC7227 GUI – Setting Frequency Synthesizer 0 and 1 On the Data Rate Detect page shown in Figure 15, enter the desired data rates into each of the look-up tables and select the corresponding Reference Clock Source.
VSC7227 GUI – Data Rate Detect VScope One of the VSC7227 features is an on-chip eye monitoring capability, which is called VScope. The user is able to look at the data eye of each channel at 2 different points inside the device. VScope sample points are before the DFE block and after the DFE block, which can be selected on the Vscope page as seen in Figure 16.
VSC7227 Evaluation Board User Guide Figure 16. VSC7227 GUI – VScope at 10.3125 Gbps Register List Reading or writing registers can be done on the Register List page as seen in Figure 17. The registers are grouped into nine tabs.
VSC7227 GUI – Register List 6.10 The VSC7227 device has an internal error detector for each channel as seen in Figure 18. The user can simply select the desired PRBS pattern. Then, click the Start Checker button to begin error counting of all channels. The cumulative number of bit errors and the cumulative BER will be displayed for the 4 accessible channels on the evaluation board.
As window will pop up, asking for the file name and the save location. The file will be in a .txt format. Then, the user can simply load the saved file back into the VSC7227 at a later time using the Load All Registers selection.
The user can also load a script into the GUI, which is in a .txt format. The Command Line Interface window can be launched by clicking uC on the top menu bar, and select the Vitesse Command Line Interface menu option as shown in Figure 20. Figure 20.