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CIRCUIT DESCRIPTION
7. Display Microprocessor : M50747-D60SP (X14-2930-00 : IC5)
7-1. Terminal connection diagram
Vee COV)
Segment
A8
Segment A7
Segment
A§
Segment
A5
Segment
A4
Segment
A3
Segment A2
Segment Al
Grid 6
Grid 5
Grid 4
Grid 3
Grid 2
Grid ]
Segment
A5Q
Segment AQ5
RDY
CLK
SYNC
DATA
BUSY
CE
Latch
output
Segment
C3
CE
CNVss
Reset
input RESET
Clock
input
Xin
Clock output
Xout
Timing
output
¢
Vss COV)
t
f
a
i
64]
=
=
2
\63}
3
62) >
I |
61|
ra
=
5
60]
6.
59| >
—
=
7
158] >
[ 8|
57] +
L9|
56) >
10)
55] o
=
iL
54] <>
ay
= Ol +
13
ina
52) +
4)
[51] >
15
a
50] >
[26]
|
[49} <>
17)
~
[48] +
[18 |
47>
ca
st
so
i
i
Ao) ~
20!
45| >
=a
ome)
Eas
[21
44)
=
je
22
ae
13)
2
=
12]
(24
[41] +
25)
40) -
[26]
39] <
(27
[38] =
aa
a1 ~
29)
(36) =
(30|
135]
31
3a] -
32,
33) -
P20
P21
P22
P23
P24
P25
P26
P27
P0o
P01
PQe
PQs
P04
POs
POs
P07
Plo
Pli
Pls
Pl
Pls
Ple
Ply
Pdo
Po
Pde
POs
PSs
Pds
Pde
Po7
Grid 7
Grid 8
Grid 9
Grid 10
Grid 11
Grid 12
Grid 13
Grid 14
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Display
GND
GND
GN
GN
G
G
G
Uo
©
ND
ND
ND
GE-940
GE-940
inverter
input
7-2. Description of terminals
Pin No.| Pin name
Name
Description
Pin name
'|
os ™~ oO
Description
oY
Voc
+
Power supply
33
POT
+4.
POT
GND
4
Segment A8
Segment
34
P56
P96
GND
t
Segment A7
ani
Segment
39
P59
Po
GND
Oo;}o!;1ot;=—
Segment A6
Segment
36
t
Pod
Po4
Segment
Segment
Segment
Segment
37
POS
P53
GND
Segment
38
PO2
PO2
GND
Segment
39
Pol
| Pol
GND
Segment
Segment
40
P50
Invert
Display invert
input
Grid 6
Segment
4]
PIT
Segment
Segment
Al |
Grid
42
P16
Segment
=
Segment
~
Segment
Grid 5
Grid
43
P15
| Segment
Segment
Grid 4
Grid
44
Pl4
Segment
| See
Grid 3
Grid
45
P13
Segment
Segment
Segment
Grid 2
Grid
46
Segment
Segment
Grid |
47
Pll
| Segnent
Segment
HH
|H|o
LATCH OUT
| :
Segment A50 | Segment
Serial CLK
Serial SYNC
Serial DATA
Serial BUSY
Chip inable
7T4HC77 latch control
Segment C3
Fgacnent
48
P10
t
SIlOoOlol
oa]
Ol]
OG]
OES
| ad
atm
tet
ee]
Segment
Segment A1[6
Segment A15
Segment Al4
Segment A13
Segment Al2
OoO;o;o;yo;o;];o
Segment Al
Segment A10
Segment AQ"
o!1o
T
Segment
Segment
Segment
Segment
Segment
Segment
Segment
Segment
CE
Chip inable
| CNss
GND
RESET
RESET
Xin
Clock
Ole
lel
Rel
olo
Xour
Clock
Timing signal ¢ output
el
COLO}
ol}
o};]o;o;o|o
10
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