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HYCON HY12P User Manual

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HY12P Family
User's Guide
Digital Multimeter
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© 2015-2017 HYCON Technology Corp
UG-HY12S65-V05_EN
www.hycontek.com

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Summary of Contents for HYCON HY12P

  • Page 1 HY12P Family User’s Guide Digital Multimeter © 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN www.hycontek.com...

  • Page 2: Table Of Contents

    Register Description-Interrupt ......................42 HARDWARE MULTIPLIER ........................48 INPUT/OUTPUT PORT, I/O ........................49 7.1. PORT Related Register Introduction ....................50 7.2. Buzzer ..............................51 7.3. Input/Output Port 1, I/O Port1 ......................52 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page2...
  • Page 3 Example of Calculation ........................76 12.2. Register Description- Frequency Counter ................... 77 13. LCD ................................. 78 13.1. LCD Manual ............................79 13.2. LCD Output Waveform ........................82 13.3. Register Description -LCD ........................87 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page3...
  • Page 4 Analog Switch Network ........................118 17.6. DMM Comparator Network ....................... 126 17.7. Pre-Filter, ADC Input MUX and Temperature Sensor ............... 128 18. ΣΔADC, LOW PASS FILTER, RMS CONVERTER AND PEAK HOLD ..........131 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page4...
  • Page 5 19.6. 500K~50Mohm ..........................145 19.7. 5nF~500nF ............................146 19.8. 5uF~500uF ............................147 20. BUILD-IN EPROM ..........................148 20.1. BIE instruction ........................... 149 20.2. Register Description-BIE ........................152 21. REVISION RECORD ..........................153 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page5...

  • Page 6: Reading Guidance

    Digital Multimeter 1. Reading Guidance 1.1. About This User Guide Attention: 1、 HYCON Technology Corp. reserves the right to change the content of this datasheet without further notice. For most up-to-date information, please constantly visit our website: http://www.hycontek.com 2、 HYCON Technology Corp. is not responsible for problems caused by figures or application circuits narrated herein whose related industrial properties belong to third parties.

  • Page 7: Terms And Definition

    One Time Program-EPROM  Program Counter  PWM and PFD  SD18 Sigma-Delta ADC  Special Register  SRAM Static Random Access Memory  Stack  Watch Dog Timer  WREG Work Register 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page7...
  • Page 8 Hardware  set by Hardware  cleared by User  set by User  Not use  users are forbidden to change  unchanged  unknown  depends on condition 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page8...

  • Page 9: Cpu

     One instruction accomplished utmost 16-bit FSR register data movement and address 8KW program memory look-up-table instruction.  Data memory operation includes Program Counter (PC), Status Register (Status) and Stack Register (Stack) data movement.  Processor core is H08A core. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page9...

  • Page 10: Memory

    Memory Related Registers：(x：Means it constitutes several registers). PC[12:0] PCHSR[4:0],PCLATH[4:0],PCLATL[7:0] TOS[12:0] TOSH[4:0],TOSL[7:0] FSRx[8:0] FSRxH[8],FSRxL[7:0] INDFx INDF0[7:0],INDF1[7:0] POINCx POINC0[7:0], POINC1[7:0] PODECx PODEC0[7:0], PODEC1[7:0] PRINCx PRINC0[7:0], PRINC1[7:0] PLUSWx PLUSW0[7:0], PLUSW1[7:0] STKCN STKFL[0],STKOV[0],STKUN[0],STKPRT[2:0] PSTATUS SKERR[0] BSRCN BSR[0] 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page10...
  • Page 11 1 or 0 according to the written data type. Please be noticed that if the emulation software (HYIDE) compiling option has been configured the programming protection function, all data type will only be read as 0. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 12 To write PC[12:0], PCLATH[4:0] must be written first then to write PCLATL[7:0]. Any reverse order may result in incorrect data. Program memory address ability varies from every product scheme. Common capacities are 4KB (0xFFFh), 6KB (0x17FFh, HY12P65 emulation IC capacity). 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com...
  • Page 13 Digital Multimeter ORG 0000 JMP START ORG 0004H RETI START: ;jump to 0109h MVFF PCLATL,B1 PCLATH,F,ACCE MVL 2 ADDF B1,W,ACCE MVF PCLATL,F,ACCE ORG 0109H NOP ... Example 2-1 Read/Write PCLAT Example Program 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page13...
  • Page 14 Stack layer register, STKn：Every stack layer has the same length data register as that of top-of-stack register, TOS. When stack index STKPRT being designated, the content of data register will be sent to TOS. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 15 That is to say, whether to generate stack error reset signal must be determined at program developing stage. If reset is chosen, after IC on powered, SKRST [0] is set as 1, the opposite situation is set as 0. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 16 STKOV：Stack overflow flag 1：Happened 0：Not happened STKPRT[2:0]：Stack pointer register 110：the 6 layer 101：the 5 layer 000：the 0 layer, TOS[12:0]=0x0000h PCLATU/PCLATH/PCLATL：Program Counter, PC[12:0] PCLATH：PC[12:8] PCLATL：PC[7:0] PSTATUS：Status Register SKERR：Stack error generated reset flag 1：Happened 0：Not happened 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page16...
  • Page 17 Special Register I 128 byte 07Fh < 080h > General purpose RAM 128 byte 0FFh 100h General purpose RAM 128 byte 17Fh 180h < > Unused 1FFh Figure 2-4 Data Memory architecture diagram 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page17...
  • Page 18 “d” is data storage place after operation. d=0 is saved in WREG register, d=1 is saved in Data Memory Register. “a” is the designated memory operation segment；a=0 is operated in segment 0, a=1 is operated in designated segment of BSRCN[0]. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com...
  • Page 19 ; Put 0AAh into W > Unused MVF V1,1,1 ; Write W value into 1FFh 17 Fh address of Bank 1. Example 2-2 Relation between Segment Selector Example Program And Data Memory 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page19...
  • Page 20 Send back current FSR0[8:0] appointed address value. The register W value will be±128d. 2.2.2.3.3. General Purpose Register, GPR General purpose register, GPR is the free area for users to conduct data storage, operation, flag bit setup…etc. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page20...
  • Page 21 FSR1L[7:0]：Please refer to File Select Register, FSR and INDF description. WREG：Force Select Register WREG[7:0]：Please refer to Working Register, WREG description. BSRCN：Memory Segment Read/Write Control Register BSR[0]：Memory read/write segment pointer register 1: Segment 1, address 0x100h~0x1FFh. 0: Segment 0, address 0x000h~0x0FFh. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page21...
  • Page 22 BRGRL xxxx xxxx uuuu uuuu *,*,*,* *,*,*,* UART Transmit Register TXREG xxxx xxxx uuuu uuuu *,*,*,* *,*,*,* UART Receive Register RCREG xxxx xxxx uuuu uuuu r,r,r,r r,r,r,r Table 2-3 Data Memory List 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page22...
  • Page 23 80H ~ FFH GPR0 General Purpose Register as 128Byte xxxx xxxx uuuu uuuu *,*,*,* *,*,*,* General Purpose Register as 128Byte 100H~17FH GPR1 xxxx xxxx uuuu uuuu *,*,*,* *,*,*,* Table 2-4 Data Memory List (continued) 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page23...

  • Page 24: Oscillator, Clock Sources And Power Managed Modes

    Digital Multimeter 3. Oscillator, Clock Sources and Power Managed Modes HY12P Series has three clock sources, HAO, LPO and XT as shown in Table 3-1. Through clock sources controller register set-up, it helps to flexibly manage CPU and peripheral operating frequency. Moreover, it also appropriately adjusts IC’s consumed power as to reach the purpose of energy economy.
  • Page 25 “x”: ignore, resistor unit:Ω,capacitor unit: F Ceramic Crystal MCKCN1 Resonator Oscillator Configuration Symbol Frequency ENXT HSSEL 455Hz 32768Hz 4.0MHz 8.0MHz Table 3-6 Oscillator Optimized Capacitor Value and MCKCN1 Register Set Up 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page25...

  • Page 26: Cpu And Peripheral Circuit Clock Sources

    4.0MHz. Compared to external XT oscillator, internal HAO equips with fast Start-up and better anti-interference character, thus, HAO is called restated CPU operation clock source. When CPU of HY12P Series utilizes other oscillator as operating clock source, HAO oscillator can be turned off by setting ENHAO[0] as <0>. 3.1.3. LPO Oscillator LPO is internal low speed RC oscillator, the typical output frequency is 32KHz.
  • Page 27 ; LS_CK clock source is OSC_LPO ; Instruction cycle is INTR_CK=8M/2/4=1MHz ;Turn off internal OSC_HAO frequency source and switches to external oscillator for power-saving MCKCN1,1,0 Example 3-2 HS_DCK Outputs 4MHz (External Oscillator) Example Program 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page27...
  • Page 28 CPU Operation Frequency Instruction Operation Cycle HAO, LPO CPU_CK INST_CK HSS_CK 4MHz 4MHz HS_DCK 4MHz 2MHz LS_CK 32KHz 32KHz 125us HS_CK 4MHz 4MHz Table 3-7 HSS[1:0]=01b, CPU Operating Frequency and Instruction Execution Cycle 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page28...
  • Page 29 Digital Multimeter 3.2.3. CPU Clock Source Clock source of HY12P Series peripheral circuit are configured by different distribution controller and prescaler. The configuration will be fully illustrated in each peripheral unit; hence Figure 3-4 only presents the peripheral clock sources configuration.

  • Page 30: Register Description-Operating Clock Source Controller

    HSCK：Control bit of high speed clock source selector When ENXT = 1 1：OSC_XT 0：OSC_HAO When ENXT = 0 1：Cannot be configured 0：OSC_HAO ENXT：Control bit of starting external crystal/resonator 1：Active 0：Inactive ENHAO：Control bit of starting internal HAO (4MHz) 1：Active 0：Inactive 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page30...
  • Page 31 PT2.1：Control bit of external pins 1：high potential 0：low potential PT2.0：Control bit of external pins 1：high potential 0：low potential TRISC2：Input/Output Control Register TC2.1：Input/output control bit of external pins 1：output 0：input TC2.0：Input/output control bit of external pins 1：output 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page31...
  • Page 32 HY12S65 User’s Guide Digital Multimeter 0：input PT2PU：Pull-Up Resistor Control Register PU2.1：Pull-up resistor control bit of external pins 1：Start 0：Shutoff PU2.0：Pull-up resistor control bit of external pins 1：Start 0：Shutoff 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page32...

  • Page 33: Power Managed And Operation Mode

    HY12S65 User’s Guide Digital Multimeter 3.4. Power Managed and Operation Mode HY12P Series CPU provides three operating modes for users to acquire the best managed circumstance between operating efficiency and power economy. These modes are run mode, idle mode and sleep mode.
  • Page 34 ；Configuration can base on both PT1 and PT2 at the same time. INTF1, 0, ACCE 10000001B ；Set external interrupt PT1.0 to enable INTE1, F, ACCE IDLE Example 3-4 Idle Mode Example Program 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page34...
  • Page 35 ；Set PT2 PULL UP CLRF TRISC2 SETF PT2PU ；Set PT3 PULL UP CLRF TRISC3 11000010b PT3PU,F,ACCE INTF1, 0, ACCE 10000001B ；Set external interrupt PT1.0 to enable INTE1, F, ACCE Example 3-5 Sleep Mode Example Program 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page35...

  • Page 36: Reset

    HY12S65 User’s Guide Digital Multimeter 4. RESET HY12P Series reset circuit includes the following four events to trigger reset signal. Reset block diagram is as Figure 4-1.  Power interference reset.  External reset input pin.  watch dog timer reset.

  • Page 37: Reset Events Description

    When BOR reset occurred, BOR[0] flag of register PSTATUS[7:0] will be configured as <1> to record the occurred event. BOR circuit of HY12P Series will generate approximately lower than 1uA current consumption; there is no other program or configuration methods can shut it off.

  • Page 38: Status Registers

    IC operating status is displayed in reset register, PSTATUS [7:0]; the interrelation is indicated in Table 4-2. “0”：not happened, “1”：happened, “u”：unchanged, “-”：unused Name/Status Address PSTATUS 02CH IDLEB SKERR Hardware Reset (A-RESET) Software Reset (I-RESET) SKERR Table 4-10 Interrelation of Reset Status Flags 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page38...
  • Page 39 T1:2048 oscillation delay cycle, using LPO(32KHz) clock source. T2:1024 oscillation delay cycle, using HAO(4MHz) clock source. Two signals will be generated after WDT ceased, please refer to Watch Dog, WDT chapter for detailed instruction description. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 40 0：Cleared through BOR, RST or instruction BOR：Power interference reset flag 1：Set up <1> to operate BOR 0：Cleared through instruction SKERR：Stack error reset flag 1：Stack error set up <1> 0：Cleared through BOR, RST or instruction 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page40...

  • Page 41: Interrupt

    RETI can be applied directly. At this time, GIE [0] will automatically be set up as <1>. Moreover, if return instruction RET is conducted, GIE[0] status will remain as 0. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...

  • Page 42: Register Description-Interrupt

    WDTIE[0]：Watch Dog interrupt event starting controller 1：Start (WDT) 0：Shutoff E1IE[0]：Interrupt event starting controller of input pin 1 1：Start (external input pin, PT1.1) 0：Shutoff E0IE[0]：Interrupt event starting controller of input pin 0 1：Start (external input pin, PT1.0) 0：Shutoff 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page42...
  • Page 43 0：Shutoff RMSIE[0]：True RMS interrupt event starting controller 1：Start 0：Shutoff LPFIE[0]：Low Pass Filter interrupt event starting controller 1：Start 0：Shutoff AD1IE[0]：ADC interrupt event starting controller 1：Start 0：Shutoff CTIE[0]：CONTER interrupt event starting controller 1：Start 0：Shutoff 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page43...
  • Page 44 1：Start (External input pin, PT2.5) 0：Shutoff E26IE[0]：Interrupt event starting controller of input pin 6 1：Start (External input pin, PT2.6) 0：Shutoff E27IE[0]：Interrupt event starting controller of input pin 7 1：Start (External input pin, PT2.7) 0：Shutoff 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page44...
  • Page 45 1：Happened (WDT) 0：Not happened E1IF[0]：Interrupt event flag of input pin 1 1：Happened (External input pin, PT1.1) 0：Not happened E0IF[0]：Interrupt event flag of input pin 0 1：Happened (External input pin, PT1.0) 0：Not happened 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page45...
  • Page 46 0：Not happened RMSIF[0]：True RMS interrupt event flag 1：Happened 0：Not happened LPFIF[0]：Low Pass Filter interrupt event flag 1：Happened 0：Not happened AD1IF[0]：ADC interrupt event flag 1：Happened 0：Not happened CTIF[0]：COUNTER interrupt event flag 1：Happened 0：Not happened 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page46...
  • Page 47 1：Happened (External input pin, PT2.5) 0：Not happened E26IF[0]：Interrupt event flag of input pin 6 1：Happened (External input pin, PT2.6) 0：Not happened E27IF[0]：Interrupt event flag of input pin 7 1：Happened (External input pin, PT2.7) 0：Not happened 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page47...

  • Page 48: Hardware Multiplier

    ；7Fh x FFh = 7Fh x ( 0FFh – 100h ) ； = 7Fh x 0FFh – 7Fh x 100h ； = 7E81h – 7F00h ； = FF81h Example 6-4 Signed Value Operation 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page48...

  • Page 49: Input/Output Port, I/O

    PU1[7:0], PU2[7:0], PU3[7:5] PM1[7:4], INTEG1[1:0], INTEG0[1:0], PM2[1:0] 1≦n≦3, n = Port PUn.x 0≦x≦7, x = Pin DAn.x Digital Input PTn.x DAn.x Analog Input PMn.x[1:0] TCn.x Digital Output Figure 7-12 Block Diagram of I/O Frame 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page49...

  • Page 50: Port Related Register Introduction

    PT1[1:0] first then start INTEGx[1:0]=10b or 11b mode (0≦x≦1). When the pins, PT1.0/PT1.1 are detected to rising edge, the interrupt signals will be appeared. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...

  • Page 51: Buzzer

    7.2. Buzzer BZ can produce several different frequencies to drive external buzzer. BZ operating frequency prescaler, BZS[2:0] can set diverse output frequency. BZS[2:0] Pre-scaler PER_CK 1,2,4,8,16,32, 64,128 Figure 7-13 BZ Block Diagram 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page51...

  • Page 52: Input/Output Port 1, I/O Port1

    EUART communication interface TX pin PT1.5 Digital input/output pin PT1.6 Digital input/output pin PT1.7 Digital input/output pin Buzzer output pin PSDO OTP programming pin, PSDO Set at PT1PU[7:0]=00h Table 7-14 PORT1 Function 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page52...
  • Page 53 10：Potential conversion (0→1 or 1→0) 01：Rising edge (0→1) 00：Falling edge (1→0) INTEG0[1:0]：PT1.0 Interrupt signal generated conditions 11：Potential conversion ( 0→1 or 1→0 ) 10：Potential conversion ( 0→1 or 1→0 ) 01：Rising edge (0→1) 00：Falling edge (1→0) 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page53...

  • Page 54: Input/Output Port 2, I/O Port2

    Digital input/output pin INT26 Interrupt source input pin CMP2 Comparator input interface pin PT2.7 Digital input/output pin INT27 Interrupt source input pin CMP3 Comparator input interface pin Set at PT2PU[7:0]=00h Table 7-16 PORT2 Function 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page54...
  • Page 55 DA2.x：External analog/digital input signal pin control bit（3≦x≦7） 1：Analog 0：Digital PM2.2[1:0]：PT2.2 output mode control bit 11：Reserved 10：Timer C PWM output starts. 01：Timer C PFD output starts. 00：Shutoff PT2PU：Pull-Up Resistor Control Register PU2.x：External pull-up resistor pin control bi（0≦x≦7） 1：Start 0：Shutoff 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page55...

  • Page 56: Input/Output Port 3 , I/O Port3

    Buffer PT3.5 Digital input/output pin Analog channels input pin PT3.6 Digital input/output pin Frequency counting input pin PT3.7 Digital input/output pin CMPO Comparator output pin Set at PT3PU[7:5]=000b Table 7-18 PORT3 Function 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page56...
  • Page 57 TC3.x：External pin input/output control bit（5≦x≦7） 1：Output 0：Input PT3PU：Pull-Up Resistor Control Register PU3.x：External pull-up resistor pin control bit（5≦x≦7） 1：Start 0：Shutoff PM3.7：PT3.7 CMPO output control bit 1：Start 0：Shutoff DA3.5：PT3.5 External analog/digital input signal pin control bit 0：Analog1：Digital 0：Analog 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page57...

  • Page 58: Watch Dog Timer, Wdt

    WDT uses internal clock source, LPO. It can be operated under Run Mode and Idle Mode. Under Run Mode, WDT can be zeroed by software as to avoid IC reset. However, WDT cannot be zeroed by any means under Idle Mode. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 59 ；Zero WDT CWDT ；Enter into Idle Mode. IDLE …. ；Interrupt Service Program Idle Interrupt： ；Clear WDT Interrupt event flag BCF INTF1,WDTIF,0 …. ；Interrupt service return RETI Example 8-6 WDT Interrupt Event Example Program 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page59...

  • Page 60: Register Description-Wdt

    PSTATUS：Please refer to RESET Chapter TMACN：Timer-A Control Register ENWDT：WDT Starting Controller 1：Start 0：Shutoff； （cannot be configured <0> through software） WDTS[2:0]：Configure WDT overflow time 111：F /32768 110：F /8192 101：F /2048 100：F /512 011：F /128 010：F 001：F 000：F 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page60...

  • Page 61: Timer-A

    The next time interrupt occurs TMAR[7:0]=00001000b。 So, every time interrupt occurs TMAR[7:0]=TMAR[7:0]+4. Configure TMAS[1:0]=10b, when TMAR[7:0]=01000000b, first interrupt occurs, The next time interrupt occurs TMAR[7:0]=10000000b。 So, every time interrupt occurs TMAR[7:0]=TMAR[7:0]+64. Figure 9-15 Timer-A Block Diagram 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page61...

  • Page 62: Tma Manual

    ；Whether interrupt event service is started TMAR=TMAR+16 ；Interrupt service return RETI Example 9-7 TM A Interrupt Event Example Program During counting, TMAS[1:0] overflow generated time may lead to TMA mis-action, users must use with extra attention. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page62...

  • Page 63: Register Description -Tma

    / 256；Every overflow occurs interrupt event, TMAR[7:0]=TMAR[7:0]+256 10：F / 64；Every overflow occurs interrupt event, TMAR[7:0]=TMAR[7:0]+64 01：F / 16；Every overflow occurs interrupt event, TMAR[7:0]=TMAR[7:0]+16 00：F / 4；Every overflow occurs interrupt event, TMAR[7:0]=TMAR[7:0]+4 TMAR：TMA ascending counter, readable but not writable 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page63...

  • Page 64: Timer-C

    Compare TMCR Match Clean TMCCK[1:0] TMCC PRC_CK Digital Input Comparator TMCR TMCS0_CK TCn.x/DAn.x TMC_CP Data Bus Note: PWM just work at TMCCK=00 mode (clock source = INTR_CK) Figure 10-16 Timer-C Block Diagram 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page64...

  • Page 65: Timer-C Manual

    For detail register description, please refer to Input/Output Port, I/O Chapter. TMCR[7:0] only can be read, any writing action to TMCR[7:0] or TMCCN[7:0] will be deemed as zeroing counter, TMCR[7:0] and the value of prescaler and postscaler will be zeroed as well. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...

  • Page 66: Register Description -Tmc

    PWM / PDF description TMCR：Timer C Counter Ascending counter of Timer-C that is can only read. Any write in action to TMCR[7:0] or TMCCN[7:0] will be deemed as zeroing TMCR[7:0]. PRC：Frequency Control Register 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page66...
  • Page 67 HY12S65 User’s Guide Digital Multimeter Frequency controller of Timer-C, TMC_CP will contrast the content of TMCR[7:0] and PRC[7:], when the value is in equality, reversed PRC_CK status. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page67...

  • Page 68: Frequency Generator, Pwm/Pfd

    TMC_CK INTR_CK Compare TMCR Match Clean TMCCK[1:0] TMCC PRC_CK Digital Input Comparator TMCR TMCS0_CK TCn.x/DAn.x TMC_CP Data Bus Note: PWM just work at TMCCK=00 mode (clock source = INTR_CK) Timer-C Block Diagram 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page68...

  • Page 69: Pfd Mode Manual

    BSF PWMCN,ENPFD,0 PFD Mode must correctly configure I/O PORT setup while using or the signal may not be output and PFD Mode will have abnormal function. Detailed description please refers to Input/Output Port, I/O Chapter. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...

  • Page 70: Pwm Mode Manual

    PWM Mode must correctly configure PORT related configuration while using, or the signal may not be output and PFD Mode will have abnormal function. Detailed register description please refer to Input/Output Port, I/O Chapter. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 71 When PWM is in operating status, PWMR will show the written value until the end of this period. If PWMR value is bigger than PRC value, PWMx output pin will not be configured as 0. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 72 Under this configuration, 4 prescaling arguments of TMCS0[1:0] configuration can be used. Configure TMCCK[1:0] as <01>, LS_CK provides operating frequency to TMC. Under this configuration, only TMCS0[1:0] <11> is applicable. Detailed description please refers to Register Description-TMC Chapter. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com...
  • Page 73 ；high duty percentage=49.61% PWMCN,5,0 PWMCN,4,0 084h ；Start TMC, configure operating frequency as INTR_CK, TMCCN,1,0 ；do not prescale but postscale configurated TMCS1[2:0] = 001b ；Start PWM 0B0H PWMCN,1,0 Example 11-2 PWM Output Example Program 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page73...

  • Page 74: Register Description-Pfd/Pwm

    1：Hardware automatically configures PASF as 0. PWMx modulated output will restart in next period. 0：Users employ software to configure PASF as 0. PWMx modulated output will restart in next period PWMR：PWM Duty Cycle High Bit Register PWM duty cycle high byte [9:2] 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com...

  • Page 75: Frequency Counter, Cnt And Cmp Pin

    Standby signal, Duty Cycle=CTC<23:0>/[1000000h-CTA<23:0> + CTA<23:0> Initial Final Within it, F is the frequency of SYSCLK, CTA<23:0> is the value before SYSCLK Initial count operated. CTA<23:0> is the value occurred after count operated. Final 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page75...

  • Page 76: Example Of Calculation

    =(1000000h-C00000h +000760h)/3D0900h --- >hexadecimal =(16777216-12582912+1888)/4000000=1.0490 --- >decimal Standby signals frequency: Freq = CTB<23:0>/T = 1049/1.0490=1000 Hz Standby signal, Duty Cycle: Duty Cycle = CTC<23:0>/[1000000h-CTA<23:0>Initial + CTA<23:0>Final] = 20043Ah/400760h --- >hexadecimal = 2098234/4196192=0.5=50% --- >decimal 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page76...

  • Page 77: Register Description- Frequency Counter

    CTF: CTF is the flag of Frequency Counter events occurred. The signals will be sent in INTF register. ENPCMPO: PT3PU[PM3.7] register bit, can enable CMPO Pin if output by PT3.7. 1=Enable; 0=Disable. Configure CMPO is output by PT3.7 and need to configure PT3.7 is output as well. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...

  • Page 78: Lcd

    Selectable input clock source and output frequency  Equips with Blinking capability LCD Registers： LCDCN1 ENLCD[0],LCDPR[0] ,VLCDX[1:0],LCDBF[0],LCDBI[1:0] LCDCN2 LCDBL[0],LCDMX[1:0] LCD[159:0] LCD0[7:0]~ LCD6[7:0], LCD7[3:0] VLCD LCDPR[0] SEGn VLCD COMn Figure 13-18 LCD Block Diagram 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page78...

  • Page 79: Lcd Manual

    LCDS_CK / 4 Figure 13-19 LCD Operating Frequency and Frame Frequency LCDS[2:0] PERA_CK=1953Hz (PERCK[0]=1b, PERA_CK~4MHz/2/32/32) LCDS_CK 1953 Static, LCDMX[1:0]=00 2-MUX, LCDMX[1:0]=01 Frame Frequency 3-MUX, LCDMX[1:0]=10 4-MUX, LCDMX[1:0]=11 Unit：Hz Table 13-24 LCD Operating Frequency Configuration 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page79...
  • Page 80 SEGn[3:0] 4-bit is valid. Besides, if output waveform is 2-mux, only the lowest SEGn[3:0] 2-bit is valid. Because of the valid and invalid characteristic, LCD0 and LCD1 digit register has SEG0[3:0] and SEG1[3:0] multiplexed design. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 81 ;1/3 bias, LCD start. Initiating LCD charge pump power VLCD=3V CALL DELAY ;LCD charge pump power regulated time (at VLCD CAP-4.7uF) ;VDD=2.2V, VLCD=3V, Stable time ~ 85msec ;VDD=3.6V, VLCD=3V, Stable time ~ 15msec Example 13-10 LCD Example Program 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page81...

  • Page 82: Lcd Output Waveform

    SEG7 SEG9 SEG2 Model Bias: Static Duty: 1/1 SEG3 COM0-SEG2 COM0-SEG3 SEG3 COM0 COM0 SEG5 COM1 SEG7 SEG9 Model SEG2 Bias: Static Duty: 1/2 SEG3 COM0-SEG2 COM0-SEG3 Figure 13-20(a) Output Waveform-Static Operation 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page82...
  • Page 83 SEG9 COM2 Model Bias: Static Duty: 1/3 SEG2 SEG3 COM0-SEG2 COM0-SEG3 SEG3 COM0 COM0 SEG5 SEG2 SEG7 SEG9 Model SEG3 Bias: Static Duty: 1/4 COM0-SEG2 COM0-SEG3 Figure 13-3(b) Output Waveform-Static Operation (continued) 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page83...
  • Page 84 HY12S65 User’s Guide Digital Multimeter SEG3 COM0 COM0 SEG5 COM1 SEG7 SEG9 SEG2 Model Bias: 1/3 SEG3 Duty: 1/2 COM0-SEG2 - V1 - V2 COM0-SEG3 - V1 - V2 Figure 13-21 Output Waveform -2-Mux 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page84...
  • Page 85 HY12S65 User’s Guide Digital Multimeter SEG3 COM0 COM0 SEG5 COM1 SEG7 SEG9 COM2 Model Bias: 1/3 SEG2 Duty: 1/3 SEG3 COM0-SEG2 COM0-SEG3 Figure 13-22 Output Waveform-3-Mux 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page85...
  • Page 86 HY12S65 User’s Guide Digital Multimeter SEG3 COM0 COM0 SEG5 COM1 SEG7 SEG9 COM2 Model COM3 Bias: 1/3 Duty: 1/4 SEG2 SEG3 COM0-SEN2 COM0-SEN3 Figure 13-23 Output Waveform-4-Mux 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page86...

  • Page 87: Register Description -Lcd

    VLCDX[1:0]：Charge pump voltage state select controller 11：VLCD = 2.55V。 10：VLCD = 2.8V。 01：VLCD = 3.05V。 00：VLCD = 3.3V。 LCDBF：LCD output buffer 1：Start 0：Shutoff LCDBI[1:0]：LCD waveform bias controller 11：Unused 10：1/3 bias 01：Reserved 00：Static operation 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page87...
  • Page 88 LCDCN2：LCD Control Register 2 LCDBL：LCD digit blink controller 1：LCD digit off 0：LCD digit display LCDMX[1:0]：LCD Waveform output controller 00：Static status (COM0)。 01：1/2 duty (COM0,COM1)。 10：1/3 duty (COM0,COM1,COM2)。 11：1/4 duty (COM0,COM1,COM2,COM3) LCD0~LCD7：LCD Digit Data Register 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page88...

  • Page 89: Enhanced Universal Asynchronous Receiver Transmitter

    Frame error detection (FERR)：UART does not receive the initial bit that usually aroused from the noise on signal line. UART cannot ontain correct data from shift register. Overflow error detection (OERR)：The latest data has covered the previous data. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...

  • Page 90: Euart Manual

     Read RCREG register to obtain the received 8 bit data.  Read whether the FERR bit of URSTA register is configured. Make sure if the read data is wrong. FERR can be cleared through ENCR bit. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...

  • Page 91: Baud Rate Generator, Brg

    Example 14-1 illustrated the calculation of Baud Rate Error. BRG/EUART MODE Baud Rate Equation 13 bit/ asynchrony CPU_CK÷[4 (n + 1)] CPU_CK= operating frequency； n = BRGRH:BRGRL register correct value Table 14-26 Baud Rate Equation 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page91...
  • Page 92 00000H, auto baud rate flag, ABDOVF[0] will be placed 1. Users can clear ABDOVF[0] by instruction or through configure ENABD[0] as 0 to make ABDOVF[0] to be 0. After ABDOVF[0] is set up as 1, ENABD[0] status will remain as 1. Please refer to Figure 14-2. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 93 BRG Overflow Sequence BRG Clock edge #1 RC pin Start bit 0 bit 1 Set by user ENABD bit ABDOVF bit BRG Value xxxxh 0000h 0000h Figure 14-25 Auto Baud Rate Overflow (ABDOVF) Waveform 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page93...

  • Page 94: Hardware Parity Check

    Moreover, the EUART transmits and receives the last LSB. The transmitter and receiver are functionally independent but use the same data format and baud rate. Parity is supported by hardware and can be stored as the 9 data bit. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com...
  • Page 95 TXREG register. TXIF is cleared in the second instruction period following the load instruction. TXIF will be configured as 1 again when Stop bit occurred. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 96 Exclusive OR PARITY[0] TXREG Register TX9D TX9D[0] TX9[0] ENADD[0] Interrupt TXIE[0] TXIF Buffer ENTX[0] ………… TX pin Control TSR Register TRMT[0] BRGRH BRGRL Baud Rate Generator Figure 14-26 EUART Transmission Block Diagram 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page96...
  • Page 97 When receiving data, hardware will conducts the received 8 bit data exclusive or. If RC9 is set as 1, the received RC9D data (9 bit) will be calculated by exclusive or. After 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 98 Recover RSR Register ENSP[0] RX9D[0] RX9[0] Exclusive OR BRGRH BRGRL Baud Rate Generator PARITY[0] PERR[0] RX9D Interrupt Overflow RXREG Register FIFO RXIF[0] RXIE[0] Data Bus Figure 14-30 EUART 9-bits Receive Block Diagram 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page98...
  • Page 99 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CPU_CK Auto cleared Bit set by user RC pin RXIF Cleared due to user read of RXREG Note： The EUART remains in Idle while the WUE bit is set. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page99...
  • Page 100 RCIDL bit to verify that a receive operation is not in progress. If a receive operation is not executed, the WUE can be placed 1, forcing the IC entering the Sleep mode. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 101 ；Move the received data to BUF0 register MVFF RCREG,BUF0 ；Move the 9 MVFF URSTA,BUF1 received data to BUF1 register …. ；Return from interrupt RETI ；Data receive error loop FAIL_LOOP: Figure 14-34 EUART Example Program 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page101...

  • Page 102: Register Description-Euart

    PU1.4 PU1.3 0000 0000 0000 0000 *,*,*,* *,*,*,* PT1M1 PM1.4 0000 0000 0000 0000 *,*,*,* *,*,*,* Table 14-28 EUART Register INTE1/INTE2/INTF2：Please refer to Interrupt Chapter. PT1/TRISC1/PT1PU/PT1M1：Please refer to Input/Output Port, I/O Chapter. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page102...
  • Page 103 RC9D：Receiving the ninth bit data 1：Data is”1” 0：Data is”0” PERR：Data parity check result flag 1：Receiving parity check error 0：Receiving parity check correctness FERR：Incomplete UART data receiving (start, 8(9) bit data, end) flag 1：Represents incomplete data 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page103...
  • Page 104 RCIDL：Response whether it is in receiving status flag 1：In receiving status 0：Not in receiving status TRMT：Represents transmission register (TSR) status flag 1：Represents TSR register is empty 0：Represents TSR register has data ABDOVF：Auto Baud Rate overstate flag 1：Happened 0：Not happened 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page104...
  • Page 105 1：High potential flag or high potential output. 0：Low potential flag or low potential output. TRISC1: Input/output control register TC1.4：External pin input/output control bit 4 1：Output 0：Input TC1.3：External pin input/output control bit 3 1：Output 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page105...
  • Page 106 PU1.4：External pin pull up resistor control bit 4 1：Enable 0：Disable PU1.3：External pin pull up resistor control bit 3 1：Enable 0：Disable PT1M1: Digital output mode select register PM1.4：PT1.4 EUART TX output control bit 1：Enable 0：Disable 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page106...

  • Page 107: Multi-Function Comparator

    1.2V to constitute 2~3.3V low battery voltage determination. Comparing external input to internal 1.2V can form an external comparator of low battery voltage detection. Moreover, comparing external input pins (PT2.4~PT2.7) to VDD divide voltage to form a simple 4 bits ADC. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com...

  • Page 108: Scan Key Description

    8 ranges as to avoid VDD power noise and comparator noise). When in sleep mode, PT2.7 can be set as output low to deduce power consumption. 15.2. Example Program To be provided. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com...

  • Page 109: Register Description- Multi-Function Comparator

    SVIN: VDD is 4 Bits divide power mode (must configure: VSL, VJ1, VJ2=110) SVIN<3:0> SVIN 16/16VDD 15/16VDD 14/16VDD 13/16VDD 12/16VDD 11/16VDD 10/16VDD 9/16VDD SVIN<3:0> 1000 1001 1010 1011 1100 1101 1110 1111 SVIN 8/16VDD 7/16VDD 6/16VDD 5/16VDD 4/16VDD 3/16VDD 2/16VDD 1/16VDD 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page109...

  • Page 110: Low Power Voltage Detection Description

    If it is set as external input, users may need to design divide voltage circuit to produce proper voltage signal and input via LVDIN pin to LVD comparator. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...

  • Page 111: Charge Pump Regulator And Vdda Ldo

    VGG connects to1~10μF capacitor for power regulator. VDDA LDO input power source is VGG; VDDA output can be regulated at 2.4V to 3.6V by program. VDDA must connect to 1μF capacitor for power regulator. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...

  • Page 112: Register Description- Charge Pump Regulator

    16.2. Power on Example Program Example code： 11000000b ;Configure MCUBIAS，enable Charge pump regulator PWRCN2,F,A 11111100b ；Configure DMMBIAS，AGND voltage selection 0.5xVDDA，enable Voltage ; Reference Generator，Enable VDDA LDO, LDO output voltage selection 3.6V PWRCN,F,A 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page112...

  • Page 113: Auto Range Dmm Multi-Function Network

    AGND Auto Range DMM Multi-Function Network includes Voltage Reference Generator, Analog Switch Network, DMM Comparator Network and Pre-Filter, ADC Input MUX and Temperature Sensor. Detailed description will be separately given in below. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page113...

  • Page 114: Voltage Reference Generator (Vrg)

    Voltage reference generator (VRG) produces different voltage reference for ADC and Comparator usage. VDS<17:1> is the divided voltage that resulted from VDDA-VSS while AGNDP<9:0> and AGNDN<9:1> are the divided voltage that resulted from +/-REFO-VSS. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com...
  • Page 115 VDSC<N> is the node that generated from dividing (VDDA,VSS) voltage, AGNDP<N> is the node that generated from dividing (REFO,AGND) voltage and AGNDN<N> is the node that generated from dividing (-REFO,AGND) voltage. All relative voltage is listed in below. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 116 0：Disable, REFO pin is in floating state ADCN1: SDIO：Short control bit of PB<0> and PB<2> 0：Open 1：Short SREFO：Register bit, can select REFO Buffer input source 0：Select internal Band-gap Voltage Reference 1：Select PB<4> pin 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page116...

  • Page 117: Power System

    AGND is then configured as 0.1 VDDA. (AGND-VSS)=K3(VDDA-VSS) SAGND<1:0> Function Resistance Diode Capacitance/V/A 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page117...

  • Page 118: Example Program

    Analog Switch Network provides auto range switch for voltage/resistor/capacitor/diode measurement switching circuit. Nodes signal, including FB, SENSE, RLU, RLD are generated after switching and output to ADC or Comparator Network. Measurement mode is primarily selected by SMODE[7:0]. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com...
  • Page 119 SMODE<7:0> PAX6: PS6：PA<6> Power select control bit 1：Connect 0：Disconnect DS6：PA<6> OP3 output select control bit 1：Connect 0：Disconnect FS6：PA<6> Feedback select control bit 1：Connect 0：Disconnect SS6：PA<6> Sense end select control bit 1：Connect 0：Disconnect 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page119...
  • Page 120 SS5：PA<5> Sense select control bit 1：Connect 0：Disconnect PS4：PA<4> Power select control bit 1：Connect 0：Disconnect DS4：PA<4> OP3 select control bit 1：Connect 0：Disconnect FS4：PA<4> Feedback select control bit 1：Connect 0：Disconnect SS4：PA<4> Sense end select control bit 1：Connect 0：Disconnect 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page120...
  • Page 121 SS3：PA<3>Sense end select control bit 1：Connect 0：Disconnect PS2：PA<2> Power select control bit 1：Connect 0：Disconnect DS2：PA<2> OP3 output select control bit 1：Connect 0：Disconnect FS2：PA<2> Feedback select control bit 1：Connect 0：Disconnect SS2：PA<2>Sense select control bit 1：Connect 0：Disconnect 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page121...
  • Page 122 1：Connect 0：Disconnect PS0：PA<0> Power select control bit 1：Connect 0：Disconnect DS0：PA<0> OP3 output select control bit 1：Connect 0：Disconnect FS0：PA<0> Feedback select control bit 1：Connect 0：Disconnect SS0：PA<0> Sense end select control bit 1：Connect 0：Disconnect 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page122...
  • Page 123 X 1 0 1 1 1 AGNDN<7> X 1 1 0 1 0 AGNDP<6> X 1 1 0 1 1 AGNDN<6> X 1 1 1 1 0 AGNDP<0> X 1 1 1 1 1 PB<5> 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page123...
  • Page 124 1 1 0 X 1 1 0 0 1 0 0 0 1 1 1 X 0 0 1 0 0 1 1 0 1 1 1 X 1 0 0 1 0 1 0 1 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page124...
  • Page 125 SGND AGND PA<6> PA<N> SVSO1 Sense 1.111M RN-1 PA<5> PA<N-1> Sense SMODE<5> SMODE<5> AGND AGND PTC + 100 PTC + 100 SMODE<7> SMODE<7> VDDA VDDA Diode Driver and Divider Reference Resistor Measure 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page125...

  • Page 126: Dmm Comparator Network

    CMPO is the output of window comparator while CMPHO and CMPLO are output of CMPH and CMPL comparator respectively. Comparator Network is mainly used to measure frequency, test short circuit and measure capacitor range. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com...
  • Page 127 1100 1101 1110 1111 VRLCMP AGNDN<6> AGNDN<5> AGNDN<4> AGNDN<3> AGNDN<2> AGNDN<1> AGNDP<0> AGNDP<1> SCMPI<2:0> INCMP SENSE PB<2> PB<0> PB<1> PB<3> PB<4> (3) ENCMP：Register bit, can enable CMPH and CMPL comparator. 1=Enable, 0=Disable. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page127...

  • Page 128: Pre-Filter, Adc Input Mux And Temperature Sensor

    Input signal and reference signal of ADC are connected by MUX. ADC preamplifier can bypass Pre-filter through selection. Additionally, the chip has a built-in Temperature Sensor that helps to measure chip temperature through ADC measurement. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN ©...
  • Page 129 SADRH and SADRL：ADC positive/negative signal reference that commonly controlled by register bit SAD1RH<2:0> and SAD1RL<2:0>. SAD1I<1:0> AD1IP ADFP TS1P TS1N AD1IN ADFN TS2N TS2P SAD1RH<2:0> SADFRP REFO VREF PB<4> AGND SAD1RL<2:0> SADFRN AGND PB<3> PB<5> VREF 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page129...
  • Page 130 Temperature curve slope, G can be gained as follows: TCode@25 is offset, about 8 273.15 ℃, then we can gained: Supposed that the temperature-to-be-measured is T TCode@T − 273.15 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page130...

  • Page 131: Σδadc, Low Pass Filter, Rms Converter And Peak Hold

    ADSFN SAD1FN<2:0> RSLPF LPFBW<1:0> 2nd Order i l t RSTCOMB Comb Filter LPF<18:0> AD1OSR[2:0] ENSQRE ENSQRE RSRMS 1bit 19bit AD1<18:0> X * X ENRMS ENPKH [37:0] ADCIF Peak PKHMAX<18:0> Interrupt Hold PKHMIN<18:0> 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page131...

  • Page 132: Register Data Synchronization

    ADC of HY12P65 comprises four parts, Input/VR Buffer and Chopper Control, Gain Stage, Modulator and three-stage Comb Filter. ADIP and ADIN are positive/negative input signal while SAD1RH and SAD1RL are positive/negative reference signal. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com...
  • Page 133 ADCCK. When OSR1=0xx, ADC is under fast ADCLK ADCLK output mode. HSAD=1 and AD1CHOP=0x must be configured. In different OSR configurations, the maximum output value of ADC output code (Comb Filter Gain Factor) will be different as follows: 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page133...
  • Page 134 (12) AD1DATA<18:0>：ADC data output register, total 19 bits. (13) AD1IF：Flag for ADC event occurrence; this signal will be sent to INTF register. (14) RSTCOMB：Reset Comb Filter. <0>Clear; Write "0" must be written back to "1". <1>Normal. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page134...

  • Page 135: Suggested Configurations For Dmm Application

    ADIG ADRG ADC Gain VREF Measurement Range DC/AC 500mV, DC/ACV,DC/AC 10A, 500mA, (REFO,AGND) 5000uA, Diode DC/AC 50mV , DC/AC 5A, 0.33 10.8 (REFO(AGND) 50mA, 500uA 500/5k/50k OHM (RLU,FB) 500k/5M/50M OHM 0.33 (VDDA,VSS) 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page135...
  • Page 136 When switching ranges, users need to wait until the analog filter was stabilized. Additionally, RSTCOMB bit can be used to reset comb filter as to gain accurate output by waiting for the second ADC data. The sequence is as follows: 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com...
  • Page 137 ADC Data Output ADC IRQ ADC N Data=(N+(N-1))/2 ADC N+1 Data=((N+1)+N)/2 Range Change & Analog Filter Settle COMBRST ADCHOP=1x Dout-Doff Dout+Doff ADC Data Output ADC IRQ ADC 1 Data= (0+Dout-Doff)/2 ADC 2 Data= ((Dout-Doff)+Dout+Doff))/2 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page137...

  • Page 138: Peak Hold

    Low Pass Filter to gain RMS<37:0> output. For true RMS value measurement, MCU is required to implement radical. The output time sequence is as follows: LPFBW*OSR/400k RMS Output Data RMS N Data RMS N+1 Data RMS N+2 Data 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page138...
  • Page 139 RMSIF：Flag bit of RMS Converter event; this signal will be sent to INTF register. ∑ < >= (5) ENSQRE: ”1” will display ∑ < >= ”0” will display (6 ) RSRMS：Reset RMS Low Pass Filter。 <0>Clear; Write "0" must be written back to "1". <1>Normal. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page139...

  • Page 140: Dmm Range Application Example

    AGND 100n DC500mV Function AGND AD1OSR=111 400khz/20000/2=10hz VOLT Modulator AD1IP AD1<18:0> PTC+100 100k Test Gain x 0.9 inside AD1F AD1IN VRGain x 1 AGND= 0.5*VDDA AD1RH AD1RL HY12P65 AGND REFO AGND 100n 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page140...

  • Page 141: Ac Mv

    AGND AD1OSR=000 400khz/32=12.5khz VOLT Modulator AD1<18:0> AD1IP LPFBW=10 12.5khz/1024=12.2hz PTC+100 Test Gain x 0.9 AD1F AD1IN square VRGain x 1 AGND= 0.5*VDDA Mean Square Converter AD1RH AD1RL HY12P65 AGND REFO AGND 100n 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page141...

  • Page 142: Dcv

    500V: 1KV: 19.3.2. Example DCV Function VOLT AD1OSR=111 400khz/20000/2=10hz Modulator AD1IP Test AD1<18:0> 100k Gain x 0.9 inside AD1F AD1IN VRGain x 1 AGND= 0.5*VDDA AD1RH AD1RL HY12P65 AGND REFO AGND 100n 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page142...

  • Page 143: Acv

    ACV Function VOLT AD1OSR=000 400khz/32=12.5khz Modulator AD1<18:0> AD1IP LPFBW=10 Test 12.5khz/1024=12.2hz Gain x 0.9 AD1F AD1IN square VRGain x 1 AGND= 0.5*VDDA Mean Square Converter AD1RH AD1RL HY12P65 AGND REFO AGND 100n 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page143...

  • Page 144: 50Kohm

    50Kohm: 19.5.2. Example 500/5k/50k? Function AD1OSR=111 400khz/20000/2=10hz PTC+100 Modulator AD1IP AD1<18:0> 900k 100k Test Gain x 0.9 inside AD1F AD1IN VRGain x 1 AGND= 0.3*VDDA AD1RH AD1RL HY12P65 AGND VREF= AGND+1V inside 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page144...

  • Page 145: 50Mohm

    19.6.2. Example VDDA 500k/5M/50M? Function inside PMOS, inside AD1OSR=111 400khz/20000/2=10hz PTC+100 Modulator AD1IP AD1<18:0> 900k 100k Test Gain x 0.9 inside AD1F AD1IN VRGain x 0.33 AGND= 0.3*VDDA AD1RH AD1RL HY12P65 AGND VDDA 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page145...

  • Page 146: 5Nf~500Nf

    HY12S65 User’s Guide Digital Multimeter 19.7. 5nF~500nF 19.7.1. Register Configuration 19.7.2. Example 50nF/500nF Function VDDA 101k Flag 22/36*VDDA PTC+100 CMPHO CMPH Frequency Latch ACPO Counter 900k Test CMPL CMPLO 10/36*VDDA AGND= 0.5*VDDA HY12P65 AGND 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page146...

  • Page 147: 5Uf~500Uf

    19.8. 5uF~500uF 19.8.1. Register Configuration 19.8.2. Example 5u/50u/500uF VREF= 34/36*VDDA Function inside VDDA PMOS, inside Flag 22/36*VDDA PTC+100 CMPH CMPHO Frequency Latch ACPO Counter 900k Test CMPL CMPLO 10/36*VDDA AGND= 0.5*VDDA HY12P65 AGND 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page147...

  • Page 148: Build-In Eprom

    0004H 0005H Blank read as “1” Data Protect read as “0” XXXXH Figure 20-35 Build-In EPROM Architecture BIE Register summary： BIECN VPPHV[0], BIEWR[0], BIERD[0] BIEARH ENBIE[0] BIEARL BIE_ADDR[5:0] BIEDRH BIE_DATA[15:8] BIEDRL BIE_DATA[7:0] 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page148...

  • Page 149: Bie Instruction

     Data after complete read, BIERD [0] is automatically set by the hardware as <0>, and BIEARL [7: 0] address register content is automatically incremented until 3Fh that is no longer incremented. 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page149...
  • Page 150  BIE read operation has nothing to do with the VPP voltage, but not for the low voltage; when use the BIE to program, the power order is VDD first, then VPP 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com...
  • Page 151 BIEDRL, F, BANK BIECN, BIEWR, BANK ; After finish writing EPROM，BIECN[BIEWR] automatically be 0. ; BIEARL(BIE_ADDR)automatically add 1, to 3FH upmost. WAITWRBIE: BTSZ BIECN, BIEWR, BANK  Figure 20-3 H08A BIE Example program (applyHY12P62) 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page151...

  • Page 152: Register Description-Bie

    1：Available to write in (BIE read) BIEARH：EPROM Control Register ENBIE： 0：not enable BIE function 1：enable BIE function BIEARL：EPROM address definition BIE_ADDR[5:0]：EPROM address, only 00H~3FH，total 64 words BIEDRH：EPROM High Byte data definition BIEDRL：EPROM Low Byte data definition 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page152...

  • Page 153: Revision Record

    Revise HS_DCK Outputs 4MHz (External Oscillator) Example Program 56, 57 Revise DA3.5 description 91, 92 Revise UART operating frequency as CPU_CK 133, 134 Revise ADCOSR<2:0> and ADC Min value Add RSTCOMB description Add RSLPF description Add RSRMS description 2015-2017 HYCON Technology Corp UG-HY12S65-V05_EN © www.hycontek.com page153...

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