6 Theory of Operation
XLR
P.I.P.
BALANCED
INPUTS
BALANCE
INPUT STAGE
GAIN STAGE
1/4" PHONE
DISPLAY
page 20
TRANSLATOR
E
A
B
ODEP
C
D
VARIABLE
ERROR
AMP
TRANSLATOR
+Vcc
+Vcc
A
(ODEP)
LVA
NPN HI
OUTPUT
STAGE
OUTPUT
CURRENT
BIAS
LIMIT
+
PNP HI
OUTPUT
STAGE
LVA
C
(ODEP)
–Vcc
–Vcc
ONLY ONE CHANNEL SHOWN
Figure 6.1 Circuit Block Diagram (Channel 1)
Macro-Tech MA-24X6 & 36X12 Power Amplifiers
B
(ODEP)
NPN LOW
OUTPUT
STAGE
+Vcc
BIAS
BRIDGE
–Vcc
BALANCE
PNP LOW
OUTPUT
STAGE
D
(ODEP)
Operation Manual