KSI Lumissil IS31AP2121 Manual

2×25w stereo / 1× 50w mono digital audio amplifier with 20 bands eq functions, drc and 2.1ch mode

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IS31AP2121
2×25W STEREO / 1× 50W MONO DIGITAL AUDIO AMPLIFIER
WITH 20 BANDS EQ FUNCTIONS, DRC AND 2.1CH MODE
GENERAL DESCRIPTION
The IS31AP2121 is a digital audio amplifier capable of
driving 25W (BTL) each to a pair of 8Ω speakers and
50W (PBTL) to a 4Ω speaker operating at 24V supply
without external heat-sink or fan. The IS31AP2121 is
also capable of driving 4Ω, 12W (SE)×2 + 8Ω, 25W
(BTL)×1 at 24V supply for 2.1CH application.
The
IS31AP2121
processing functions, such as volume control, 20 EQ
bands, audio mixing, 3D surround sound and Dynamic
Range Control (DRC). These are fully programmable
via a simple I2C control interface. Robust protection
circuits are provided to protect the IS31AP2121 from
damage due to accidental erroneous operating
condition. The full digital circuit design of IS31AP2121
is more tolerant to noise and PVT (Process, Voltage,
and Temperature) variation than the analog Class-AB
or Class-D audio amplifier counterpart implemented by
analog circuit design. IS31AP2121 is pop free during
instantaneous power on/off or mute/shut down
switching because of its robust built-in anti-pop circuit.
APPLICATIONS
TV audio
Boom-box, CD and DVD receiver, docking system
Powered speaker
Wireless audio
Lumissil Microsystems – www.lumissil.com
Rev. D, 08/10/2021
Arrow.com.
Downloaded from
can
provide
advanced
FEATURES
16/18/20/24-bits input with I2S, Left-alignment and
Right-alignment data format
PSNR & DR (A-weighting)
Loudspeaker: 104dB (PSNR), 110dB (DR) @24V
Multiple sampling frequencies (F
- 32kHz / 44.1kHz / 48kHz and
audio
- 64kHz / 88.2kHz / 96kHz and
- 128kHz / 176.4kHz / 192kHz
System clock = 64x, 128x, 192x, 256x, 384x,
512x, 576x, 768x, 1024x Fs
- 64x~1024x F
- 64x~512x F
S
- 64x~256x F
S
Supply voltage
- 3.3V for digital circuit
- 10V~26V for speaker driver
Supports 2.0CH/2.1CH/Mono configuration
Loudspeaker output power for at 24V
- 10W × 2CH into 8Ω @0.16% THD+N for stereo
- 15W × 2CH into 8Ω @0.19% THD+N for stereo
- 25W × 2CH into 8Ω @0.3% THD+N for stereo
Sound processing including:
- 20 bands parametric speaker EQ
- Volume control (+24dB ~ -103dB, 0.125dB/step),
- Dynamic range control (DRC)
- Dual band dynamic range control
- Power clipping
- 3D surround sound
- Channel mixing
- Noise gate with hysteresis window
- Bass/Treble tone control
Bass management crossover filter
-
- DC-blocking high-pass filter
Anti-pop design
Short circuit and over-temperature protection
Supports I2C control without MCLK
I2C control interface with selectable device
address
Support BCLK system
Support hardware and software reset
Internal PLL
LV Under-voltage shutdown and HV Under-voltage
detection
Power saving mode
August 2021
)
S
for 32kHz / 44.1kHz / 48kHz
S
for 64kHz / 88.2kHz / 96kHz
for 128kHz / 176.4kHz / 192kHz
1

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Summary of Contents for KSI Lumissil IS31AP2121

  • Page 1 IS31AP2121 2×25W STEREO / 1× 50W MONO DIGITAL AUDIO AMPLIFIER WITH 20 BANDS EQ FUNCTIONS, DRC AND 2.1CH MODE August 2021 GENERAL DESCRIPTION FEATURES  The IS31AP2121 is a digital audio amplifier capable of 16/18/20/24-bits input with I2S, Left-alignment and driving 25W (BTL) each to a pair of 8Ω...
  • Page 2: Typical Application Circuit

    IS31AP2121 TYPICAL APPLICATION CIRCUIT Figure 1 Typical Application Circuit (For Stereo) Figure 2 Typical Application Circuit (For Mono) Logic Power Down Normal RSTB Reset Normal PBTL Stereo Mono Lumissil Microsystems – www.lumissil.com Rev. D, 08/10/2021 Arrow.com. Downloaded from...
  • Page 3 IS31AP2121 Figure 3 Typical Application Circuit (For 2.1CH) (Note 5) Logic Power Down Normal RSTB Reset Normal PBTL Note 1: When concerning about short-circuit protection or performance, it is suggested using the choke with its I larger than 7A. Note 2: These capacitors should be placed as close to speaker jack as possible, and their values should be determined according to EMI test results.
  • Page 4: Pin Configuration

    IS31AP2121 PIN CONFIGURATION Package Pin Configuration (Top View) OUTLA OUTRB VCCLA VCCRA VCCLB VCCRB eLQFP-48 CLK_OUT PBTL DGND DGND DVDD RSTB Lumissil Microsystems – www.lumissil.com Rev. D, 08/10/2021 Arrow.com. Downloaded from...
  • Page 5: Pin Description

    IS31AP2121 PIN DESCRIPTION Description Characteristics OUTLA Left channel output A. VCCLA Left channel supply A. 3,44 VCCLB Left channel supply B. 4~6,10~12 Not connected. PLL ratio setting pin during power up, this pin is monitored on the rising edge of reset. PMF register will be default set at 1 or 4 times PLL ratio.
  • Page 6 IS31AP2121 PIN DESCRIPTION (CONTINUE) Description Characteristics 34,41 VCCRB Right channel supply B. VCCRA Right channel supply A. OUTRB Right channel output B. 37,38 GNDR Right channel ground. OUTRA Right channel output A. 42,43,45 Not connected. OUTLB Left channel output B. 47,48 GNDL Left channel ground.
  • Page 7: Ordering Information

    IS31AP2121 ORDERING INFORMATION Industrial Range: 0°C to +70°C Order Part No. Package IS31AP2121-LQLS1 e-LQFP-48, Lead-free 250/Tray Copyright  ©  2021  Lumissil  Microsystems.  All  rights  reserved.  Lumissil  Microsystems  reserves  the  right  to  make  changes  to  this  specification  and  its  products  at  any  time  without  notice.  Lumissil  Microsystems  assumes  no  liability  arising  out  of  the  application  or  use  of  any  information,  products  or  services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and ...
  • Page 8: Absolute Maximum Ratings

    IS31AP2121 ABSOLUTE MAXIMUM RATINGS Supply for driver stage (VCCR, VCCL), V -0.3V ~ +30V Supply for digital circuit (DVDD), V -0.3V ~ +3.6V Input voltage (SDA,SCL,RSTB,PDB,ERRORB,MCLK, -0.3V ~ +3.6V BCLK,LRCIN,SDATA,PBTL), V Thermal resistance, θ 27.4°C/W Junction temperature range, T 0°C ~ 150°C Storage temperature range, T -65°C ~ +150°C ESD (HBM)
  • Page 9: Ac Electrical Characteristics

    IS31AP2121 DC ELECTRICAL CHARACTERISTICS (CONTINUE) =25°C, unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit Logic Electrical Characteristics High level input voltage =3.3V Low level input voltage =3.3V High level output voltage =3.3V Low level output voltage =3.3V Input capacitance Note 1: Loudspeaker over-current protection is only effective when loudspeaker drivers are properly connected with external LC filters.
  • Page 10 IS31AP2121 I2C DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 4) Standard Mode Fast Mode Symbol Parameter Unit Min. Max. Min. Max. Serial-Clock frequency Bus free time between a STOP and a START μs condition Hold time (repeated) START condition μs HD, STA Repeated START condition setup time μs SU, STA...
  • Page 11 IS31AP2121 Figure 4 I2C Timing Figure 5 I2S Figure 6 Left-Alignment Figure 7 Right-Alignment Figure 8 System Clock Timing Lumissil Microsystems – www.lumissil.com Rev. D, 08/10/2021 Arrow.com. Downloaded from...
  • Page 12 IS31AP2121 Figure 9 Timing Relationship (Using I2S format as an example) Lumissil Microsystems – www.lumissil.com Rev. D, 08/10/2021 Arrow.com. Downloaded from...
  • Page 13: Typical Performance Characteristics

    IS31AP2121 TYPICAL PERFORMANCE CHARACTERISTICS = 8Ω = 8Ω = 24V = 12V Strereo Strereo = 10W = 5W = 5W = 2.5W = 1W = 0.25W 0.05 0.05 = 0.5W = 0.5W 0.02 0.02 0.01 0.01 Frequency(Hz) Frequency(Hz) Figure 10 THD+N vs. Frequency Figure 11 THD+N vs.
  • Page 14 IS31AP2121 = 24V = 12V = 8Ω = 8Ω Strero Strero 10kHz 10kHz 1kHz 1kHz 0.05 0.05 20Hz 0.02 0.02 20Hz 0.01 0.01 5m 10m 50m 100m 500m 1 10 20 50m 100m 500m 1 Output Power(W) Output Power(W) Figure 16 THD+N vs. Output Power Figure 17 THD+N vs.
  • Page 15 IS31AP2121 = 24V = 12V = 8Ω = 8Ω Stereo Stereo Left to Right Left to Right -100 -100 Right to Left Right to Left -120 -120 Frequency(Hz) Frequency(Hz) Figure 22 Cross-Talk Figure 23 Cross-Talk = 24V = 24V = 8Ω = 8Ω...
  • Page 16 IS31AP2121 = 4Ω = 4Ω 2.1CH Mode PBTL Mode THD+N = 10% THD+N = 10% THD+N = 1% THD+N = 1% Supply Voltage(V) Supply Voltage(V) Figure 28 Output Power vs. Supply Voltage Figure 29 Output Power vs. Supply Voltage Note: Dashed lines represent thermally limited region. Note: Dashed lines represent thermally limited region.
  • Page 17: Functional Block Diagram

    IS31AP2121 FUNCTIONAL BLOCK DIAGRAM Lumissil Microsystems – www.lumissil.com Rev. D, 08/10/2021 Arrow.com. Downloaded from...
  • Page 18: Applications Information

    IS31AP2121 APPLICATIONS INFORMATION IS31AP2121 has a built-in PLL internally, the default volume is muted. IS31AP2121 will activate while the de-mute command via I2C is programmed. OPERATION MODES Without I2C Control The default settings, Bass, Treble, EQ, Volume, DRC, PLL, Subwoofer Bandwidth, …, and Sub- -103dB woofer gain are applied to register table content when using IS31AP2121 without I2C control.
  • Page 19: Surround Sound

    IS31AP2121 temperature drops to 125°C. The temperature Low indicates an I2C address of 0x30, and high an values may vary around 10%. address of 0x31. Short-Circuit Protection OUTPUT CONFIGURATION The short-circuit protection circuit protects the output The bit 4 [SEM] of address 0X11 and PBTL pin stage when the wires connected to loudspeakers are defines the configuration mode.
  • Page 20: Power-On Sequence

    IS31AP2121 POWER ON SEQUENCE Hereunder is IS31AP2121’s power on sequence. Give a de-mute command via I2C when the whole system is stable. Normal Normal Power-On PDB=L Operation Operation MCLK BCLK LRCIN RSTB I2C Active De-mute Figure 33 Power On Sequence Table 2 Power On Sequence POWER OFF SEQUENCE Hereunder is IS31AP2121’s power off sequence.
  • Page 21 IS31AP2121 Table 3 Power Off Sequence Symbol Min. t1 (With I2C Control) 35ms t1 (Without I2C Control) 0ms (Note) Note: When t2 is less than 0.1ms, pop noise may occur. Lumissil Microsystems – www.lumissil.com Rev. D, 08/10/2021 Arrow.com. Downloaded from...
  • Page 22: Register Definitions

    IS31AP2121 I2C-BUS TRANSFER PROTOCOL INTRODUCTION only occurs when SCL signal is low. IS31AP2121 samples the SDA signal at the rising edge of SCL IS31AP2121 employs I2C-bus transfer protocol. Two signal. wires, serial data and serial clock carry information between the devices connected to the bus. Each Device Addressing device is recognized by a unique 7-bit address and The master generates 7-bit address to recognize...
  • Page 23 IS31AP2121 Dual Band DRC Enable (Only for stereo mode, PBTL=Low) LRCIN ASRC PreScal BCLK SDATA ASRC PreScal MCLK OUTLA Volume Clipping HPF1 HPF2 DRC1 HPFdc PostScal S/H2 OUTLB Power Stage OUTRA Volume Clipping HPF1 HPF2 DRC1 HPFdc PostScal S/H2 OUTRB Volume DRC2 Volume...
  • Page 24 IS31AP2121 Table 4 Register Function Address Name Table Default State Control 1 Register 000x 0100 State Control 2 Register x000 0100 State Control 3 Register 0xxx 1111 Master Volume Control Register 0001 1000 04h~06h Channel 1~3 Volume Register 0001 0100 07h,08h Bass/Treble Tone Register xxx1 0000...
  • Page 25 IS31AP2121 LV_UVSEL LV Under-voltage Selection EN_CLK_OUT PLL Clock Output 2.7V Disabled 3.0V Enable LREXC Left/Right Channel Exchanged MUTE Master Mute No exchange All channel not muted L/R exchange All channel muted Table 6 01h State Control 2 Register Channel x Mute D5:D4 D3:D0 Channel x not muted...
  • Page 26 IS31AP2121 Table 9 04h~06h Channel 1~3 Volume Registers Bass Management Crossover Frequency 0000 80Hz D7:D0 0001 100Hz 0010 120Hz Name 0011 140Hz Default 0001 0100 0100 160Hz 0101 180Hz Channel x Volume 0110 200Hz 0000 0000 +12.0dB 0111 300Hz 0000 0001 +11.5dB 1000 400Hz...
  • Page 27 IS31AP2121 DSPB EQ Bypass Table 14 0Dh Channel 3 Configuration Register EQ enable D7:D5 EQ bypass Name C3DRCM C3PCBP DC Blocking HPF Bypass Default HPF DC enable HPF DC bypass Name C3DRCBP C3HPFBP C3VBP Table 13 0Bh~0Ch Channel 1~2 Configuration Default Registers The IS31AP2121 can configure each channel to...
  • Page 28 IS31AP2121 0110 0.4528dB/ms DIS_MCLK_DET Disable MCLK Detect Circuit 0111 0.2264dB/ms Enable MCLK detect circuit 1000 0.15dB/ms Disable MCLK detect circuit 1001 0.1121dB/ms 1010 0.0902dB/ms QT_EN Power Saving Mode 1011 0.0752dB/ms Disable 1100 0.0645dB/ms Enable 1101 0.0563dB/ms 1110 0.0501dB/ms PWM_SEL PWM Modulation 1111 0.0451dB/ms Qua-ternary...
  • Page 29 IS31AP2121 D1~ D0. When noise gate function occurs, input Table 21 18h~1Ah User-Defined Coefficients signal will multiply noise gate gain (x1/8, x1/4 x1/2, Registers x0). User can select fade out or not via D4. (Top/Middle/Bottom 8-bits of coefficients A2) D7:D0 A_SEL_FAULT I2C Address Selection or ERROR Name output...
  • Page 30: Ram Access

    IS31AP2121 Table 26 2Ah Power Saving Mode Switching MV_FT Master Volume Fine Tune Level Register -0.125dB D7:D5 D4:D0 -0.25dB Name QT_SW_WINDOW QT_SW_LEVEL -0.375dB Default 01101 C1V_FT Channel 1 Volume Fine Tune If the PWM exceeds the programmed switching power level (default 26×40ns), the modulation -0.125dB algorithm will change from quaternary into power -0.25dB...
  • Page 31 IS31AP2121 10. Read middle 8-bits of coefficient B1 in I2C 16. Write bottom 8-bits of coefficient A0 in I2C address-0X1C address-0X23 11. Read bottom 8-bits of coefficient B1 in I2C 17. Write 1 to WA bit in address-0X24 address-0X1D Note: the read and write operation on RAM 12.
  • Page 32 IS31AP2121 ATTACK THRESHOLD The IS31AP2121 provides power limited function. When the input RMS exceeds the programmable attack threshold value, the output power will be limited by this threshold power level via gradual gain reduction. Two sets of power limit are provided. One is used of channel 1 and channel 2, while the other is used for channel 3.
  • Page 33 IS31AP2121 Attack Threshold Release Threshold Input Release Threshold Attack Threshold Gain ∆gain2 ∆gain1 Attack rate=∆gain1/∆t1 Release rate=∆gain2/∆t2 ∆t1 ∆t2 Touch Attack Under Release Threshold Threshold Attack Threshold Release Threshold Output Release Threshold Attack Threshold Figure 37 Attack And Release Threshold NOISE GATE ATTACK LEVEL DRC ENERGY COEFFICIENT When both left and right signals have 2048...
  • Page 34 IS31AP2121 Table 31 Sample Calculation for DRC Energy Coefficient DRC Energy Linear Decimal Coefficient (1.23 Format) 8388607 7FFFFF 1/256 -48.2 1/256 32768 8000 1/1024 -60.2 1/1024 8192 2000 (x/20) 8388607×L dec2hex(D) Lumissil Microsystems – www.lumissil.com Rev. D, 08/10/2021 Arrow.com. Downloaded from...
  • Page 35 IS31AP2121 THE USER DEFINED RAM The contents of user defined RAM is represented in following table. Table 32 User Defined RAM Address Name Coefficient Default Address Name Coefficient Default 0x00 CH1EQ1A1 0x000000 0x32 CH2EQ1A1 0x000000 0x01 CH1EQ1A2 0x000000 0x33 CH2EQ1A2 0x000000 Channel 1 Channel 2...
  • Page 36 IS31AP2121 Table 32 User Defined RAM (Continues) Address Name Coefficient Default Address Name Coefficient Default 0x1E CH1EQ7A1 0x000000 0x50 CH2EQ7A1 0x000000 0x1F CH1EQ7A2 0x000000 0x51 CH2EQ7A2 0x000000 Channel 1 Channel 2 0x20 CH1EQ7B1 0x000000 0x52 CH2EQ7B1 0x000000 0x21 CH1EQ7B2 0x000000 0x53 CH2EQ7B2 0x000000...
  • Page 37 IS31AP2121 Table 32 User Defined RAM (Continues) Address Name Coefficient Default 0x64 Channel 1 Mixer1 0x7FFFFF 0x65 Channel 1 Mixer2 0x000000 0x66 Channel 2 Mixer1 0x000000 0x67 Channel 2 Mixer2 0x7FFFFF 0x68 Channel 3 Mixer1 0x400000 0x69 Channel 3 Mixer2 0x400000 0x6A Channel 1 Prescale...
  • Page 38 IS31AP2121 CLASSIFICATION REFLOW PROFILES Profile Feature Pb-Free Assembly Preheat & Soak 150°C Temperature min (Tsmin) 200°C Temperature max (Tsmax) 60-120 seconds Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) 217°C Time at liquidous (tL) 60-150 seconds Peak package body temperature (Tp)* Max 260°C...
  • Page 39: Package Information

    IS31AP2121 PACKAGE INFORMATION eLQFP-48 Lumissil Microsystems – www.lumissil.com Rev. D, 08/10/2021 Arrow.com. Downloaded from...
  • Page 40 IS31AP2121 RECOMMENDED LAND PATTERN Note: 1. Land pattern complies to IPC-7351. 2. All dimensions in MM. 3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since land pattern design depends on many factors unknown (eg. user’s board manufacturing specs), user must determine suitability for use. Lumissil Microsystems –...
  • Page 41: Revision History

    IS31AP2121 REVISION HISTORY Revision Detail Information Date Initial release 2015.07.07 Update pin out, exchange Pin 36 and Pin 39 2015.09.10 1. Update EC table 2015.10.20 2. Add performance figures Add “End of Life” watermark 2021.08.10 Lumissil Microsystems – www.lumissil.com Rev. D, 08/10/2021 Arrow.com.

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