LG 32LH35FD Service Manual page 24

A
7
6
+3.3V_MEMC
GPIO12 GPIO14
Non M+S LVDS LOW LOW
M+S 42" Mini LVDS LOW HIGH
M+S 47" Mini LVDS HIGH LOW
M+S 37" Mini LVDS HIGH HIGH
5
+1.8V_MEMC
BLM18PG121SN1D
L2702
* ISP Port for MEMC
4 +5.0V
P2701
TJC2508-4A
009:Q13
ENG
009:Q13
1
009:Q13
009:Q12
2
ISP_RXD_TR
3
B6
009:Q13
009:Q12
4
B6
ISP_TXD_TR
+3.3V_MEMC
3
2
+3.3V_MEMC
SPI FLASH
IC2702
W25X20AVSNIG
R2703 56
CS VCC
M_SPI_CZ 1 8
008:Y11
R2704 56
DO HOLD
M_SPI_DO 2 7
008:Y11
R2705 10K
R2710
WP CLK
3 6
R2711
GND DIO
4 5
1
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
B C
XTAL
R2720
1M
X2701
008:P27
M_XTALO
12MHz
C2717 C2724
20pF 20pF
+1.26V_MEMC
+3.3V_MEMC
PI Result
R2714 0
001:L5 ISP_RXD_TR
R2715 0
+3.3V_MEMC
001:L5
ISP_TXD_TR
R2716 100
R2712 1K
9:I4 SDA3_3.3V
100
R2717
9:I4 SCL3_3.3V
R2713 1K C2731
OPT
R2721 0 OPT
BIT_SEL
R2722 0 OPT
LVDS_SEL
+3.3V_MEMC
BLM18PG121SN1D
C2714 C2716
L2704
0.1uF 0.1uF
C2710
16V 16V
10uF
10V
PI Result
0.1uF
0.1uF
C2703
C2707
22uF 0.1uF
C2728
URSA_DQ[20]
16V
URSA_DQ[19]
URSA_DQ[17]
URSA_DQ[22]
URSA_DQ[27]
URSA_DQ[28]
0.1uF
C2719
URSA_DQ[25]
URSA_DQ[30]
URSA_DQM3
URSA_DQM2
0.1uF
C2720
URSA_DQS2
URSA_DQSB2
0.1uF
C2729
URSA_DQS3
URSA_DQSB3
URSA_DQ[31]
URSA_DQ[24]
0.1uF
C2721
URSA_DQ[26]
URSA_DQ[29]
URSA_DQ[23]
URSA_DQ[16]
URSA_DQ[18]
URSA_DQ[21]
009:Q16
URSA_MCLK
0.1uF
URSA_MCLKZ
009:Q15
C2726
009:Q15;009:Y15
URSA_ODT
0.1uF C2722
0.1uF
C2723
56
M_SPI_CK 008:Y10
56
M_SPI_DI 008:Y11
D E
M_XTALI 0 08:P27
R2723 R2729
100 100
R2724 R2730
100 100
R2725 R2731
100 100
R2726 R2732
100 100
R2727 R2733
100 100
R2728 R2734
100 100
SDAS
E1
SCLS
D1
GPIO[8]
F1
GPIO[9]
0.1uF G1
GND_14
K8 [E1]
VDDC_1
E5
[D1]
GPIO[10]
E2
GPIO[11]
F2
GPIO[12]
F3
GPIO[13]
G2
GPIO[22]
M4
GPIO[23]
M5
GPIO[14]
G3
GPIO[15]
E4
GPIO[16]
F4
GPIO[17]
G4
GPIO[18]
H4
GPIO[19]
J4
GPIO[20]
K4
GPIO[21]
L4
C2732 VDDP_2
J6
GND_7
H9
GND_15 K9
VDDC_2
F6
MDATA[20]
H1
MDATA[19]
H2
IC2701
MDATA[17]
H3
MDATA[22]
J1
MDATA[27]
J2
MDATA[28]
J3 LGE7329A
MDATA[25]
K1
MDATA[30]
K2
AVDD_DDR_2
K6
DQM[3]
K3
DQM[2]
L1
GND_10 LH50_90_ONLY
J8
DQS[2]
L2
DQSB[2]
L3
AVDD_DDR_4
L6
VDDP_3
L8
GND_8
H10
DQS[3]
M1
DQSB[3]
M2
AVDD_DDR_5
L7
MDATA[31]
M3
MDATA[24]
N1
GND_11
J9
MDATA[26]
N2
MDATA[29]
N3
AVDD_DDR_6
L10
MDATA[23]
P1
MDATA[16]
R1
MDATA[18]
T1 [L9]
MDATA[21]
T2
[N5]
MCLK[0]
R2 [N4]
MCLKZ[0]
P2
GND_1
G7
AVDD_MEMPLL
L9
MVREF
N5
ODT
N4
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
F G
URSA_A+[0-4],URSA_A-[0-4],URSA_ACK+,URSA_ACK- URSA_B+[0-4],URSA_B-[0-4],URSA_BCK+,URSA_BCK-
+3.3V_MEMC
L2706
BLM18PG121SN1D
+3.3V_MEMC
C2754 10uF
R2736
C2755
820
GPIO_5
D8
GPIO_7
D10
GPIO_11
E10
GPIO_10 0.1uF
E3
GPIO_3
D2
LVB2P
C15
LVB2M
B15
LVBCKP
A15
LVBCKM
A16
LVB3P
B16
LVB3M
C16
LVB4P
D15
LVB4M
D16
AVDD_33_2
F9
GND_4
G10
LVC0P
E15
LVC0M
E16
LVC1P
E14
LVC1M
F14
LVC2P
F16
LVC2M
F15
LVCCKP
G15
LVCCKM
G16
LVC3P
G14
LVC3M
H14
LVC4P
H16
LVC4M
H15
LVD0P
J15
LVD0M
J16
LVD1P
J14
LVD1M
K14
GND_3
G9
LVD2P
L14
LVD2M
L15
LVDCKP
L16
LVDCKM
M16
AVDD_33_1
F8
LVD3P
M15
LVD3M
M14
LVD4P
N16
LVD4M C2748
N15
VDDC_5
H6
0.1uF
GPIO[24]
N6
GPIO[7]
E12
GPIO[6]
D14
GPIO[5]
F12
GPIO[4]
E13
GPIO[3]
F13
GPIO[2]
G13
GPIO[1]
H13
GPIO[0]
J13
PWM0
K12
PWM1
[N13] L12
CSZ
K13
[N12]
SDO
M12
SDI
M13
SCK
L13
GPIO[30]
N14
GPIO[29]
N13
GPIO[28]
N12
EEPROM
URSA_DQ[0-31]
009:D21;009:AL21
This page is all LH50/90_ONLY option
H I J
C2756
10uF
10V
10uF
10V
C2751
0.1uF
C2749
C2750
URSA_B+[2]
URSA_B-[2]
URSA_BCK+
URSA_BCK-
URSA_B+[3]
URSA_B-[3]
URSA_B+[4]
URSA_B-[4]
C2752
008:AE17
URSA_C+[0-4],URSA_C-[0-4],URSA_CCK+,URSA_CCK-
URSA_C+[0]
URSA_C-[0]
0.1uF
URSA_C+[1]
URSA_C-[1]
URSA_C+[2]
URSA_C-[2]
URSA_CCK+
URSA_CCK-
URSA_C+[3]
URSA_C-[3]
URSA_C+[4]
URSA_C-[4]
URSA_D+[0]
URSA_D-[0]
URSA_D+[1]
URSA_D-[1]
C2753
URSA_D+[2]
URSA_D-[2]
0.1uF
URSA_DCK+
URSA_DCK-
URSA_D+[3]
URSA_D-[3]
URSA_D+[4]
URSA_D-[4]
008:AL17
+3.3V_MEMC
URSA_D+[0-4],URSA_D-[0-4],URSA_DCK+,URSA_DCK-
008:AF6
M_SPI_CZ
M_SPI_DO 008:AF6
M_SPI_DI 008:AK5
M_SPI_CK 008:AK5
+3.3V_ST
R2737
10K
MEMC_RESET 001:AB21
GPIO8 PWM1 PWM0
I2C HIGH LOW HIGH
HIGH HIGH LOW
SPI HIGH HIGH HIGH
BCM (BRAZIL VENUS)
2008.10.15
Mstar FRC 7 15