MSI G31M4-F Manual page 53

M S-7527 M ainboard
CAS Latency(CL)
W hen the DRAM Timing M ode sets to [Manual], the field is adjustable.This
controls the CAS latency, which determines the timing delay (in clock cycles)
before SDRAM starts a read command after receiving it.
tRCD
W hen the DRAM Timing Mode sets to [Manual], the field is adjustable. W hen
DRAM is refreshed, both rows and columns are addressed separately. This
setup item allows you to determine the timing of the transition from RAS (row
address strobe) to CAS (column address strobe). The less the clock cycles, the
faster the DRAM performance.
tRP
W hen the DRAM Timing Mode sets to [Manual], the field is adjustable. This
item controls the number of cycles for Row Address Strobe (RAS) to be allowed
to precharge. If insufficient time is allowed for the RAS to accumulate its charge
before DRAM refresh, refreshing may be incomplete and DRAM may fail to retain
data. This item applies only when synchronous DRAM is installed in the system.
tRAS
W hen the DRAM Timing Mode sets to [Manual], the field is adjustable. This
setting determines the time RAS takes to read from and write to a memory cell.
tRTP
W hen the DRAM Timing Mode sets to [Manual], time interval between a read
and a precharge command.
tRC
W hen the DRAM Timing Mode sets to [Manual], the field is adjustable. The row
cycle time determines the minimum number of clock cycles a memory row takes
to complete a full cycle, from row activation up to the precharging of the active
r ow.
tWR
W hen the DRAM Timing Mode is set to [Manual], the field is adjustable. It
specifies the amount of delay (in clock cycles) that must elapse after the
completion of a valid write operation, before an active bank can be precharged.
This delay is required to guarantee that data in the write buffers can be written
to the memory cells before precharge occurs.
tRRD
When the DRAM Timing Mode sets to [Manual], the field is adjustable. Specifies
the active-to-active delay of different banks.
tWTR
W hen the DRAM Timing Mode is set to [Manual], the field is adjustable. This
item controls the W rite Data In to Read Command Delay memory timing. This
constitutes the minimum number of clock cycles that must occur between the
last valid write operation and the next read command to the same internal bank
of the DDR device.
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