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AsashiKASEI AKM AK7722 Manual

24bit 4ch adc + 24bit 4ch dac with audio dsp
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The AK7722 is a digital signal processor with an integrated 4ch 24bit DAC, a stereo ADC with input selector
and a 2ch input ADC. The integrated 4ch DAC, the 2ch ADC with input selector and the other 2ch ADC
feature high performance achieving 108dB, 96dB and 95dB, respectively. The integrated SRC has three
input selector enabling the DSP to operate in master mode with digital inputs. The audio DSP has
1536step/fs (at 48kHz sampling) parallel arithmetic operation performance and the 5k-word delay RAM
allows surround processing and time alignment adjusting. As the AK7722 is a RAM based DSP, it is
programmable for various user requirements. It is housed in an 80pin LQFP package.
[DSP Block]
- Word length: 24bit (Coefficient RAM & Data RAM: F24 floating point)
- Processing Speed: 13.6 ns (1536step/fs; fs = 48kHz)
- Multiplication: 20 x 24 → 44-bit Double precision arithmetic available
- Divider 20 / 20 → 20bit
- ALU: 48bit arithmetic operation (overflow margin 4bit) 20bit floating point arithmetic
and logic operation
- Program RAM: 3072 x 36bit
- Coefficient RAM: 2048 x 24bit (F24 floating point)
- Data RAM: 2048 x 24-bit (F24 floating point)
- Offset Register: 64 x 13bit
- Delay RAM1: 3072 x 24-bit
- Delay RAM2: 2048 x 24-bit
- Sampling rate: fs= 7.35k ~ 48kHz
- Master Clock: 1536fs
(generated from 32fs, 48fs, 64fs, 128fs, 256fs, 384fs by internal PLL)
- Master/Slave Operation
[ADC1 Block]
- Stereo with 6 Inputs Selector
- DR, S/N: 96dB (fs = 48kHz, when differential input)
- S/(N+D): 90dB (fs = 48kHz)
- Differential & Single-ended Inputs
- Digital HPF (fc=1Hz)
- 6 Analog Inputs Selector (2 differential, 4 single-ended)
- Digital Volume Control (24dB ~ -103dB, 0.5dB Step, Mute)
[ADC2 Block]
- DR, S/N: 95dB (fs = 48kHz)
- Single-ended Inputs
- Digital Volume Control (24dB ~ -103dB, 0.5dB Step, Mute)
[SRC Block]
- 3 Pair of Stereo → 1 Stereo Pair Selector
- 2ch x 1 system
- Supporting frequency: Fin = 7.35kHz ~ 96kHz → Fout = 7.35kHz ~ 48kHz
MS1328-E-00
24bit 4ch ADC + 24bit 4ch DAC with Audio DSP
GENERAL DESCRIPTION
(FSO/FSI = 0.167~ 6.0)
FEATURES
- 1 -
[AK7722]
AK7722
2011/09

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  • Page 1 [AK7722] AK7722 24bit 4ch ADC + 24bit 4ch DAC with Audio DSP GENERAL DESCRIPTION The AK7722 is a digital signal processor with an integrated 4ch 24bit DAC, a stereo ADC with input selector and a 2ch input ADC. The integrated 4ch DAC, the 2ch ADC with input selector and the other 2ch ADC feature high performance achieving 108dB, 96dB and 95dB, respectively.
  • Page 2 [AK7722] [Guidance SRC Block] (GSRC) - 1 Channel (24bit) Up-converter for Voice Guidance - Supporting frequency: Fin = 7.35kHz ~ 12kHz → Fout = 44.1kHz or 48kHz [DAC Block] - 4ch (2 Stereos) - 24bit 128 x Over-sampling advanced multi-bit (fs=8kHz~48kHz) - DR, S/N: 108dB (Differential Output) - S/(N+D): 90dB - Digital Volume Control (12dB ~ -115dB, 0.5dB Step, Mute)
  • Page 3 [AK7722] ■ Block Diagram LFLT DVDD pull down Hi-z VSS2 Open Drain AVDD VSS3 VCOM BICKI AVDRV LRCKI CLKGEN & CONT TESTI1 TESTI2 DVOL ADC2 IRESETN A2INL,A2INR SDOUTAD2 CLKOE ASEL[2:0] CLKO ADC1 DVOL AIN6L,AIN6R BICKOE BICKO AIN5L,AIN5R LRCKOE SDOUTAD1 LRCKO AIN4L,AIN4R SELDI5 AIN3L,AIN3R...
  • Page 4 [AK7722] DLP0, DLP1 CP0, CP1 DP0, DP1 DLRAM1:3072W x 24-Bit OFREG DRAM CRAM DLRAM2:2048W x 24-Bit 64w x 13-Bit 2048w x 24-Bit 2048W x 24-Bit CBUS(24-Bit) DBUS(24-Bit) Micon I/F MPX24 MPX20 Control Serial I/F PRAM 3072w x 36-Bit Multiply 24 x 20 → 44-Bit Stack: 5level(max) 24-Bit TMP 12 x 24-Bit...
  • Page 5 [AK7722] ■ Ordering Guide -40 ∼ +85°C AK7722VQ 80pin LQFP AKD7722 Evaluation Board for AK7722 ■ Pin Layout BICKO AOUTR2N AOUTR2P LRCKO AOUTL2N CLKO VSS3 AOUTL2P DVDD AOUTR1N AOUTR1P AOUTL1N AOUTL1P SI / CAD0 SCLK / SCL AVDD 80 pin LQFP VCOM RQN / CAD1 VSS6...

  • Page 6: Pin Function

    [AK7722] PIN FUNCTION Name Function Classification I ADC1 Lch Single-ended Input 3 Pin. AINL3 Analog Input AINR2N I ADC1 Inverted Rch Differential Input 2 Pin Analog Input AINR2P I ADC1 Non-inverted Rch Differential Input 2 Pin Analog Input AINL2N I ADC1 Inverted Lch Differential Input 2 Pin Analog Input AINL2P I ADC1 Non-inverted Lch Differential Input 2 Pin...
  • Page 7 [AK7722] Function Classification Name 29 SRIN1 I Serial Data Input Pin 1 (for SRC) Digital Input SDIN3 I Serial Data Input Pin 3 Data Write Ready Output Pin for Microprocessor Interface Microprocessor 30 RDY This pin outputs RDY, and outputs “H” during initial reset. Microprocessor Interface Write Request Pin (I2CSEL pin = “L”) Interface When initial reset state and Microcomputer interface are not in use, leave...
  • Page 8 [AK7722] Function Classification Name System Clock 49 SRBICK3 I Serial Bit Clock Input Pin 3 (for SRC) Input SRIN3 I Serial Data Input Pin 3 (for SRC) Digital Input I Conditional Jump Pin2 The conditional jump pin (JX2) is valid by setting control register (JX2E) to Conditional Input “1”.
  • Page 9 [AK7722] Name Function Classification 71 VSS6 - Ground Pin 0V Power Supply 72 A2INR I ADC2 Rch Single-ended Input Pin Analog Input 73 A2INL I ADC2 Lch Single-ended Input Pin Analog Input 74 AINR6 I ADC1 Rch Single-ended Input Pin 6 Analog Input 75 AINL6 I ADC1 Lch Single-ended Input Pin 6...

  • Page 10: Absolute Maximum Ratings

    [AK7722] ABSOLUTE MAXIMUM RATINGS (VSS1~VSS6=0V: Note Parameter Symbol Unit Power Supply Voltage Analog AVDD -0.3 Digital DVDD -0.3 Input Current (except for power supply pin ) – ±10 Analog Input Voltage VINA -0.3 AVDD+0.3 Digital Input Voltage VIND -0.3 DVDD+0.3 Operating Ambient Temperature ºC Storage Temperature...
  • Page 11 [AK7722] ANALOG CHARACTERISTICS (CODEC) ■ ADC Characteristics 1. ADC1 (Ta=25ºC; AVDD=DVDD=3.3V, BITCLK=64fs; Signal frequency 1kHz; Measurement frequency = 20Hz~20kHz @fs=48kHz; CKM mode0 (CKM[2:0]=000); BITFS[1:0]=00(64fs); with Differential Input; in SRC reset, Unless otherwise specified.) Parameter Unit Resolution Bits Section Dynamic Characteristics S/(N+D) (-1dBFS) Dynamic Range (A-weighted) (Note...
  • Page 12 [AK7722] ■ DAC1/2 Characteristics (Ta=25ºC; AVDD=DVDD=3.3V; VSS1~VSS6=0V; Signal frequency 1kHz; Measurement frequency =20Hz~20kHz @fs=48kHz; CKM[2:0]=000, BITFS[1:0]=00, in SRC Reset) Unless otherwise specified.) Parameter Unit DAC1 Resolution Bits DAC2 Dynamic Characteristics S/(N+D) (0 dBFS) Dynamic Range (A-weighted) (Note S/N (A-weighted) Inter-channel Isolation (f=1kHz) (Note DC accuracy Channel Gain Mismatch...

  • Page 13: Power Consumption

    [AK7722] DC CHARACTERISTICS (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V) Parameter Symbol Unit High Level Input Voltage (Note 80%DVDD Low Level Input Voltage (Note 20%DVDD SCL,SDA High Level Input Voltage 70%DVDD SCL,SDA Low Level Input Voltage 30%DVDD DVDD-0.5 High Level Output Voltage Iout=-100μA Low Level Output Voltage Iout=100μA (Note SDA Low Level Output Voltage Iout=3mA μA...
  • Page 14 [AK7722] DIGITAL FILTER CHARACTERISTICS ■ ADC Block (ADC1/2) 1. fs=48kHz (Ta=-40ºC ~85ºC, AVDD=DVDD=3.0~3.6V, fs=48kHz, Note Parameter Symbol Unit Passband (±0.1dB) (Note 18.9 (-1.0dB) 20.0 (-3.0dB) 23.0 Stopband Passband Ripple (Note ±0.04 Stopband Attenuation (Note Note Group Delay Distortion μs ΔGD Group Delay (Ts=1/fs) Note 21.
  • Page 15 [AK7722] ■ (Ta=-40ºC ~85ºC; AVDD=DVDD=3.0~3.6V) Parameter Symbol Unit Passband 0.980≤FSO/FSI≤6.000 0.4583FSI 0.900≤FSO/FSI<0.990 0.4167FSI 0.450≤FSO/FSI<0.910 0.2177FSI 0.225≤FSO/FSI<0.455 0.0917FSI 0.167≤FSO/FSI<0.227 0.0917FSI Stopband 0.980≤FSO/FSI≤6.000 0.5417FSI 0.900≤FSO/FSI<0.990 0.5021FSI 0.450≤FSO/FSI<0.910 0.2813FSI 0.225≤FSO/FSI<0.455 0.1573FSI 0.167≤FSO/FSI<0.227 0.1354FSI Passband Ripple 0.225≤FSO/FSI<0.455 ±0.0100 0.167≤FSO/FSI<0.227 ±0.0612 Stopband Attenuation 92.3 Group Delay (Ts=1/fs) (Note Note 27.

  • Page 16: Switching Characteristics

    [AK7722] SWITCHING CHARACTERISTICS ■ System Clock (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V, VSS1~VSS6=0V) Parameter Symbol Unit XTI CKM[2:0]=000, 001, 010 a) with a Crystal Oscillator: fXTI 11.2896 CKM[2:0]=000 fs=44.1kHz 12.288 fs=48kHz fXTI 16.9344 CKM[2:0]=001 fs=44.1kHz 18.432 fs=48kHz b) with an External Clock Duty Cycle fXTI 11.2896 CKM[2:0]=000, 010 fs=44.1kHz...
  • Page 17 [AK7722] ■ SRC Input Clock (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V; VSS1~VSS6=0V) Parameter Symbol Unit SRLRCKn Frequency 7.35 SRBICKn Frequency Frequency fBCLK 0.23 3.072 6.144 High Level Width tBCLKH Low Level Width tBCLKL ■ GSRC Input Clock (Ta=-40 ºC ~85 ºC; AVDD=DVDD=3.0~3.6V; VSS1~VSS6=0V) Parameter Symbol Unit GLRCK Frequency...
  • Page 18 [AK7722] ■ Audio Interface (SDIN1-2, SRIN1-3, SDOUT1-3) (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V, CL=20pF) Parameter Symbol Unit DSP Section Input SDIN1-2, SRIN1-3 (Note Delay Time from BICKI “↑” to LRCKI (Note tBLRD Delay Time from LRCKI to BICKI “↑” (Note tLRBD Serial Data Input Latch Setup Time tBSIDS Serial Data Input Latch Hold Time tBSIDH...

  • Page 19: Microprocessor Interface

    [AK7722] ■ Microprocessor Interface (Ta=-40ºC~85ºC; AVDD=DVDD=3.0~3.6V; CL=20pF) Parameter Symbol Unit Microprocessor Interface Signal RQN Fall Time tWRF RQN Rise Time tWRR SCLK Fall Time SCLK Rise Time SCLK Frequency fSCLK SCLK Low Level Width tSCLKL SCLK High Level Width tSCLKH Microprocessor →...
  • Page 20 [AK7722] ■ Timing Diagram 1/fXTI tXTI=1/fXTI 1/fXTI 1/fs ts=1/fs 1/fs LRCKI 1/fBCLK tBCLK=1/fBCLK 1/fBCLK BICKI tBCLKH tBCLKL Figure 3. System Clock INITRSTN tRST Figure 4. Reset Note 40. The INITRSTN pin must be “L” when power-up/power-down the AK7722. MS1328-E-00 2011/09...
  • Page 21 [AK7722] 1) Audio Interface LRCKI tBLRD tLRBD BICKI tBSIDS tBSIDH SDINn n=1, 2 Figure 5. DSP Block Input Interface in Slave Mode LRCKO 50%DVDD tMBL tMBL BICKO 50%DVDD tBSIDS tBSIDH SDINn n=1, 2 Figure 6. DSP Block Input Interface in Master Mode SRLRCKn tBLRD tLRBD...
  • Page 22 [AK7722] GLRCK tLRBD tBLRD GBICK tBSIDS tBSIDH SDIN5 Figure 8. GSRC Block Input Interface LRCKI tLRD BICKI tBSOD tLRD tBSOD SDOUTn 50%DVDD n=1, 2, 3 Figure 9. Output Interface in Slave Mode MS1328-E-00 2011/09...
  • Page 23 [AK7722] 2) Micro-controller Interface tWRF tWRR SCLK tSCLKL tSCLKH 1/fSCLK 1/fSCLK INITRSTN tRST tIRRQ Figure 10. Micro-controller Interface Signal tWRQH tSIS tSIH SCLK tWSC tSCW tWSC tSCW Figure 11. Micro-controller → AK7722 MS1328-E-00 2011/09...
  • Page 24 [AK7722] SCLK tSOH tSOS Figure 12. AK7722 → Micro-controller 3) I C-Bus Interface tBUF tLOW tHIGH tHD:STA tHD:DAT tSU:DAT tSU:STA tSU:STO Stop Start Start Stop Figure 13. I C-bus Interface MS1328-E-00 2011/09...

  • Page 25: Operation Overview

    [AK7722] OPERATION OVERVIEW ■ System Clock CKM[2:0] Clock Mode Select Pin Master/Slave mode switching, MCLK/ICLK (internal master clock/generated clock) clock source pin select, and ICLK frequency change are controlled by CKM [2:0] clock mode select pins. CKM[2:0] pins can only be set during initial reset or clock reset.
  • Page 26 [AK7722] ■ Relationship between MCLK Generating Clock (ICLK) and MCLK ICLK REFCLK MCLK XTI Pin Divider CKM mode 0/1/2 (MCLK source) ICLK REFCLK MCLK BICKI Pin Divider CKM mode 3 (MCLK source) ICLK REFCLK MCLK SRBICKn Pin Divider CKM mode 4 (MCLK source) MCLK 73.728MHz(@fs=48kHz) Figure 14.

  • Page 27: External Clock

    [AK7722] 2. Slave Mode (XTI Input Clock, CKM Mode 2) fs: sampling frequency Input Frequency Range Use of Crystal Mode [2:0] (MHz) Unit fs=48kHz fs=44.1kHz 12.288MHz 11.2896MHz 11.0~12.4 Required System Clocks are XTI, LRCKI and BICKI. XTI and LRCKI must be synchronized, but the phase between these clocks is not important.
  • Page 28 [AK7722] BITFS=0 @(DIFPCM=0 & DIFI2S=0) Right ch LRCKI Left ch BICKI 32×BICK 32×BICK BITFS=2 @(DIFPCM=0 & DIFI2S=0) Right ch LRCKI Left ch BICKI 16×BICK 16×BICK BITFS=1 @(DIFPCM=0 & DIFI2S=0) Right ch LRCKI Left ch BICKI 24×BICK 24×BICK * DIFPCM is set by CONT01: D7, and DIFI2S is set by CONT01: D6. * The sampling rate is determined by control register CONT0 DFS mode settings.
  • Page 29 [AK7722] 4. Slave Mode (SRBICKn Input, CKM Mode 4) This mode is the same slave mode as CKM mode 3 but the required clocks are different. SRBICKn is used instead of BICKI and SRLRCKn is used instead of LRCKI (n=1, 2, 3). This mode is available when the SRC is not used. Control register SRCRST bit should be set to “1”...
  • Page 30 [AK7722] ■ Control Register Setting The AK7722 control register settings are executed through a microcontroller interface. All registers are initialized by INITRSTN pin = “L” initial reset. When power-up the AK7722, initial reset must always be made. Since control registers CONT00, CONT01 and CONT0B are related to clock generation, they must be changed during clock reset (CKRSTN bit = “0”).
  • Page 31 [AK7722] 1. CONT00: Input Interface Select Write during control reset. Name Default CONT00 Reserved CKM[2] CKM[1] CKM[0] DFS[1] DFS[0] BITFS[1] BITFS[0] D7: Reserved 0: Normal operation (default) Write “0” into this bit. D6, D5, D4: CKM[2:0] Clock Mode Select Master MCLK Source Input Frequency System Clock Input Pins...
  • Page 32 [AK7722] 2. CONT01: Control Write during control reset. Name Default CONT01 DIFPCM DIFI2S PCM[1] PCM[0] TEST TEST TEST TEST D7: DIFPCM Audio Interface Select 0: MSB justified, LSB justified and I S format (default) 1: PCM format PCM format setting is not available when I S mode is selected.
  • Page 33 [AK7722] 3. CONT02: RAM Control Write during control or system reset. Name Default CONT02 Reserved Reserved BANK[1] BANK[0] JX1E JX2E SS[1] SS[0] D7: Reserved 0: Normal operation (default) Write “0” into this bit. D6: Reserved 0: Normal operation (default) Write “0” into this bit. D5, D4: BANK[1:0] DLRAM Mode Setting DLRAM1 DLRAM2...
  • Page 34 [AK7722] 4. CONT03: RAM Control Write during control or system reset. Name Default CONT03 POMODE DATARAM WDTEN WAVM WAVP[1] WAVP[0] EFEN CRCE D7: POMODE DLYRAM pointer0 Select 0: OFREG (default) 1: DBUS direct D6: DATARAM DATA RAM Addressing Select DATARAM A(000h-3FFh) B(400h-7FFh) Mode...
  • Page 35 [AK7722] 5. CONT04: In/Output Interface Clock Select Write during control or system reset. Name Default CONT04 DIF2[1] DIF2[0] DIF1[1] DIF1[0] TEST TEST TEST TEST D7, D6: DIF2[1:0] DSP DIN2 Input Format Select DIF Mode DIF2[1:0] Input Data Format MSB justified (24Bits) (default) LSB justified 24Bits LSB justified 20Bits...
  • Page 36 [AK7722] 6. CONT05: Output Interface Setting Write during control or system reset. Name Default CONT05 DOF3[1] DOF3[0] DOF2[1] DOF2[0] DOF1[1] DOF1[0] SELDO5[1] SELDO5[0] D7, D6: DOF3[1:0] DSP DOUT3 Output Format Select DOF3 Mode DOF3[1:0] Output Data Format MSB justified (24Bits) (default) LSB justified 24Bits LSB justified 20Bits...
  • Page 37 [AK7722] 7. CONT06: DSP Output Select Write during control or system reset. Name Default CONT06 BICKOE LRCKOE OUTS SELBCK SELDI5 SELDI4 SELDI3 DIF3SEL D7: BICKOE 0: BICKO pin = “L” (default) 1: Output Enable The BICKO output can be set to “L”. D6: LRCKOE 0: LRCKO pin= “L”...
  • Page 38 [AK7722] 8. CONT07: Output Setting Write during control or system reset. Name Default CONT07 CLKOE CLKS[2] CLKS[1] CLKS[0] CLKOP OUT3E OUT2E OUT1E D7: CLKOE 0: CLKO pin= “L” (default) 1: CLKO Output Enable D6, D5, D4: CLKS[2:0]: CLKO Output Clock Select CLKS CLKS[2:0] fs=48kHz...
  • Page 39 [AK7722] 9. CONT08: DSP Output Setting Write during control or system reset. Name Default CONT08 SELDO3 SELDO3 SELDO2 SELDO2 SELDO1 SELDO1 SELDO4 SELDO4 D7, D6: SELDO3[1:0] SDOUT1 Output Select SELDO3 Mode SELDO3[1:0] Output Data Select DSP DOUT3 (default) SRCO/SRIN1 DSP IRPT DSP DOUT5 D5, D4: SELDO2[1:0] SDOUT2 Output Select SELDO1 Mode...
  • Page 40 [AK7722] 10. CONT09: MUX Setting Write during control or system reset. Name Default CONT09 MUX2E MUX2[2] MUX2[1] MUX2[0] Reserved MUX1[2] MUX1[1] MUX1[0] D7: MUX2E 0: MUX2 Disable (default) 1: MUX2 Enable 1[1/fs] group delay occurs when MUX2 is enabled. The signal selected by SELDO4[1:0] is output when MUX2 is disabled. D6, D5, D4: MUX2[2:0] MUX2 Output Setting MUX2[2:0] MUX2 Output...
  • Page 41 [AK7722] 11. CONT0A: SRC Setting Write during control or system reset. Name Default CONT0A BIEDGE IDIF[2] IDIF[1] IDIF[0] BIFS[1] BIFS[0] SEMIAUTO AUTOSEL D7: BIEDGE SRBICKn edge select when using SRC 0: Falling edge against SRLRCKn edge. (default) 1: Rising edge against SRLRCKn edge. This setting is enable only when SRC input interface is PCM mode (IDIF mode 6/7) (Refer to IDIF[2:0] D6~D4) D6, D5, D4: IDIF[2:0] SRIN1-3 Input Interface Select...
  • Page 42 [AK7722] 12. CONT0B: MUX Setting Write during control reset. Name Default CONT0B Reserved TEST DSEL[1] DSEL[0] Reserved Reserved Reserved SETSRC D7: Reserved 0: Normal operation (default) Write “0” into this bit. D6: TEST 0: Normal operation (default) Write “0” into this bit. D5, D4: DSEL[1:0] SRC Input Select DSEL[1:0] SRC Input...
  • Page 43 [AK7722] 13. CONT0C: ADC Setting Name Default CONT0C TEST ASEL[2] ASEL[1] ASEL[0] TEST GDIF[2] GIDIF[1] GIDIF[0] D7: TEST 0: Normal operation (default) Write “0” into this bit. D6, D5, D4: ASEL[2:0] ADC Input Select ASEL Mode ASEL1[2:0] Selected Input Pin AIN1LP, AIN1LN, AIN1RP, AIN1RN (default) AIN2LP, AIN2LN, AIN2RP, AIN2RN...
  • Page 44 [AK7722] 14. CONT0D: Reset Name Default CONT0D AD2RST AD1RST ATSPAD GSRCRST DA2RST DA1RST ATSPDA SRCRST D7: AD2RST ADC2 Reset 0: ADC2 Reset Release (default) 1: ADC2 Reset In a system applications which do not need ADC2, set AD2RST bit = “1” for power saving. D6: AD1RST ADC1 Reset 0: ADC1 Reset Release (default) 1: ADC1 Rest...
  • Page 45 [AK7722] 15. CONT0E: Reset, Soft Mute Name Default CONT0E CRSTN DSPRSTN CKRSTN SMUTE SMUTE SMUTE SMUTE SMUTE D7: AD2SMUTE ADC2 SMUTE Setting 0: ADC2 SMUTE Release (default) 1: ADC2 SMUTE D6: AD1SMUTE ADC2 SMUTE Setting 0: ADC2 SMUTE Release (default) 1: ADC2 SMUTE D5: DA2SMUTE DAC2 SMUTE Setting 0: DAC2 SMUTE Release (default)
  • Page 46 [AK7722] 16. CONT10-13: ADC1, ADC2 Volume Setting Name Default CONT10 VOLA1L VOLA1L *VOLA1L *VOLA1L VOLA1L VOLA1L VOLA1L VOLA1L CONT11 VOLA1R VOLA1R *VOLA1R *VOLA1R VOLA1R VOLA1R VOLA1R VOLA1R CONT12 VOLA2R VOLA2R *VOLA2R *VOLA2R VOLA2R VOLA2R VOLA2R VOLA2R CONT13 VOLA2R VOLA2R *VOLA2R *VOLA2R VOLA2R VOLA2R...

  • Page 47: Power Up/Down Sequence

    [AK7722] ■ Power Up/Down Sequence 1. Power Up Sequence The AK7722 should be powered up when the INITRSTN pin= “L”. The analog REF voltage generator and power supply circuits for internal digital circuits are powered up by the INITRSTN pin = “H” after all power supplies are fed. The power up sequence between AVDD and DVDD is not critical.
  • Page 48 [AK7722] 2. Power Down Sequence It is recommended to execute initial reset (INITRSTN pin = “L”) before power-down the AK7722. Do not input any external signal after power-down the AK7722. (Current may flow via the protection diode.) DVDD, AVDD INITRSTN (pin) Power OFF Figure 19.
  • Page 49 [AK7722] 3. System Reset System reset is defined as when CRSTN bit = “0” (CONT0E D2) and DSPRSTN bit = “0” (CONT0E D1) after initial reset is released (INITRSTN pin = “L” → “H”). The state when CKRSTN bit = “0” (CONT0E D0) in system reset is called clock reset.
  • Page 50 [AK7722] 4. Clock Reset CKM[2:0] bits setting and Input clock ICLK (XTI@CKM Mode 0-2 or BICKI1@CKM Mode 3, SRBICKn@CKM mode 4 or LRCKI@CKM mode 5, SRLRCKn@CKM mode6) can be also changed during the clock reset as well as during initial reset. By this reset, both the PLL and the internal clocks stop and clock selection can be safely done during system reset.
  • Page 51 [AK7722] ■ Status Output Pin The STO (status output) pin outputs “H” during the INITRSTN pin is “L” if the AK7722 is powered-up. After initial reset is released, WDT (watchdog timer) error and CRC error status can be output from this pin by LDO shutdown signal and control register settings.
  • Page 52 [AK7722] ■ Audio Data Interface (Figure Serial audio data pins; the SDIN1, SDIN2, SDIN3, SDIN4, SDIN5, SDOUT1, SDOUT2, SDOUT3 pins, are interfaced with an external system, by LRCKI and BICKI (LRCKO and BICKO). Control register settings are needed to use these interfaces (Refer to the ■...
  • Page 53 [AK7722] Input Pin DIFPCM DIFI2S Input To Necessary Settings for the Supported Input Formats Path Selection SDIN1 DSP DIN1 None SDOUT1 pin SELDO1[1:0] bits= “01” DAC1 SELDO4[1:0] bits= “01” SDINDA1 MUX2[2:0] (Refer to P.41) Depends on PCM[1:0] SDIN2/JX1 DSP DIN2 JX1E bit= “0”...
  • Page 54 [AK7722] Output Pin DIFPCM DIFI2S Output From Necessary Settings for the Supported Output Path Selection Format SDOUT1/GP0 DSP DOUT1 SELDO1[1:0] bits= “00” OUT1E bit= “1” SDIN1 pin SELDO1[1:0] bits= “01” OUT1E bit= “1” ADC1 SELDO1[1:0] bits= “10” SDOUTAD1 OUT1E bit= “1” SDOUT2 DSP DOUT2 SELDO2[1:0] bits= “00”...
  • Page 55 [AK7722] 1. MSB, LSB justified Formats 1) Master Mode (CKM Mode 0, 1) MSB justified (24bit), BICKO=64fs CONT01 D7 CONT01 D6 CONT01 D5 CONT01 D4 CONT00 D1,D2 DIFPCM DIFI2S PCM[1] PCM[0] BITFS Left ch Right ch LRCKO BICKO 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 SDIN1, 2...
  • Page 56 [AK7722] 3) Slave Mode (CKM Mode 2, 3, 4) MSB justified (24bit), BICK/SRBICKn=64fs CONT01 D7 CONT01 D6 CONT01 D5 CONT01 D4 CONT00 D1,D2 DIFPCM DIFI2S PCM[1] PCM[0] BITFS Left ch Right ch LRCKI/SRLRCKn BICKI/SRBICKn 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 SDIN1, 2 M: MSB, L: LSB...
  • Page 57 [AK7722] 2. I S Compatible Format 1) Master Mode (CKM Mode 0, 1) CONT01 D7 CONT01 D6 CONT01 D5 CONT01 D4 CONT00 D1, D2 DIFPCM DIFI2S PCM[1] PCM[0] BITFS Left ch Right ch LRCKO BICKO 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 SDIN1, 2 M: MSB, L: LSB...
  • Page 58 [AK7722] 3. PCM Format 1) PCM Mode 0 (CKM Mode 2, 3, 4) CONT01 D7 CONT01 D6 CONT01 D5 CONT01 D4 CONT00 D1,D2 DIFPCM DIFI2S PCM[1] PCM[0] BITFS tBICK LRCKI BICKI 63 62 61 60 59 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 SDIN1, 2 22 21 20 19...
  • Page 59 [AK7722] 3) PCM Mode 2 (CKM Mode 2, 3, 4) CONT01 D7 CONT01 D6 CONT01 D5 CONT01 D4 CONT00 D1,D2 DIFPCM DIFI2S PCM[1] PCM[0] BITFS 1 ≤ tBICK ≤ 60 LRCKI BICKI 62 61 60 59 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 SDIN1, 2 tBICK...

  • Page 60: General Purpose Output

    [AK7722] 4. General Purpose Output The AK7722 has tow ports for general purpose outputs (GP0 and GP1 pins). SELDO1[1:0] bits (CONT08 D3, D2) switch the control of the SDOUT1/GP0 pin. Output control can be done by the DSP programs. The GP0 and GP1 pins output “L”...
  • Page 61 [AK7722] 2. Command Code BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R/W flag Area to be accessed Accompanying data to the access area R/W Flag Write at “1”, Read at “0”. Access data and accompanying data BIT6 BIT5 BIT4 BIT3~0 number of write Write preparation to CRAM during RUN...
  • Page 62 [AK7722] 4. Data Length of write data is depending on the writing area size. When accessing RAM, data may be written from sequential address locations by reading data continuously. ■Write Command Address Data Length Description Code Write preparation to CRAM during RUN. BIT3 ~ BIT0 of the command code assign # of write operation (80h:1, 80h~8Fh 16bit...
  • Page 63 [AK7722] 5. Echo-Back Mode The AK7722 has an Echo-back mode where written-data is output on the SO pin one after another. 1. Write COMMAND ADDRESS1 ADDRESS2 DATA1 DATA2 “L” or “H” Fix COMMAND ADDRESS1 OLD ECHO COMMAND ADDRESS1 ADDRESS2 DATA1 DATA2 COMMAND Data is output on SO delaying the time for 8bit from SI input.
  • Page 64 [AK7722] 6. Format 6-1. Write Operation during System Reset 1. Program RAM (PRAM) Writing (during System Reset) (1) COMMAND (2) ADDRESS1 0 0 0 0 0 0 0 0 (3) ADDRESS2 0 0 0 0 0 0 0 0 (4) DATA1 0 0 0 0 D35 D34 D33 D32 (5) DATA2 D31~D24...
  • Page 65 [AK7722] 6-3. Write Operation during Run 1. Coefficient RAM (CRAM) writing (during Run) Input (1) COMMAND 80h~8Fh (one data at 80h, sixteen data at 8Fh) (2) ADDRESS1 0 0 0 0 A11 A10 A9 A8 (3) ADDRESS2 A7~A0 (4) DATA1 D23~D16 (5) DATA2 D15~D8...
  • Page 66 [AK7722] 6-4. Read Operation during System Reset 1. Program RAM (PRAM) Reading (during System Reset) Input Output (1) COMMAND (2) ADDRESS1 0 0 0 0 0 0 0 0 (3) ADDRESS2 0 0 0 0 0 0 0 0 (4) DATA1 0 0 0 0 D35 D34 D33 D32 (5) DATA2 D31~D24...
  • Page 67 [AK7722] 6-5. Read Operation during System Reset and Run 1. Control Register Reading (during System Reset and Run) Input Output (1) COMMAND 40h~4Dh, 50h~57h (2) DATA D7~D0 2. Device Identification (during System Reset and Run) Input Output (1) COMMAND (2) DATA 3.
  • Page 68 [AK7722] 7. Timing 7-1. RAM Writing Timing during System Reset Write to Program RAM (PRAM), Coefficient RAM (CRAM) and Offset REG (OFREG) during System Reset in the order of Command code, Address and Data. The PRAM address is fixed to 0h. When writing Data to consecutive address locations, continue to input data only.
  • Page 69 [AK7722] 7-2. RAM Writing Timing during RUN Use this operation to rewrite Coefficient RAM (CRAM) and Offset REG(OFREG) during RUN. 1. Write Preparation After inputting the assigned command code (8-bit) to select the number of data from 1 to 16, input the Starting Address of write (16-bit all 0) and the number of data assigned by command code in this order.
  • Page 70 [AK7722] SCLK don’t care don’t care (L/H) (L/H) Address DATA DATA DATA DATA DATA Echo back output RDY= “H” Figure 30. CRAM, OFREG Write Preparation Confirm DSPRSTN= “1” SCLK Command 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 don’tcare don’tcare (L/H)
  • Page 71 [AK7722] 7-3. External Conditional Jump External Conditional Jump Code Writing (during System Reset and RUN) (1) COMMAND (2) DATA D7~D0 External Conditional Jump code can be input during both DSP Reset and RUN. Input data is set to the designated register on the rising edge of LRCKO.
  • Page 72 [AK7722] DSPRSTN= “1” SCLK don’tcare D7 … D0 don’tcare (L/H) (L/H) L ch R ch LRCKO max 2LRCK max0.25LRCK Figure 33. External Conditional Jump Timing (during RUN) 7-4. RAM Reading Timing during System Reset Read Program RAM (PRAM), Coefficient RAM (CRAM) and Offset REG (OFREG) during System Reset in the order of input Command code and Address.
  • Page 73 [AK7722] DSPRSTN (Control Register Setting is Omitted SCLK don’tcare don’tcare Command Address (L/H) (L/H) Echo Back Output DATA RDY = “H” Figure 35. RAM Reading during System Reset and RUN ■ C Bus Interface (I2CSEL= “H”) Access to the AK7722 registers and RAM is processed by I²C bus. The format of the I²C is complement with fast mode (max: 400kHz).

  • Page 74: Start Condition

    [AK7722] 1-2. Start condition and Stop Condition A Start condition is generated by the transition of “H” to “L” on the SDA line while the SCL line is “H”. All instructions are initiated by a Start condition. A Stop condition is generated by the transition of “L” to “H” on SDA line while SCL line is “H”.
  • Page 75 [AK7722] Clock pulse for acknowledge SCL FROM MASTER DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY acknowledge RECEIVER START CONDITION Figure 39. Generation of Acknowledgement 1-5. The First Byte The First Byte which includes the Slave-address is input after the Start condition is set, and a target IC device that will be accessed on the bus is selected by the Slave-address.
  • Page 76 [AK7722] Example) When transferring / receiving A1B2C3 (hex) 24-bit serial data in microprocessor interface format: (1) Microcomputer interface format (1) I C format 24BIT 8BIT 8BIT 8BIT A …Acknowledge Figure 41. Division of Data Note 58. In this document, there is a case that describes a write instruction command code which is received at the second byte as “Write Command”.
  • Page 77 [AK7722] Command Address Data length Description Code 3byte × n Write preparation to CRAM during RUN. 80h-8Fh 2byte BIT3 ~ BIT0 of the command code assign # of write operation (80h:1, 81h:2,…, 8Fh: 16). Write operation exceeding the assigned # of write, abandons the data.
  • Page 78 [AK7722] 3. Read Sequence In the AK7722, when a “write- slave-address assignment” is received at the first byte, the read command at the second byte and the data at the third and succeeding bytes are received. At the data block, the address is received in a single byte unit in accordance with a read command code.

  • Page 79: Slave-Address

    [AK7722] 4. Acknowledgement Polling The AK7722 cannot receive instructions while the RDY pin (Data Write Ready pin) is at a low level. The maximum transition time of the RDY pin from low level to high level is specified in the “■...
  • Page 80 [AK7722] 4-4. When Read Slave-address assignment is received without receiving Read command code Data read in the AK7722 can be made only in the previously documented Read sequence. Data cannot be read out without receiving a read command code. In the AK7722, a “Not Acknowledged” is generated when a “Read Slave-address Assignment”...
  • Page 81 [AK7722] Note: The meaning of symbols in I C format figures. …Slave Address (7 bits) SLAD …Command Code (8 bits) …Start Condition …Repeated Star tCondition …Stop Condition …R / W bit, the lowest bit of the first byte is at write (= 0) condition, Write ( 1 bit ) …R / W bit, the lowest bit of the first byte is at read (= 1) condition, Read ( 1 bit ) …Acknowledge (1 bit) …Not Acknowledge (1 bit)

  • Page 82: Adc Block

    [AK7722] ■ ADC Block 1. ADC High-pass filter The AK7722 ADC has digital High Pass Filter (HPF) for DC offset cancellation. The cut-off frequency of the HPF is approximately 1Hz (at fs=48kHz). This cut-off frequency is shown below. 48kHz 44.1kHz 8kHz Sampling frequency (fs) 0.93Hz...
  • Page 83 [AK7722] 4. ADC (ADC1, ADC2) Digital Volume The AK7722 has channel-independent digital volume control ( 256 levels, 0.5dB step). ADC1 Lch ADC1 Rch Attenuation Level VOLA1L [7:0] VOLA1R [7:0] ADC2 Lch ADC2 Rch Attenuation Level VOLA2L [7:0] VOLA2R [7:0] +24.0dB +23.5dB +23.0dB +0.5dB...
  • Page 84 [AK7722] CODE CODE CODE CODE CODE CODE CODE CODE 24.0 20h 8.0 40h -8.0 60h -24.0 80h -40.0 A0h -56.0 C0h -72.0 E0h -88.0 23.5 21h 7.5 41h -8.5 61h -24.5 81h -40.5 A1h -56.5 C1h -72.5 E1h -88.5 23.0 22h 7.0 42h -9.0 62h -25.0 82h...
  • Page 85 [AK7722] 5. ADC1 Input selector switching sequence The input selector should be changed after soft mute to avoid the switching noise of the input selector (Figure 49). · Input selector switching sequence. 1. Enable the soft mute before changing channel. 2.
  • Page 86 [AK7722] ■ DAC Blocks 1. DAC Digital Volume Control The DACs of the AK7722 have channel-independent digital volume control (256 levels, 0.5dB step). The VOLDA1L[7:0], VOLDA1R[7:0] (DAC1), VOLDA2L[7:0] and VOLDA2R[7:0] (DAC2) bit set the volume level of each DAC channel. (Table 8) DAC2 Lch DAC2 Rch DAC1 Lch...
  • Page 87 [AK7722] CODE CODE CODE CODE CODE CODE CODE CODE 12.0 -4.0 -20.0 -36.0 -52.0 -68.0 -84.0 -100.0 11.5 -4.5 -20.5 -36.5 -52.5 -68.5 -84.5 -100.5 11.0 -5.0 -21.0 -37.0 -53.0 -69.0 -85.0 -101.0 10.5 -5.5 -21.5 -37.5 -53.5 -69.5 -85.5 -101.5 10.0 -.6.0...
  • Page 88 [AK7722] 2. DAC Soft Mute Control The DACs have a soft mute function. The soft mute operation is performed at digital domain. When the DA1SMUTE and DA2SMUTE bits go to “1”, the output signal is attenuated by -∞ during VOLDA** × ATT Speed transition time from the current ATT level.
  • Page 89 [AK7722] ■ SRC Block 1. Sampling rate The AK7722 includes a stereo digital sampling rate converter (SRC). The input sampling rate is supported from 7.35kHz to 96kHz(FSI). The output sampling frequency (FSO) is 7.35kHz ~ 48kHz. When sampling rate ratio FSO/FSI is more than 1, the output sampling rate is converted to 7.35kHz ~ 48kHz.
  • Page 90 [AK7722] 2. SRC Input/Output Interface 2-1. Input Interface Format The AK7722 has three input ports for SRC (SRIN1-3 pins). DSEL[1:0] bits (CONT 0B D5, D4) control the input ports switching. An internal system clock is generated by the internal PLL using SRBICK1-3 (SETSRC bit =“0”) or SRLRCK1-3 (SETSRC bit = “1”).
  • Page 91 [AK7722] D3, D2: BIFS[1:0] SRBICK1-3 Select BIFS Mode BIFS[1] BIFS[0] SRBICK1-3 32fsi (default) 64fsi 128fsi Note 70. This setting is necessary when operating PLL by SRBICK1-3 pins (SETSRC bit= “0”) or in IDIF mode6/7. 128fsi supports to fsi=48kHz. Table 12. SRBICK1-3 Select Left ch Right ch SRLRCK1-3...
  • Page 92 [AK7722] SRLRCK1-3 Left ch Right ch SRBICK1-3 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 SRIN1-3 M: MSB, L: LSB 22 21 20 3 2 1 L 22 21 20...
  • Page 93 [AK7722] 1 ≤ tBICK ≤ 60 SRLRCK1-3 SRBICK1-3 62 61 60 59 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 SRIN1-3 M: MSB, L: LSB tBCLK 22 21 20 19...
  • Page 94 [AK7722] 2-2. Output Interface Format The SRC output format is fixed to MSB justified 24-bit 2’s complement. It outputs a data synchronizing with internal clock LRCKO and BICKO. The output sampling rate is fs=48kHz or fs=44.1kHz. I²S compatible format is available by setting a control register CONT0 DIFI2S bit = “1”.
  • Page 95 [AK7722] 3. Soft Mute Operation 3-1. Manual Mode The soft mute operation is performed in the digital domain of the SRC output. When SRCSMUTE bit is set to “1”, the SRC output data are attenuated by −∞ during 1024 LRCLKO cycles. When the SRCSMUTE bit is set to “0” the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCLKO cycles.
  • Page 96 [AK7722] SRCRST “H” SRCSMUTE Don’t Care “L” 2205/fso(SAUTOSEL=0) @44.1kHz,48kHz 8820/fso(SAUTOSEL=1) Attenuation @44.1kHz,48kHz -∞ SRCO (1) The output data is attenuated by 0dB during 1024LRCKO cycles (1024/fso). (2) The digital output corresponding to the digital input has group delay, GD. Figure 60. Soft Mute Semi-Auto Mode 4.
  • Page 97 [AK7722] Case 2 External clocks Input Clocks Don’t care (No Clock) (Input port) SRCI (Don’t care) Input Data Don’t care External clocks Output Clocks (Don’t care) Don’t care (Output port) < 200ms(SETSRC=”1”) SRCRST < 50ms(SETSRC=”0”) PLL lock & Normal Power-down (Internal state) Power-down PLL Unlock...
  • Page 98 [AK7722] 6. SRCPLL 6-1. SETSRC bit SETSRC bit (CONT0: D0) selects a locked clock of SRCPLL. Normally this setting is fixed. PLL lock can be applied to SRBICK1-3 when BIFS[1:0] bits (CONT0A: D3, D2) setting is 32fsi, 64fsi or 128fsi. SETSRC Mode SETSRC bit PLL Lock Pin...
  • Page 99 [AK7722] ■ GSRC (Up-convertor for Guidance Voice Interruption) 1. General 1-1. Sampling Rate The AK7722 has a Guidance SRC (GSRC) for up-converting mono voice data. It converts the sampling rate of guidance or phone call voice from 7.35kHz~12kHz (FSI) to 44.1kHz/48kHz (FSO). [Up-sampling] Supported sampling rate is shown below.
  • Page 100 [AK7722] GLRCK Left ch Right ch GBICK SDIN5 Don’t care M 18 17 16 15 14 IDIF Mode 1 M: MSB, L: LSB Figure 66. GIDIF Mode 1 @GBICK 64fs GLRCK Left ch Right ch GBICK 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0...
  • Page 101 [AK7722] ■ MUX1 GSRC and ADC2 serial data are output from MUX1. These signals can be switched by MUX1[2:0] bits. The delay time of GSRC and ADC2 serial outputs via MUX1 is 1Ts (1/fs). MUX1[2:0] MUX1 Output 000 (Default) ADC2L ADC2R ADC2R ADC2L...

  • Page 102: System Design

    [AK7722] SYSTEM DESIGN Figure 70 Figure 71 shows the system connection diagram. An evaluation board (AKD7722) is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. <Serial Interface Mode> Digital +3.3V 0.1μ 0.1μ 0.1μ 10μ DVDD ×...
  • Page 103 [AK7722] <I C Mode> Digital +3.3V 0.1μ 0.1μ 0.1μ 10μ DVDD × 3 “H” I2CSEL CLKO BICKO LRCKO SDOUT1 Micom SDOUT2 CAD0 SDOUT3 AK7722 CAD1 CLOCK SRLRCK1 SRBICK1 SRIN1 & SRLRCK2 INITRSTN RESET SRBICK2 CONTROL Audio I/F SRIN2 TESTI1 SRLRCK3 SRBICK3 TESTI2 Digital Ground...

  • Page 104: Peripheral Circuits

    [AK7722] (2) Peripheral Circuits 1. Ground and Power Supply To minimize digital noise coupling, AVDD and DVDD should be individually de-coupled at the AK7722. System analog power is supplied to AVDD. VSS1-6 should be connected to the same analog ground. Decoupling capacitors, particularly ceramic capacitors of small capacity, should be connected at positions as close as possible to the AK7722.

  • Page 105: Analog Output

    [AK7722] 4. Analog Output 8.2k 4.16Vpp 2.08Vpp 8.2k AOUT- 270p +12V VAOUT 2.2n AOUT+ LME49720MA 8.2k +12V 8.2k 270p 4.7k 2.08Vpp 4.7k 0.1u Figure 73. External LPF Circuit Example The analog output is full differential. The output range is ±2.08Vpp (typ.) centered on AVDD/2 (typ). The differential outputs are summed externally, VAOUT = (AOUT+) - (AOUT-) between AOUT+ and AOUT-.
  • Page 106 [AK7722] 7. LFLT Pin External Connection The LFLT pin should be connected a capacitor with the following specification. CKM Mode DFS[1:0] BITFS[1:0] 0, 1, 2 0, 1, 2, 3 0, 1, 2 8.2[kΩ] 33[nF] None 3, 4 0, 1 ±5% ±30% None or 1, 2...
  • Page 107 [AK7722] PACKAGE 80pin LQFP (Unit: mm) 1.60 Max. 14.0±0.2 12.0 0.05~0.15 0.09~0.20 0.22±0.05 0.10 M 0°~10° 0.60±0.15 0.10 ■ Materials and Lead Specification Package: Epoxy Lead frame: Copper Lead-finish: Soldering (Pb free) plate MS1328-E-00 - 107 - 2011/09...

  • Page 108: Revision History

    [AK7722] MARKING AK7722VQ XXXXXXX 1) Pin#1 indication 2) Date Code: XXXXXXX (7 digits) 3) Marking Code: AK7722VQ REVISION HISTORY Date (YY/MM/DD) Revision Reason Page Contents 11/09/09 First Edition MS1328-E-00 - 108 - 2011/09...

  • Page 109: Important Notice

    [AK7722] IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products.

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