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7.4.2
DTV T2 reception
The Front-End for DVT part consist of the following key
components:
•
TUNER EUROPE TDSY-G480D
•
SCALER MT5593FPIJ HSBGA-900 Processor
•
DEMODULATOR Si2168-C50-GMR QFN-48
Below find a block diagram of the front-end application for DTV
part.
TDSY-G408D
2
I
C
IF-AGC
IF_AGC
RF_AGC
Figure 7-7 Front-End DVB-T2 DTV block diagram
7.4.3
Front-End DTV-S2 reception
The Front-End for ISTB part consist of the following key
components:
•
TUNER EUROPE TDQS-A701F
•
SCALER MT5593FPIJ HSBGA-900 Processor
•
DEMODULATOR Si2166-C50-GMR QFN48
Below find a block diagram of the front-end application for DTV
part.
S2 function
LNB power
S2 tuner
Tuner I2C
S2 Demond
SI2169
IP/IN/OP/ON
Tuner I2C
Figure 7-8 Front-End DVB-S2 DTV block diagram
I
2
C
IF
DECODER
Si2168
TS DATA
2
I
MT5593
20050_204.eps
System I2C
MT5593
TS DATA
20050_205.eps
Circuit Descriptions
7.5
HDMI
Refer to figure
RX
TX
I
2
CN505
HDMI1
C
The following HDMI connector can be used:
•
HDMI 1: HDMI input ( TV digital interface support
HDMI1.4/HDCP1.3) with digital audio/PC DVI input/ARC
•
HDMI 2: HDMI input ( TV digital interface support HDCP)
with digital audio/PC DVI input/ARC
•
HDMI 3: HDMI input ( TV digital interface support
HDMI1.4/HDCP1.3) with digital audio/PC DVI input/ARC
•
HDMI 4: HDMI input ( TV digital interface support
HDMI1.4/HDCP1.3) with digital audio/PC DVI input/ARC
•
+5V detection mechanism
•
Stable clock detection mechanism
•
HPD control
•
CEC control
7.6
Video and Audio Processing - MT5593FPIJ
The MT5593FPIJ is the main audio and video processor (or
System-on-Chip) for this platform. It has the following features:
•
ATSC /DVB-T /DVB-C/DTMB demodulators
•
Ture 120HZ Full HD MJC
•
Power CPU core
•
3D graphic support OpenGL ES 1.1/2.0
•
A muti-standard video decoder
•
A transport de-multiplexer
•
One HDMI 2.0 receiver with 3D support
•
MHL2.0& Standby charging
•
2D/3D converter
•
Rich format audio codec
•
Local dimming (LED backlight)
•
Ethernet MAC+PHY
•
TCON
•
Panel overdrive control
•
Four-link LVDS, mini-LVDS,V-by-one, EPI
The MT5593FPIJ family consists of a DTV front-end
demodulator, a backend decoder and a TV controller and offers
high integration for advanced applications. It integrates a
transport de-multiplexer, a high definition video decoder, an
audio decoder, a four-link LVDS transmitter, a mini-LVDS
transmitter, a V-by-one transmitter, an EPI transmitter, and an
NTSC/PAL/SECAM TV decoder with 3D comb
filter(NTSC/PAL).
The MT5593FPIJ enables consumer electronics
manufacturers to build high quality, low cost and feature-rich
DTV.
The MT5593PFIJ family supports Full-HD
MPEG1/2/4/H.264/VC1/RM/AVS/ and H.264/HEVC video
decoder standards, and JPEG. The MT5593FPIJ also supports
Media Tek MDDi de-interlace solution which can reach very
smooth picture quality for motions. A 3D comb filter added to
the TV decoder recovers great details for still pictures. The
back to
div.table
QM16.4E LA
7-9 HDMI input configuration
MT5593
C
TX
I
2
C
I
2
C
RX
RX
CN504
CN502
HDMI2
HDMI3
Figure 7-9 HDMI input configuration
7.
EN 35
for the application.
2
I
C
TX
RX
CN501
HDMI4
20050_206.eps
2016-Apr-1
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