GigaDevice Semiconductor GD32VW55 Series User Manual

Risc-v 32-bit mcu for gd32vw553xx

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GigaDevice Semiconductor Inc.

GD32VW55x

RISC-V 32-bit MCU

For GD32VW553xx

User Manual

Revision 1.0

( Oct. 2023 )

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Page 1 GigaDevice Semiconductor Inc. GD32VW55x RISC-V 32-bit MCU For GD32VW553xx User Manual Revision 1.0 ( Oct. 2023 )
Page 2: Table Of Contents
GD32VW55x User Manual Table of Contents Table of Contents ......................2 List of Figures ......................16 List of Tables ........................ 21 1. System and memory architecture ................ 23 1.1. RISC-V processor ...................... 23 1.2. System architecture ....................24 1.3. Memory map ......................25 1.3.1.
Page 3 GD32VW55x User Manual 2.3.9. Wirte protection ........................50 2.3.10. FLASH interrupts ........................51 Register definition ..................... 52 2.4. 2.4.1. Unlock key register (FMC_KEY) ................... 52 2.4.2. Option byte unlock key register (FMC_OBKEY) ..............52 2.4.3. Status register (FMC_STAT) ....................52 2.4.4.
Page 4 GD32VW55x User Manual 3.4.11. HUK key register x (EFUSE_HUKKEYx) (x = 0…3) ............. 73 3.4.12. User data register x (EFUSE_USER_DATAx) (x = 0…7) ............. 73 3.4.13. Boot address register (EFUSE_BOOTADDR) ..............74 4. Power management unit (PMU) ................75 Overview ........................75 4.1.
Page 5 GD32VW55x User Manual 5.3.8. APB1 reset register (RCU_APB1RST) ................115 5.3.9. APB2 reset register (RCU_APB2RST) ................116 5.3.10. AHB1 enable register (RCU_AHB1EN) ................118 5.3.11. AHB2 enable register (RCU_AHB2EN) ................120 5.3.12. AHB3 enable register (RCU_AHB3EN) ................120 5.3.13. APB1 enable register (RCU_APB1EN) ................121 5.3.14.
Page 6 GD32VW55x User Manual 7.3.8. Alternate function (AF) configuration .................. 147 7.3.9. GPIO locking function ......................148 7.3.10. GPIO I/O compensation cell ....................148 7.3.11. GPIO single cycle toggle function ..................148 Register definition ....................149 7.4. 7.4.1. Port control register (GPIOx_CTL, x = A…C) ..............149 7.4.2.
Page 7 GD32VW55x User Manual Block diagram ...................... 172 10.3. Function overview ....................172 10.4. 10.4.1. Peripheral handshake ......................174 10.4.2. Data process ........................175 10.4.3. Address generation ......................180 10.4.4. Circular mode........................181 10.4.5. Switch-buffer mode ......................181 10.4.6. Transfer flow controller ....................... 182 10.4.7.
Page 8 GD32VW55x User Manual Analog to digital converter (ADC) ..............207 Overview ....................... 207 12.1. Characteristics ..................... 207 12.2. Pins and internal signals ..................208 12.3. Function overview ....................209 12.4. 12.4.1. ADC clock .......................... 209 12.4.2. ADCON switch........................209 12.4.3. Routine sequence ......................
Page 9 GD32VW55x User Manual 13.2.2. Characteristics ........................236 13.2.3. Function overview ....................... 236 13.2.4. Register definition ....................... 239 Real time clock (RTC) ..................241 Overview ....................... 241 14.1. Characteristics ..................... 241 14.2. Function overview ....................242 14.3. 14.3.1. Block diagram ........................242 14.3.2.
Page 10 GD32VW55x User Manual 14.4.17. Tamper register (RTC_TAMP) .................... 269 14.4.18. Alarm 0 sub second register (RTC_ALRM0SS) ..............271 14.4.19. Alarm 1 sub second register (RTC_ALRM1SS) ..............272 14.4.20. Backup registers (RTC_BKPx) (x = 0…19) ................ 273 Timer (TIMERx) ....................275 15.1.
Page 11 GD32VW55x User Manual 16.3.8. LIN mode ..........................422 16.3.9. Synchronous mode ......................423 16.3.10. IrDA SIR ENDEC mode ...................... 424 16.3.11. Half-duplex communication mode ..................426 16.3.12. Smartcard (ISO7816-3) mode .................... 426 16.3.13. ModBus communication ..................... 428 16.3.14. Receive FIFO ........................428 16.3.15.
Page 12 GD32VW55x User Manual Register definition ....................478 17.4. 17.4.1. Control register 0 (I2C_CTL0) .................... 478 17.4.2. Control register 1 (I2C_CTL1) .................... 480 17.4.3. Slave address register 0 (I2C_SADDR0) ................482 17.4.4. Slave address register 1 (I2C_SADDR1) ................483 17.4.5. Timing register (I2C_TIMING) .................... 484 17.4.6.
Page 13 GD32VW55x User Manual 19.3.3. QSPI signal line modes ...................... 514 19.3.4. CSN and SCK ........................514 Operating modes ....................514 19.4. 19.4.1. Normal mode ........................515 19.4.2. Read polling mode ......................516 19.4.3. Memory map mode ......................517 QSPI configuration ....................517 19.5.
Page 14 GD32VW55x User Manual CAU suspended mode ..................548 20.8. Register definition ....................550 20.9. 20.9.1. Control register (CAU_CTL) ....................550 20.9.2. Status register 0 (CAU_STAT0) ..................551 20.9.3. Data input register (CAU_DI) ....................552 20.9.4. Data output register (CAU_DO) ..................553 20.9.5.
Page 15 GD32VW55x User Manual 22.2. Characteristics ..................... 575 22.3. Function overview ....................575 22.3.1. Operands ..........................576 22.3.2. RSA algorithm ........................576 22.3.3. ECC algorithm........................578 22.3.4. Integer arithmetic operations ....................579 22.3.5. Elliptic curve operations in Fp domain ................589 22.3.6.
Page 16: List Of Figures
GD32VW55x User Manual List of Figures Figure 1-1. GD32VW55x system architecture ................25 Figure 2-1. Process of page erase operation ................45 Figure 2-2. Process of mass erase operation ................46 Figure 2-3. Process of word program operation ..............48 Figure 3-1.
Page 17 GD32VW55x User Manual Figure 13-2. Window watchdog timer block diagram ............237 Figure 13-3. Window watchdog timing diagram ..............238 Figure 14-1. Block diagram of RTC ..................242 Figure 15-1. Advanced timer block diagram ................277 Figure 15-2. Normal mode, internal clock divided by 1 ............278 Figure 15-3.
Page 18 GD32VW55x User Manual Figure 15-41. Channel input capture principle ..............340 Figure 15-42. Channel output compare principle (x=0,1,2,3) ..........341 Figure 15-43. Output-compare in three modes ..............342 Figure 15-44. Timing chart of EAPWM ..................343 Figure 15-45. Timing chart of CAPWM ..................343 Figure 15-46.
Page 19 GD32VW55x User Manual Figure 17-1. I2C module block diagram .................. 452 Figure 17-2. Data validation ..................... 453 Figure 17-3. START and STOP condition ................454 Figure 17-4. I2C communication flow with 10-bit address (Master Transmit) ....454 Figure 17-5. I2C communication flow with 7-bit address (Master Transmit) ...... 455 Figure 17-6.
Page 20 GD32VW55x User Manual Figure 20-9. AES ECB decryption ................... 540 Figure 20-10. AES CBC encryption ..................541 Figure 20-11. AES CBC decryption ..................542 Figure 20-12. Counter block structure ..................542 Figure 20-13. AES CTR encryption / decryption ..............543 Figure 21-1.
Page 21: List Of Tables
GD32VW55x User Manual List of Tables Table 1-1. The interconnection relationship of the AHB interconnect matrix...... 24 Table 1-2. Memory map of GD32VW55x devices ..............26 Table 1-3. BOOT0 modes ......................30 Table 1-4. BOOT1 modes ......................30 Table 1-5. Boot address modes ....................30 Table 2-1.
Page 22 GD32VW55x User Manual Table 15-6. Complementary outputs controlled by parameters .......... 382 Table 16-1. Description of USART important pins..............414 Table 16-2. Configuration of stop bits ..................415 Table 16-3. USART interrupt requests ..................429 Table 17-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) ........................
Page 23: System And Memory Architecture
GD32VW55x User Manual System and memory architecture The devices of GD32VW55x series devices are 32-bit general-purpose microcontrollers based on the Nuclei N307 processor. The N307 processor is based on the RSIC-V architecture instruction set, hereinafter referred to as the RISC-V processor. The RISC-V processor includes two AHB buses known as I-Cache bus and System bus.
Page 24: System Architecture
GD32VW55x User Manual System architecture 1.2. A 32-bit multilayer bus is implemented in the GD32VW55x devices, which enables parallel access paths between multiple masters and slaves in the system. The multilayer bus consists of an AHB interconnect matrix, three AHB buses and two APB buses. The interconnection relationship of the AHB interconnect matrix is shown below.
Page 25: Memory Map
GD32VW55x User Manual SRAM0, SRAM1, SRAM2, SRAM3, AHB1, AHB2, APB1, APB2, QSPI and BLE. FMC is the bus interface of the flash memory controller. SRAM0~ SRAM3 is on-chip static random access memories. AHB1 is the AHB bus connected with all of the AHB1 slaves. AHB2 is the AHB bus connected with AHB2 slaves.
Page 26: Table 1-2. Memory Map Of Gd32Vw55X Devices
GD32VW55x User Manual registers and I/O ports are organized within the same linear 4-Gbyte address space. The maximum address range of the RISC-V is 4-Gbyte due to its 32-bit bus address width. Additionally, a pre-defined memory map is provided by the RISC-V processor to reduce the software complexity of repeated implementation of different device vendors.
Page 27 GD32VW55x User Manual Pre-defined Address Peripherals Regions 0x4002 B000 - 0x4002 BBFF Reserved 0x4002 A000 - 0x4002 AFFF Reserved 0x4002 8000 - 0x4002 9FFF Reserved 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF Reserved 0x4002 6000 - 0x4002 63FF 0x4002 5C00 - 0x4002 5FFF Reserved 0x4002 5800 - 0x4002 5BFF...
Page 28 GD32VW55x User Manual Pre-defined Address Peripherals Regions 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF 0x4001 2C00 - 0x4001 2FFF Reserved 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF 0x4001 1400 - 0x4001 1FFF...
Page 29: On-Chip Sram Memory
GD32VW55x User Manual Pre-defined Address Peripherals Regions 0x2101 0000 - 0x3FFF FFFF Reserved 0x2100 0000 - 0x2100 FFFF 0x2005 0000 - 0x20FF FFFF Reserved SRAM 0x2003 0000 - 0x2004 FFFF SRAM3 (96KB + shared 32KB) 0x2002 0000 - 0x2002 FFFF SRAM2 (64KB) 0x2001 0000 - 0x2001 FFFF SRAM1 (64KB)
Page 30: Table 1-5. Boot Address Modes
GD32VW55x User Manual the EFUSE_CTL0 register to free the GPIO pad if needed.  The BOOT1 value may come from the PB1 pin or from the value of SWBOOT1 bit in the EFUSE_CTL0 register to free the GPIO pad if needed. Table 1-3.
Page 31 GD32VW55x User Manual EFUSE_CTL0 register) is also re-sampled when exiting from Standby mode. Consequently, they must be kept in the required Boot mode configuration in Standby mode. After startup delay, the selection of the boot area is done before releasing the processor reset. The embedded bootloader is located in the System memory, which is used to reprogram the Flash memory.
Page 32: System Configuration Registers (Syscfg)
GD32VW55x User Manual System configuration registers (SYSCFG) 1.5. SYSCFG base address: 0x4001 3800 Configuration register 0 (SYSCFG_CFG0) 1.5.1. Address offset: 0x00 Reset value: 0x0000 000X (X indicates BOOT_MODE[1:0] may be any value according to the BOOT0 and BOOT1 pins) This register has to be accessed by word (32-bit). Reserved BOOT_MODE[1:0 Reserved...
Page 33: Exti Sources Selection Register 1 (Syscfg_Extiss1)
GD32VW55x User Manual 15:12 EXTI3_SS[3:0] EXTI 3 sources selection 0000: PA3 pin 0001: PB3 pin Other configurations are reserved. 11:8 EXTI2_SS[3:0] EXTI 2 sources selection 0000: PA2 pin 0001: PB2 pin Other configurations are reserved. EXTI1_SS[3:0] EXTI 1 sources selection 0000: PA1 pin 0001: PB1 pin Other configurations are reserved.
Page 34: Exti Sources Selection Register 2 (Syscfg_Extiss2)
GD32VW55x User Manual Other configurations are reserved. EXTI4_SS[3:0] EXTI 4 sources selection 0000: PA4 pin 0001: PB4 pin Other configurations are reserved. EXTI sources selection register 2 (SYSCFG_EXTISS2) 1.5.4. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved EXTI11_SS [3:0] EXTI10_SS [3:0]...
Page 35: I/O Compensation Control Register (Syscfg_Cpsctl)
GD32VW55x User Manual Reserved EXTI15_SS [3:0] EXTI14_SS [3:0] EXTI13_SS [3:0] EXTI12_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI15_SS[3:0] EXTI 15 sources selection 0000: PA15 pin 0001: PB15 pin 0010: PC15 pin Other configurations are reserved. 11:8 EXTI14_SS[3:0] EXTI 14 sources selection...
Page 36: Syscfg Configuration Register 1 (Syscfg_Cfg1)
GD32VW55x User Manual Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. CPS_RDY Compensation cell ready flag 0: I/O compensation cell not ready 1: I/O compensation cell ready Reserved Must be kept at reset value CPS_EN Compensation cell power-down 0: I/O compensation cell power-down mode 1: I/O compensation cell enabled SYSCFG configuration register 1 (SYSCFG_CFG1)
Page 37: Timer Trigger Selection Register (Syscfg_Timerxcfg)(X = 0
GD32VW55x User Manual SOWNSE Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. SOWNSEL Shared SRAM ownership select This bit is used to control the ownership of the shared 32K SRAM. 0: Wireless 1: Core TIMER trigger selection register (SYSCFG_TIMERxCFG)(x = 0..2) 1.5.9.
Page 38 GD32VW55x User Manual TSCFGy[3:0]. 27:24 TSCFG6[3:0] External clock mode 0 configuration This bit-field specifies which signal is selected as the trigger input, which is used to synchronize the counter. 0000: External clock mode0 disable 0001: Internal trigger input 0 (ITI0) 0010: Internal trigger input 1 (ITI1) 0011: Internal trigger input 2 (ITI2) 0100: Internal trigger input 3 (ITI3)
Page 39 GD32VW55x User Manual These bits must not be changed when slave mode is enabled. 15:12 TSCFG3[3:0] Restart mode configuration This bit-field specifies which signal is selected as the trigger input, which is used to synchronize the counter. 0000: Restart mode disable 0001: Internal trigger input 0 (ITI0) 0010: Internal trigger input 1 (ITI1) 0011: Internal trigger input 2 (ITI2)
Page 40: Device Electronic Signature
GD32VW55x User Manual Device electronic signature 1.6. The device electronic signature contains memory size information and the 96-bit unique device ID. It is stored in the information block of the Flash memory. The 96-bit unique device ID is unique for any device. It can be used as serial numbers, or part of security keys, etc. Memory density information 1.6.1.
Page 41 GD32VW55x User Manual UNIQUE_ID[63:48] UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF F7F0 The value is factory programmed and can never be altered by user. UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID...
Page 42: Flash Memory Controller (Fmc)
GD32VW55x User Manual Flash memory controller (FMC) 2.1. Overview The flash memory controller, FMC, provides all the necessary functions for the on-chip Flash Memory. There also provide page erase, mass erase, and word program for flash memory. 2.2. Characteristics  Two memory organizations: Main : Up to 4MB (typical : 2MB) of on-chip flash memory for instruction and data.
Page 43: Read Operations
GD32VW55x User Manual Note: The bootloader block cannot be programmed or erased by user. Read operations 2.3.2. The flash can be addressed directly as a common memory space. RTDEC function RTDEC function means that when reading data from flash, it can be decrypted in real time according to the EFUSE module's configuration of AES algorithm.
Page 44: Page Erase
GD32VW55x User Manual unlocking sequence consists of two write operations, which are writing 0x45670123 and 0xCDEF89AB to the FMC_OBKEY register. Then the hardware sets the OBWEN bit in the FMC_CTL register to 1. The software can reset OBWEN bit to 0 to protect the FMC_NODECx (x=0,1,2,3) / FMC_OFRG / FMC_OFVR registers.
Page 45: Mass Erase
GD32VW55x User Manual Figure 2-1. Process of page erase operation Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PER bit, Write FMC_ADDR Send the command to FMC by set START bit Is the BUSY bit is 0 Finish Mass erase...
Page 46: Main Flash Programming
GD32VW55x User Manual When the operation is executed successfully, the ENDF bit in the FMC_STAT register is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set. Since all flash data will be modified to a value of 0xFFFF_FFFF, the mass erase operation can be implemented using a program that runs in SRAM or using the debugging tool that accesses the FMC registers directly.
Page 47 GD32VW55x User Manual The following steps show the register access sequence of the programming operation.  Unlock the FMC_CTL register if necessary.  Check the BUSY bit in the FMC_STAT register to confirm that no flash memory operation is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished. ...
Page 48: Option Bytes
GD32VW55x User Manual Figure 2-3. Process of word program operation Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PG bit Perform word write by DBUS Is the BUSY bit is 0 Finish Note: 1.
Page 49: Security Protection
GD32VW55x User Manual Table 2-2. Option bytes Name Register map 12：SRAM1_RST 11：NRST_DPSLP Option byte register (FMC_OBR) 10：NRST_STDBY 9：NWDG_HW [7:0]：SPC[7:0] Option byte user value register [31:0]：USER[31:0] (FMC_OBUSER) Option byte write protection area [25:16]：WRP0_EPAGE[9:0] register 0 (FMC_OBWRP0) [15:0]：WRP0_SPAGE[9:0] Option byte write protection area [25:16]：WRP1_EPAGE[9:0] register 1 (FMC_OBWRP1) [15:0]：WRP1_SPAGE[9:0]...
Page 50: Wirte Protection
GD32VW55x User Manual the flash memory will be in protection level 1 state. • User mode: Code executing in user mode (boot flash) can access flash main memory, SRAM1 and backup registers with all operations (read, erase and program). • Debug, boot RAM and boot loader modes: In debug mode or when code is running from boot RAM or boot loader, the flash main memory, the backup registers and the SRAM1 are totally inaccessible.
Page 51: Flash Interrupts
GD32VW55x User Manual FLASH interrupts 2.3.10. Interrupts: end of operation / operation error. Table 2-4. Flash interrupt requests Interrupt Flag Description Clear method enable bit ENDF end of operation ENDIE Write 1 to corresponding bit erase / program on protected WPERR in FMC_STAT register ERRIE...
Page 52: Register Definition
GD32VW55x User Manual 2.4. Register definition FMC base address: 0x4002 2000 Unlock key register (FMC_KEY) 2.4.1. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). KEY[31:16] KEY[15:0] Bits Fields Descriptions 31:0 KEY[31:0] FMC_CTL unlock register These bits are only be written by software.
Page 53: Control Register (Fmc_Ctl)
GD32VW55x User Manual This register has to be accessed by word (32-bit). Reserved Reserved ENDF WPERR Reserved BUSY rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. ENDF End of operation flag bit When the operation executed successfully, this bit is set by hardware. The software can clear it by writing 1.
Page 54 GD32VW55x User Manual 0: No effect 1: Trigger an option bytes operation. This bit can only be written if OBWEN bit is set. This bit is only set by software, and is cleared when the BUSY bit is cleared in FMC_STAT.
Page 55: Address Register (Fmc_Addr)
GD32VW55x User Manual 1: Main flash page erase command Main flash program command bit This bit is set or clear by software 0: No effect 1: Main flash program command Note: This register should be reset after the corresponding flash operation completed. Address register (FMC_ADDR) 2.4.5.
Page 56: Option Byte Register (Fmc_Obr)
GD32VW55x User Manual 1: write protection is set Security protection level 1 state 0: Protection level 1 is reset 1: Protection level 1 is set Reserved Must be kept at reset value. Option byte register (FMC_OBR) 2.4.7. Address offset: 0x40 Reset value: 0xXXXX XXXX (Register bits 0 to 31 are loaded with values from flash memory when OBRLD is set or system reset.
Page 57: Option Byte User Value Register (Fmc_Obuser)
GD32VW55x User Manual Note: The security protection of the flash memory is subject to this bits field. Option byte user value register (FMC_OBUSER) 2.4.8. Address offset: 0x44 Reset value: 0xXXXX XXXX (Register bits 0 to 31 are loaded with values from flash memory when OBRLD is set or system reset.) This register can not be written if OBWEN bit is set.
Page 58: Option Byte Write Protection Area Register 1 (Fmc_Obwrp1)
GD32VW55x User Manual Option byte write protection area register 1 (FMC_OBWRP1) 2.4.10. Address offset: 0x4C Reset value: 0xXXXX XXXX (Register bits 0 to 31 are loaded with values from flash memory when OBRLD is set or system reset.) This register can not be written if OBWEN bit is set. This register has to be accessed by word (32-bit).
Page 59: Offset Region Register (Fmc_Ofrg)
GD32VW55x User Manual NODECx_SPAGE[9: Start page of NODEC region x (x=0,1,2,3). Offset region register (FMC_OFRG) 2.4.12. Address offset: 0x80 Reset value: 0x0000 1FFF This register can not be written if OBWEN bit is set. This register has to be accessed by word (32-bit). Reserved OF_EPAGE[12:0] Reserved...
Page 60: Product Id0 Register (Fmc_Pid0)
GD32VW55x User Manual Product ID0 register (FMC_PID0) 2.4.14. Address offset: 0x100 Reset value: 0xXXXX XXXX This register has to be accessed by word (32-bit). PID0[31:16] PID0[15:0] Bits Fields Descriptions 31:0 PID0[31:0] Product reserved ID code register These bits are read only by software. These bits are unchanged constant after power on.
Page 61: Rf Trim Register 1 (Fmc_Rft1)
GD32VW55x User Manual BLETXCAL[7:0] WIFITXCAL[7:0] THECAL[7:0] PABIAST1[3:0] PABIAST0[3:0] Bits Field Descriptions 31:24 BLETXCAL[7:0] BLE transmit power calibration value 23:16 WIFITXCAL[7:0] WIFI transmit power calibration value 15:8 THECAL[7:0] Thermal meter calibration value PABIAST1[3:0] The PA bias fine tune value. PABIAST0[3:0] The PA(Power Amplifier) bias coarse tune value. RF Trim register 1 (FMC_RFT1) 2.4.17.
Page 62 GD32VW55x User Manual WIFI_TRIM[15:0] Bits Field Descriptions 31:0 WIFI_TRIM[31:0] After the system is reset, it is loaded from the flash. After the WTPG is set to 1, it can be program, and the corresponding flash cannot be erased. In the register program process, the WTPG bit is set to 1. Until the BUSY bit is 0, it indicates the end of programing.
Page 63: Electronic Fuse (Efuse)
GD32VW55x User Manual Electronic fuse (EFUSE) 3.1. Overview The Efuse controller has Efuse macro that store system paramters. As a non-volatile unit of storage, the bit of Efuse macro cannot be restored to 0 once it is programmed to 1. According to the software opration, the Efuse controller can program all bits in the system parameters.
Page 64: Efuse Architecture
GD32VW55x User Manual Efuse architecture 3.3.2. The Efuse consists of up to 1024 bits storage cells organized into 128 bytes. Efuse uses 7- bit address encoding. The following table Table 3-1. Efuse address mapping shows the address. Table 3-1. Efuse address mapping ADDR [6:0] Efuse byte 000_0000...
Page 65 GD32VW55x User Manual Width Start Program- Read- Parameter Description Note address protected protected multiple times, further use EFUSE reserved register defined but can not x (EFUSE_RESx) rollback The AES key used to Read out after encrypt the firmware image system reset For more details, refer to User 7’d16...
Page 66: Read Operation
GD32VW55x User Manual Read operation 3.3.4. The value of the Efuse can only be accessed through the corresponding register. After system reset, the Efuse value take effect and reloaded to corresponding register. The following steps show the register access sequence of the Efuse reading operation. Clear the RDIF bit in EFUSE_CS register if it is set, and make sure there is no overstep boundary error.
Page 67: Register Definition
GD32VW55x User Manual 3.4. Register definition EFUSE base address: 0x4002 2800 Control and status register (EFUSE_CS) 3.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved OVBERIC RDIC PGIC Reserved OVBERIE RDIE PGIE Reserved OVBERIF RDIF...
Page 68: Address Register (Efuse_Addr)
GD32VW55x User Manual OVBERIF Overstep boundary error flag 0: No overstep boundary error occurred 1: Overstep boundary error has occurred RDIF Read operation complete flag 0: Read Efuse operation not completed 1: Read Efuse operation completed PGIF Program operation completed flag 0: Program Efuse operation not completed 1: Program Efuse operation completed 15:2...
Page 69: Control Register 0 (Efuse_Ctl0)
GD32VW55x User Manual Control register 0 (EFUSE_CTL0) 3.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SWBOOT EFBOOT SWBOOT EFBOOT EFBOOT Reserved EFSB Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. SWBOOT0 Efuse BOOT0 bit enable 0: Select boot0_pad as BOOT0 output...
Page 70: Flash Protection Control Register (Efuse_Fpctl)
GD32VW55x User Manual This register has to be accessed by word (32-bit). Reserved Reserved VFCERT VFIMG Reserved ROTLK NDBG Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. VFCERT Verify firmware certificate 0: Disable firmware certificate verification 1: Enable firmware certificate verification VFIMG Verify firmware image...
Page 71: User Byte Control Register (Efuse_Userctl)
GD32VW55x User Manual FP[2:0] Efuse flash protection value Bit2: 0~32K write protection Bit1: Reserved Bit0: Read protection level 1 User byte control register (EFUSE_USERCTL) 3.4.6. Address offset: 0x14 Reset value: 0x0000 0006 This register has to be accessed by word (32-bit). Reserved Reserved UDLK...
Page 72: Efuse Reserved Register X (Efuse_Resx) (X = 0
GD32VW55x User Manual 1: External HXTAL EFUSE reserved register x (EFUSE_RESx) (x = 0…2) 3.4.7. Address offset: 0x18 + 0x4 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). RES[31:16] RES[15:0] Bits Fields Descriptions 31:0 RES[31:0] Efuse reserved bytes.
Page 73: Product Uid Register X (Efuse_Puidx) (X = 0
GD32VW55x User Manual RKEY[15:0] Bits Fields Descriptions 31:0 RKEY[31:0] Efuse RoTPK or its HASH value. Product UID register x (EFUSE_PUIDx) (x = 0…3) 3.4.10. Address offset: 0x54 + 0x4 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). UID[31:16] UID[15:0] Bits...
Page 74: Boot Address Register (Efuse_Bootaddr)
GD32VW55x User Manual USERDATA[31:16] USERDATA[15:0] Bits Fields Descriptions 31:0 USERDATA[31:0] Efuse USER_DATA value. Boot address register (EFUSE_BOOTADDR) 3.4.13. Address offset: 0x124 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). BOOTADDR[31:16] BOOTADDR[15:0] Bits Fields Descriptions 31:0 BOOTADDR[31:0] Boot from the address.
Page 75: Power Management Unit (Pmu)
GD32VW55x User Manual Power management unit (PMU) 4.1. Overview The power consumption is regarded as one of the most important issues for the devices of GD32VW55x series. According to the power management unit (PMU), provides six types of power saving modes, including Sleep, Deep-sleep, Standby, SRAM_sleep, Wi-Fi_sleep and BLE_sleep mode.
Page 76: Function Overview
GD32VW55x User Manual 4.3. Function overview provides details on the internal configuration of the PMU Figure 4-1. Power supply overview and the relevant power domains. Figure 4-1. Power supply overview Backup Domain VBAK LXTAL BPOR 3.3V WKUPR BKP PAD PC13 SRAM_OFF WKUPx PB15...
Page 77: Vdd / V Dda
GD32VW55x User Manual mode until V is completely powered up. Also the application software can trigger the Backup domain software reset by setting the BKPRST bit in the RCU_BDCTL register to reset the Backup domain. The clock source of the Real Time Clock (RTC) circuit can be derived from the Internal 32KHz RC oscillator (IRC32K) or the Low Speed Crystal oscillator (LXTAL), or HXTAL clock divided by 1-32.
Page 78: Figure 4-3. Waveform Of The Lvd Threshold
GD32VW55x User Manual Figure 4-2. Waveform of the POR / PDR hyst RSTTEMPO Power Reset (Active Low) domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the PMU_CTL0 register. The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in the PMU_CS0 register, indicates if V is higher or lower than the LVD threshold.
Page 79: 1.1V Power Domain
GD32VW55x User Manual Generally, digital circuits are powered by V , while most of analog circuits are powered by . To improve the ADC conversion accuracy, the independent power supply V implemented to achieve better performance of analog circuits. V can be externally connected to V through the external filtering circuit that avoids noise on V...
Page 80 GD32VW55x User Manual down the system clocks (HCLK, PCLK1 and PCLK2) or gating the clocks of the unused peripherals or configuring the LDO output voltage by LDOVS bits in PMU_CTL0 register. The LDOVS bits should be configured only when the PLL is off. Besides, six power saving modes are provided to achieve even lower power consumption, they are sleep mode, deep-sleep mode, standby, SRAM_sleep, BLE_sleep and Wi-Fi_sleep mode.
Page 81 GD32VW55x User Manual power mode depending on the LDOLP bit set in the PMU_CTL0 register enters by configure LDEN[1:0] to 0b11 and LDLP to 1 in the PMU_CTL0 register. No Low-driver: The Deep-sleep mode is not in low-driver mode by configure LDEN[1:0] to 00 in the PMU_CTL0 register.
Page 82: Figure 4-4. Rf Sequence
GD32VW55x User Manual Wi-Fi_sleep mode The Wi-Fi_sleep mode can enter by software (set WPEN bit to 1 and set WPSLEEP bit to 1), or by hardware (driven by Wi-Fi hardware signal sleep_wl when WPEN is 1). This mode can exit by clearing WPEN bit to 0, or by setting WPEN bit to 1 then setting WPSLEEP bit to 1, or by hardware (driven by Wi-Fi hardware signal wake_wl when WPEN is 1).
Page 83: Table 4-1. Time In Rf Sequence
GD32VW55x User Manual registers(recommend to configure in order of Figure 4-4. RF sequence. If related registers are not configured, the clocks will remain as before). t1 = t0 + T1 Table 4-1. Time in RF sequence Name Time Discription HXTAL mode: 1ms. External supply mode (HXTAL bypass mode): 1us.
Page 84: Table 4-2. Power Saving Mode Summary
GD32VW55x User Manual Table 4-2. Power saving mode summary Mode Sleep Deep-sleep Standby SRAM_sleep BLE_sleep Wi-Fi_sleep All clocks in The 1.1V the 1.1V domain is at least one of domain are off power off SRAM1 / Descriptio Only CPU BLE_OFF is Wi-Fi_OFF is Disable Disable...
Page 85: Register Definition
GD32VW55x User Manual 4.4. Register definition PMU base address: 0x4000 7000 Control register 0 (PMU_CTL0) 4.4.1. Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) This register can be accessed by half-word (16-bit) or word (32-bit). LDEN[1:0] Reserved Reserved...
Page 86: Control And Status Register 0 (Pmu_Cs0)
GD32VW55x User Manual 010: 2.4V 011: 2.6V 100: 2.7V 101: 2.9V 110: 3.0V 111: 3.1V LVDEN Low Voltage Detector Enable 0: Disable Low Voltage Detector 1: Enable Low Voltage Detector Note: When LVD_LOCK bit is set to 1 in the SYSCFG_CFG1 register, LVDEN and LVDT[2:0] are read only.
Page 87 GD32VW55x User Manual 31:20 Reserved Must be kept at reset value. 19:18 LDRF[1:0] Low-driver mode ready flag These bits are set by hardware when enter deep-sleep mode and the LDO in Low- driver mode. These bits are cleared by software when write 11. 00: normal driver in deep-sleep mode 01: Reserved 10: Reserved...
Page 88: Control Register 1 (Pmu_Ctl1)
GD32VW55x User Manual set this bit will trigger a wakup event when the input is aready high. Reserved Must be kept at reset value. LVDF Low Voltage Detector Status Flag 0: Low Voltage event has not occurred (V is higher than the specified LVD threshold) 1: Low Voltage event occurred (V is equal to or lower than the specified LVD...
Page 89 GD32VW55x User Manual BLE go to sleep when setting this bit by software. Clear by hardware. BLEPSLEEP Reserved Must be kept at reset value. BLE_SRAM_RET BLE SRAM enter retention mode when deepsleep and BLE_sleep. 0: Disable retention mode 1: Enable retention mode Setting this bit by software will wakeup SRAM0.
Page 90: Control And Status Register 1 (Pmu_Cs1)
GD32VW55x User Manual 1: Wi-Fi_OFF domain power off when Wi-Fi sleep, and power on when Wi-Fi wakeup.(when this bit is 1, Wi-Fi power on / off can be set by software or hardware) Reserved Must be kept at reset value. Control and status register 1 (PMU_CS1) 4.4.4.
Page 91: Parameter Register 0 (Pmu_Par0)
GD32VW55x User Manual 1: BLE can wakeup WPS_ACTIVE Wi-Fi is in active state. Read only. WPS_SLEEP Wi-Fi is in sleep state. Read only. Reserved Must be kept at reset value. Parameter register 0 (PMU_PAR0) 4.4.5. Address offset: 0x10 Reset value: 0x000A 2000 This register can be accessed by half-word (16-bit) or word (32-bit).
Page 92: Parameter Register 1 (Pmu_Par1)
GD32VW55x User Manual Reserved Must be kept at reset value. Parameter register 1 (PMU_PAR1) 4.4.6. Address offset: 0x14 Reset value: 0x0020 2020 This register can be accessed by half-word (16-bit) or word (32-bit). TWKSRA TWKSRA TWKSRA TWK_SRAM3[7:0] Reserved M3EN M2EN M1EN TWK_SRAM2[7:0] TWK_SRAM1[7:0]...
Page 93: Rf Control Register (Pmu_Rfctl)
GD32VW55x User Manual TWK_BLE[7:0] TWK_SRAM0[7:0] Bits Fields Descriptions TWKBLEEN User SW value when wakeup BLE or not 0: Use HW ack signal when wakeup BLE. 1: Use SW value when wakeup BLE, the value is set by TWK_BLE. TWKSRAM0EN User SW value when wakeup SRAM0 or not 0: Use HW ack signal when wakeup SRAM0.
Page 94: Rf Timer Parameter Register (Pmu_Rfpar)
GD32VW55x User Manual 0: enable RF by BLE hardware BLESWEN 1: enable RF by software, and RF is not affected by Bluetooth on or off MCU_PLLDOWN Software set or clear Software force close, close MCU PLL power. When wireless is in active state, set this bit shall not work.
Page 95: Pmu Interrupt Flag Register(Pmu_Intf)
GD32VW55x User Manual 15:12 Reserved Must be kept at reset value. 11:8 TIM2_PAR[3:0] 1 us step, default 1us, max: 16us Reserved Must be kept at reset value. TIM1_PAR[6:0] 0.1ms step, default 1ms. Max: 12.7ms。 XTAL bypass mode: 125ns step default 1.25us. PMU interrupt flag register(PMU_INTF) 4.4.10.
Page 96: Pmu Interrupt Clear Register(Pmu_Intc)
GD32VW55x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. BLE_PS_RISE_EN 0: Disable BLE_PS_RISE interrupt 1: Enable BLE_PS_RISE interrupt BLE_PS_FALL_EN 0: Disable BLE_PS_fall interrupt 1: Enable BLE_PS_fall interrupt PMU interrupt clear register(PMU_INTC) 4.4.12. Address offset: 0x34 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit).
Page 97: Reset And Clock Unit (Rcu)
GD32VW55x User Manual Reset and clock unit (RCU) 5.1. Reset control unit (RCTL) Overview 5.1.1. GD32VW55x reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system. The system reset resets the processor core and peripheral IP components except for the JTAG controller and the backup...
Page 98: Clock Control Unit (Cctl)
GD32VW55x User Manual Figure 5-1. The system reset circuit Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control register or V power on reset (V power on, if V have previously been powered off). 5.2.
Page 99: Figure 5-2. Clock Tree
GD32VW55x User Manual Figure 5-2. Clock tree BKP HCLK CK_BKP Prescaler Hclk÷ 4 HCLK AHB enable (to AHB bus,RISC- CK_FWDGT V,SRAM,DMA,peripherals) To FWDGT RTCSRC FCLK 32k Hz (free running clock) IRC32K APB1 CK_APB1 CK_RTC Prescaler PCLK1 32.768k Hz To RTC ÷...
Page 100: Characteristics
GD32VW55x User Manual control register (RCU_BDCTL). After the RTC select HXTAL clock divided by 1 to 32 (defined by RTCDIV bits in RCU_CFG0), the clock disappeared when the 1.1V core domain power off. After the RTC select IRC32K, the clock disappeared when V power off When the RTC select LXTAL, the clock disappeared when V...
Page 101: Figure 5-4. Hxtal Clock Source In Bypass Mode
GD32VW55x User Manual control register RCU_CTL. The HXTALSTB flag in control register RCU_CTL indicate s if the high-speed external crystal oscillator is stable. When the HXTAL is powered u p, it will not be released for use until this HXTALSTB bit is set by the hardware. Thi s specific delay period is known as the oscillator “Start-up time”.
Page 102 GD32VW55x User Manual Phase locked loop digital (PLLDIG) There is a internal phase locked loop digital, PLLDIG. The PLLDIG could be used to generator system clock (no more than 160 MHz) and division-clock which used to TRNG. The PLLDIG can be switched on or off by using the PLLDIGEN / PLLDIGPU bit in the RCU_CTL register.
Page 103: Table 5-1. Clock Output 0 Source Select
GD32VW55x User Manual HXTAL clock monitor (CKM) The HXTAL clock monitor function is enabled by the HXTAL clock monitor enable bit, RFCKMEN, in the control register (RCU_CTL). This function should be enabled after the HXTAL start-up delay and disabled when the HXTAL is stopped. Once the HXTAL failure is detected, the HXTAL will be automatically disabled.
Page 104: Table 5-3. 1.1V Domain Voltage Selected In Deep-Sleep Mode
GD32VW55x User Manual Voltage control The 1.1V domain voltage in Deep-sleep mode can be controlled by DSLPVS[1:0] bit in the Deep-sleep mode voltage register (RCU_DSV). 1.1V domain voltage selected in deep-sleep mode. Table 5-3. 1.1V domain voltage selected in deep-sleep mode DSLPVS[1:0] Deep-sleep mode voltage (V) The RCU_DSV register are protected by voltage key register (RCU_VKEY).
Page 105: Register Definition
GD32VW55x User Manual 5.3. Register definition RCU base address: 0x4002 3800 Control register (RCU_CTL) 5.3.1. Address offset: 0x00 Reset value: 0x0040 xx83 where x is undefined. This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit) HXTALR HXTALP PLLDIGS RFCKME...
Page 106 GD32VW55x User Manual clock Set and reset by software. Reset by hardware when entering Deep-sleep or standby mode. 0: PLLDIG disable. 1: PLLDIG enable. PLLDIGPU PLLDIG power up, this bit cannot be reset if the PLLDIG clock is used as the system clock Set and reset by software.
Page 107: Pll Register (Rcu_Pll)
GD32VW55x User Manual 1: Internal 16 MHz RC RF differential clock enable. IRC16MSTB IRC16M internal 16MHz RC oscillator stabilization flag Set by hardware to indicate if the IRC16M oscillator is stable and ready for use. 0: IRC16M oscillator is not stable. 1: IRC16M oscillator is stable.
Page 108 GD32VW55x User Manual CKOUT1SEL[1:0] CKOUT1DIV[2:0] CKOUT0DIV[2:0] CKOUT0SEL[2:0] RTCDIV[4:0] APB2PSC[2:0] APB1PSC[2:0] Reserved AHBPSC[3:0] SCSS[1:0] SCS[1:0] Bits Fields Descriptions 31:30 CKOUT1SEL[1:0] CKOUT1 clock source selection Set and reset by software. 00: Sysclk selected. 01: Internal 16M RC Oscillator clock selected. 10: High speed crystal oscillator clock (HXTAL) selected. 11: CK_PLLDIG clock selected.
Page 109 GD32VW55x User Manual 00001: CK_HXTAL / 2. 00010: CK_HXTAL / 3. 00011: CK_HXTAL / 4. … 11111: CK_HXTAL / 32. 15:13 APB2PSC[2:0] APB2 prescaler selection Set and reset by software to control the APB2 clock division ratio. 0xx: CK_AHB selected. 100: (CK_AHB / 2) selected.
Page 110: Clock Interrupt Register (Rcu_Int)
GD32VW55x User Manual standby mode or HXTAL failure is detected by HXTAL clock monitor when HXTAL is selected directly or indirectly as the clock source of CK_SYS. Does not take effect when 2’b11 is written. SCS will keep the previous value. 00: select CK_IRC16M as the CK_SYS source.
Page 111 GD32VW55x User Manual 1: Reset IRC16MSTBIF flag. LXTALSTBIC LXTAL stabilization interrupt clear Write 1 by software to reset the LXTALSTBIF flag. 0: Not reset LXTALSTBIF flag. 1: Reset LXTALSTBIF flag. IRC32KSTBIC IRC32K Stabilization interrupt clear Write 1 by software to reset the IRC32KSTBIF flag. 0: Not reset IRC32KSTBIF flag.
Page 112: Ahb1 Reset Register (Rcu_Ahb1Rst)
GD32VW55x User Manual Reset when setting the PLLDIGSTBIC bit by software. 0: No PLLDIG stabilization interrupt generated. 1: PLLDIG stabilization interrupt generated. Reserved Must be kept at reset value. HXTALSTBIF HXTAL stabilization interrupt flag Set by hardware when the High speed 8~ 52 MHz crystal oscillator clock is stable and the HXTALSTBIE bit is set.
Page 113: Ahb2 Reset Register (Rcu_Ahb2Rst)
GD32VW55x User Manual Bits Fields Descriptions BLERST BLE reset This bit is set and reset by software. 0: No reset. 1: Reset the BLE. 30:22 Reserved Must be kept at reset value. DMARST DMA reset This bit is set and reset by software. 0: No reset.
Page 114: Ahb3 Reset Register (Rcu_Ahb3Rst)
GD32VW55x User Manual This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit) Reserved TRNGRS PKCAUR Reserved HAURST CAURST Reserved Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. TRNGRST TRNG reset This bit is set and reset by software. 0: No reset.
Page 115: Apb1 Reset Register (Rcu_Apb1Rst)
GD32VW55x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. QSPIRST QSPI reset This bit is set and reset by software. 0: No reset. 1: Reset the QSPI. Reserved Must be kept at reset value. APB1 reset register (RCU_APB1RST) 5.3.8.
Page 116: Apb2 Reset Register (Rcu_Apb2Rst)
GD32VW55x User Manual 20:19 Reserved Must be kept at reset value USART0RST USART0 reset This bit is set and reset by software. 0: No reset. 1: Reset the USART0. UART1RST UART1 reset This bit is set and reset by software. 0: No reset.
Page 117 GD32VW55x User Manual This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit) TIMER16 TIMER15 RFRST Reserved Reserved SYSCFG UART2R TIMER0R Reserved Reserved SPIRST Reserved ADCRST Reserved Reserved Bits Fields Descriptions RFRST RF reset This bit is set and reset by software. 0: No reset.
Page 118: Ahb1 Enable Register (Rcu_Ahb1En)
GD32VW55x User Manual 1: Reset the ADC. Reserved Must be kept at reset value. UART2RST UART2 reset This bit is set and reset by software. 0: No reset. 1: Reset the UART2. Reserved Must be kept at reset value. TIMER0RST TIMER0 reset This bit is set and reset by software.
Page 119 GD32VW55x User Manual This bit is set and reset by software. 0: Disabled SRAM3 clock. 1: Enabled SRAM3 clock. SRAM2EN SRAM2 clock enable This bit is set and reset by software. 0: Disabled SRAM2 clock. 1: Enabled SRAM2 clock. SRAM1EN SRAM1 clock enable This bit is set and reset by software.
Page 120: Ahb2 Enable Register (Rcu_Ahb2En)
GD32VW55x User Manual This bit is set and reset by software. 0: Disabled GPIO port A clock. 1: Enabled GPIO port A clock. AHB2 enable register (RCU_AHB2EN) 5.3.11. Address offset: 0x34 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit) Reserved PKCAUE Reserved...
Page 121: Apb1 Enable Register (Rcu_Apb1En)
GD32VW55x User Manual Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit) Reserved Reserved QSPIEN Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. QSPIEN QSPI clock enable This bit is set and reset by software. 0: Disabled QSPI clock.
Page 122 GD32VW55x User Manual This bit is set and reset by software. 0: Disabled I2C1 clock. 1: Enabled I2C1 clock. I2C0EN I2C0 clock enable This bit is set and reset by software. 0: Disabled I2C0 clock. 1: Enabled I2C0 clock. 20:19 Reserved Must be kept at reset value.
Page 123: Apb2 Enable Register (Rcu_Apb2En)
GD32VW55x User Manual This bit is set and reset by software. 0: Disabled TIMER1 clock. 1: Enabled TIMER1 clock. APB2 enable register (RCU_APB2EN) 5.3.14. Address offset: 0x44 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit) TIMER16 TIMER15 RFEN...
Page 124: Ahb1 Sleep Mode Enable Register (Rcu_Ahb1Spen)
GD32VW55x User Manual This bit is set and reset by software. 0: Disabled SPI clock. 1: Enabled SPI clock. 11:9 Reserved Must be kept at reset value. ADCEN ADC clock enable This bit is set and reset by software. 0: Disabled ADC clock. 1: Enabled ADC clock.
Page 125: Backup Domain Control Register (Rcu_Bdctl)
GD32VW55x User Manual 14:0 Reserved Must be kept at reset value. Backup domain control register (RCU_BDCTL) 5.3.16. Address offset: 0x70 Reset value: 0x0000 0018, reset by Backup domain reset. This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit) Note: The LXTALEN, LXTALBPS, RTCSRC and RTCEN bits of the Backup domain control register (RCU_BDCTL) are only reset after a Backup domain Reset.
Page 126: Reset Source / Clock Register (Rcu_Rstsck)
GD32VW55x User Manual LXTALDRI[1:0] LXTAL drive capability Set and reset by software. Backup domain reset resets this value. 00: Lower driving capability. 01: High driving capability. 10: Higher driving capability. 11: Highest driving capability (reset value). Note: The LXTALDRI is not in bypass mode. LXTALBPS LXTAL bypass mode enable Set and reset by software.
Page 127 GD32VW55x User Manual 1: Low-power management reset generated. WWDGTRSTF Window watchdog timer reset flag Set by hardware when a window watchdog timer reset generated. Reset by writing 1 to the RSTFC bit. 0: No window watchdog reset generated. 1: Window watchdog reset generated. FWDGTRSTF Free watchdog timer reset flag Set by hardware when a free watchdog timer reset generated.
Page 128: Plldig Clock Configuration Register 0 (Rcu_Plldigcfg0)
GD32VW55x User Manual 1: Enable IRC32K. PLLDIG clock configuration register 0 (RCU_PLLDIGCFG0) 5.3.18. Address offset: 0x84 Reset value: 0x0B00 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit) PLLDIGDIV_SYS[5:0] PLLDIGOSEL[1:0] Reserved Reserved Bits Fields Descriptions 31:26 PLLDIGDIV_SYS[5:0] PLLDIG clock divider factor for system clock Set and reset by software to control the PLLDIG clock divider factor for system...
Page 129 GD32VW55x User Manual RFPLLLO RFPLLCA Reserved BGVBIT[2:0] IRC16MDIV[8:0] Bits Fields Descriptions 31:30 USART0SEL[1:0] USART0 Clock Source Selection Set and reset by software to control the USART0 clock source. 00: CK_APB1 selected as USART0 source clock. 01: CK_SYS selected as USART0 source clock. 10: CK_LXTAL selected as USART0 source clock.
Page 130: Additional Clock Control Register (Rcu_Addctl)
GD32VW55x User Manual 0: BandGap power down. 1: BandGap power on. LDOCLKPU LDO clock power on enable for RF / ADC / DAC 0: LDO clock power down. 1: LDO clock power on. LDOANAPU LDO analog power on enable for RF filter 0: LDO analog power down.
Page 131: Plldig Clock Configuration Register 1 (Rcu_Plldigcfg1)
GD32VW55x User Manual Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. TRNGCKDIV[4:0] PLLDIG clock divider factor for TRNG clock Set and reset by software to control the PLLDIG clock divider factor for TRNG clock. 00000: PLLDIG clock divided by 1 for TRNG clock. 00001: PLLDIG clock divided by 2 for TRNG clock.
Page 132: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32VW55x User Manual This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit) KEY[31:16] KEY[15:0] Bits Fields Descriptions 31:0 KEY[31:0] The key of RCU_DSV register These bits are written only by software and read as 0. Only after write 0x1A2B3C4D to the RCU_VKEY, the RCU_DSV register can be written.
Page 133: Interrupt / Event Controller (Exti)
GD32VW55x User Manual Interrupt / event controller (EXTI) 6.1. Overview RISC-V integrates the Enhancement Core-Local Interrupt Controller (ECLIC) for efficient interrupts processing. ECLIC is designed to provide low-latency, vectored, pre-emptive interrupts for RISC-V systems. When activated, the ECLIC subsumes and replaces the existing RISC-V local interrupt scheme (CLINT).
Page 134: Table 6-1. Interrupt Vector Table
GD32VW55x User Manual Table 6-1. Interrupt vector table Vector Interrupt description Vector address number CLIC_INT_SFT 0x0000_000C CLIC_INT_TMR 0x0000_001C WWDGT interrupt 0x0000_004C LVD from EXTI interrupt 0x0000_0050 RTC tamper and timestamp from EXTI interrupt 0x0000_0054 RTC wakeup from EXTI interrupt 0x0000_0058 FMC global interrupt 0x0000_005C RCU global interrupt...
Page 135 GD32VW55x User Manual Vector Interrupt description Vector address number UART1 global interrupt 0x0000_00E4 UART2 global interrupt 0x0000_00E8 EXTI line[10:15] interrupts 0x0000_00EC RTC alarm from EXTI interrupt 0x0000_00F0 0x0000_00F4 - Reserved 61~62 0x0000_00F8 TIMER15 global interrupt 0x0000_00FC TIMER16 global interrupt 0x0000_0100 0x0000_0104 - 65~69 Reserved...
Page 136: External Interrupt And Event Block Diagram
GD32VW55x User Manual Vector Interrupt description Vector address number Half slot interrupt 0x0000_01B4 FIFO activity interrupt 0x0000_01B8 Error interrupt 0x0000_01BC Frequency selection interrupt 0x0000_01C0 EFUSE global interrupt 0x0000_01C4 QSPI global interrupt 0x0000_01C8 PKCAU global interrupt 0x0000_01CC 6.4. External interrupt and event block diagram Figure 6-1.
Page 137: Table 6-2. Exti Source
GD32VW55x User Manual EXTI can provide not only interrupts but also event signals to the processor. The RISC-V processor fully implements the Wait For Interrupt (WFI) instruction. EXTI can be used to wake up processor and the whole system when some expected event occurs, such as a special GPIO pin toggling or RTC alarm.
Page 138 GD32VW55x User Manual EXTI line Source number PA14 / PC14 PA15 / PB15 / PC15 RTC alarm Reserved WIFI wakeup RTC tamper and timestamp RTC wakeup I2C0 wakeup USART0 wakeup BLE wakeup PLF wakeup...
Page 139: Register Definition
GD32VW55x User Manual 6.6. Register definition EXTI base address: 0x4001 3C00 Interrupt enable register (EXTI_INTEN) 6.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved INTEN25 INTEN24 INTEN23 INTEN22 INTEN21 INTEN20 INTEN19 Reserved INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8...
Page 140: Rising Edge Trigger Enable Register (Exti_Rten)
GD32VW55x User Manual 25:19 EVENx Event enable bit x (x = 19…25) 0: Event from linex is disabled 1: Event from linex is enabled Reserved Must be kept at reset value. 17:0 EVENx Event enable bit x (x = 0…17) 0: Event from linex is disabled 1: Event from linex is enabled Rising edge trigger enable register (EXTI_RTEN)
Page 141: Software Interrupt Event Register (Exti_Swiev)
GD32VW55x User Manual FTEN15 FTEN14 FTEN13 FTEN12 FTEN11 FTEN10 FTEN9 FTEN8 FTEN7 FTEN6 FTEN5 FTEN4 FTEN3 FTEN2 FTEN1 FTEN0 Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:19 FTENx Falling edge trigger enable (x = 19...25) 0: Falling edge of linex is invalid 1: Falling edge of linex is valid as an interrupt / event request Reserved Must be kept at reset value.
Page 142: Pending Register (Exti_Pd)
GD32VW55x User Manual Pending register (EXTI_PD) 6.6.6. Address offset: 0x14 Reset value: undefined This register has to be accessed by word (32-bit). Reserved PD25 PD24 PD23 PD22 PD21 PD20 PD19 Reserved PD17 PD16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 PD15...
Page 143: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32VW55x User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) 7.1. Overview There are up to 29 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB4, PB11 ~ PB13, PB15, PC8 and PC13 ~ PC15 for the device to implement logic input / output functions.
Page 144: Figure 7-1. Basic Structure Of A General-Pupose I/O
GD32VW55x User Manual as floating (no pull-up and pull-down), pull-up or pull-down function by GPIO pull-up / pull- down registers (GPIOx_PUD). Table 7-1. GPIO configuration table PAD TYPE CTLy PUDy Floating GPIO Pull-up INPUT Pull-down Floating push-pull Pull-up Pull-down GPIO OUTPUT Floating open-drain...
Page 145: Gpio Pin Configuration
GD32VW55x User Manual GPIO pin configuration 7.3.1. During or just after the reset period, the alternative functions are all inactive and the GPIO ports are configured into the input floating mode that input disabled without Pull-Up(PU) / Pull- Down(PD) resistors. But the JTAG pins are in input PU / PD mode after reset: PA15: JTDI in PU mode PA14: JTCK in PD mode PA13: JTMS in PU mode...
Page 146: Input Configuration
GD32VW55x User Manual Input configuration 7.3.5. When GPIO pin is configured as Input:  The schmitt trigger input is enabled.  The weak pull-up and pull-down resistors could be chosen.  Every AHB clock cycle the data present on the I/O pin is got to the port input status register.
Page 147: Analog Configuration
GD32VW55x User Manual Figure 7-3. Basic structure of Output configuration Write Bit Operate Registers Output Control Read / Write Register Output driver Alternate Function Output protect I / O pin Input Read Status Input driver Register Analog configuration 7.3.7. When GPIO pin is used as analog configuration: ...
Page 148: Gpio Locking Function
GD32VW55x User Manual  A read access to the port output control register gets the last written value. Figure 7-5. Basic structure of Alternate function configuration shows the alternate function configuration. Figure 7-5. Basic structure of Alternate function configuration Output driver Alternate Function Output protect I / O pin...
Page 149: Register Definition
GD32VW55x User Manual 7.4. Register definition GPIOA base address: 0x4002 0000 GPIOB base address: 0x4002 0400 GPIOC base address: 0x4002 0800 Port control register (GPIOx_CTL, x = A…C) 7.4.1. Address offset: 0x00 Reset value: GPIOA_CTL 0xA800 0000 GPIOB_CTL 0x0000 0280 GPIOC_CTL 0x0000 0000 This register can be written by byte (8-bit), half word (16-bit) or word (32-bit).
Page 150: Port Output Mode Register (Gpiox_Omode, X = A
GD32VW55x User Manual refer to CTL0[1:0]description 19:18 CTL9[1:0] Pin 9 configuration bits These bits are set and cleared by software. refer to CTL0[1:0]description 17:16 CTL8[1:0] Pin 8 configuration bits These bits are set and cleared by software. refer to CTL0[1:0]description 15:14 CTL7[1:0] Pin 7 configuration bits...
Page 151 GD32VW55x User Manual Reset value: 0x0000 0000 This register can be written by byte (8-bit), half word (16-bit) or word (32-bit). This register can only be read by word (32-bit). Reserved OM15 OM14 OM13 OM12 OM11 OM10 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 152: Port Output Speed Register (Gpiox_Ospd, X = A
GD32VW55x User Manual refer to OM0 description Pin 6 output mode bit These bits are set and cleared by software. refer to OM0 description Pin 5 output mode bit These bits are set and cleared by software. refer to OM0 description Pin 4 output mode bit These bits are set and cleared by software.
Page 153 GD32VW55x User Manual Bits Fields Descriptions 31:30 OSPD15[1:0] Pin 15 output max speed bits These bits are set and cleared by software. refer to OSPD0[1:0]description 29:28 OSPD14[1:0] Pin 14 output max speed bits These bits are set and cleared by software. refer to OSPD0[1:0]description 27:26 OSPD13[1:0]...
Page 154: Port Pull-Up/Pull-Down Register (Gpiox_Pud, X = A
GD32VW55x User Manual These bits are set and cleared by software. refer to OSPD0[1:0]description OSPD2[1:0] Pin 2 output max speed bits These bits are set and cleared by software. refer to OSPD0[1:0]description OSPD1[1:0] Pin 1 output max speed bits These bits are set and cleared by software. refer to OSPD0[1:0]description OSPD0[1:0] Pin 0 output max speed bits...
Page 155 GD32VW55x User Manual refer to PUD0[1:0]description 25:24 PUD12[1:0] Pin 12 pull-up or pull-down bits These bits are set and cleared by software. refer to PUD0[1:0]description 23:22 PUD11[1:0] Pin 11 pull-up or pull-down bits These bits are set and cleared by software. refer to PUD0[1:0]description 21:20 PUD10[1:0]...
Page 156: Port Input Status Register (Gpiox_Istat, X = A
GD32VW55x User Manual PUD0[1:0] Pin 0 pull-up or pull-down bits These bits are set and cleared by software. 00: Floating mode, no pull-up and pull-down (reset value) 01: With pull-up mode 10: With pull-down mode 11: Reserved Port input status register (GPIOx_ISTAT, x = A...C) 7.4.5.
Page 157: Port Bit Operate Register (Gpiox_Bop, X = A
GD32VW55x User Manual 31:16 Reserved Must be kept at reset value. 15:0 OCTLy Pin output control (y = 0…15) These bits are set and cleared by software. 0: Pin output low 1: Pin output high Port bit operate register (GPIOx_BOP, x = A…C) 7.4.7.
Page 158: Alternate Function Selected Register 0 (Gpiox_Afsel0, X = A
GD32VW55x User Manual Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. Lock sequence key It can only be setted using the Lock Key Writing Sequence. And can always be read. 0: GPIO_LOCK register is not locked and the port configuration is not locked. 1: GPIO_LOCK register is locked until an MCU reset.
Page 159: Alternate Function Selected Register 1 (Gpiox_Afsel1, X = A
GD32VW55x User Manual These bits are set and cleared by software. refer to SEL0[3:0]description 15:12 SEL3[3:0] Pin 3 alternate function selected These bits are set and cleared by software. refer to SEL0[3:0]description 11:8 SEL2[3:0] Pin 2 alternate function selected These bits are set and cleared by software. refer to SEL0[3:0]description SEL1[3:0] Pin 1 alternate function selected...
Page 160: Bit Clear Register (Gpiox_Bc, X = A
GD32VW55x User Manual refer to SEL8[3:0] description 23:20 SEL13[3:0] Pin 13 alternate function selected These bits are set and cleared by software. refer to SEL8[3:0] description 19:16 SEL12[3:0] Pin 12 alternate function selected These bits are set and cleared by software. refer to SEL8[3:0] description 15:12 SEL11[3:0]...
Page 161: Port Bit Toggle Register (Gpiox_Tg, X = A
GD32VW55x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 Pin Clear bit y (y = 0…15) These bits are set and cleared by software 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit Port bit toggle register (GPIOx_TG, x = A…C) 7.4.12.
Page 162: Cyclic Redundancy Checks Management Unit (Crc)
GD32VW55x User Manual Cyclic redundancy checks management unit (CRC) Overview 8.1. A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 32-bit CRC code with fixed polynomial. Characteristics 8.2.
Page 163: Function Overview
GD32VW55x User Manual Function overview 8.3.  CRC calculation unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If the CRC_DATA register has not been cleared by software setting the CRC_CTL register, the new input raw data will be calculated based on the result of previous value of CRC_DATA.
Page 164: Register Definition
GD32VW55x User Manual Register definition 8.4. CRC access base address: 0x4002 3000 Data register (CRC_DATA) 8.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA [31:0] CRC calculation result bits Software writes and reads.
Page 165: Control Register (Crc_Ctl)
GD32VW55x User Manual by any other peripheral. The CRC_CTL register will take no effect to the byte. Control register (CRC_CTL) 8.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved Bits Fields Descriptions 31:1...
Page 166: True Random Number Generator (Trng)
GD32VW55x User Manual True random number generator (TRNG) 9.1. Overview The true random number generator (TRNG) module can generate a 32-bit random value by using continuous analog noise. 9.2. Characteristics  About 40 periods of TRNG_CLK are needed between two consecutive random numbers. ...
Page 167: Operation Flow
GD32VW55x User Manual The analog seed is generated by several ring oscillators. The LFSR is driven by a configurable TRNG_CLK (refer to chapter), so that the quality of the Reset and clock unit (RCU) generated random number depends on TRNG_CLK exclusively, no matter what HCLK frequency was set or not.
Page 168: Register Definition
GD32VW55x User Manual 9.4. Register definition TRNG base address: 0x4C06 0800 Control register (TRNG_CTL) 9.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved TRNGEN Reserved Bits Fields Descriptions Must be kept at reset value. 31:4 Reserved Interrupt enabled bit.
Page 169: Data Register (Trng_Data)
GD32VW55x User Manual Must be kept at reset value. 31:7 Reserved SEIF Seed error interrupt flag This bit will be set if more than 64 consecutive same bit or more than 32 consecutive 01(or 10) changing are detected. 0: No fault detected 1: Seed error has been detected.
Page 170 GD32VW55x User Manual Bits Fields Descriptions 31:0 TRNDATA[31:0] 32-bit random data...
Page 171: Direct Memory Access Controller (Dma)
GD32VW55x User Manual Direct memory access controller (DMA) 10.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the MCU, thereby increasing system performance by off-loading the MCU from copying large amounts of data and avoiding frequent interrupts to serve peripherals needing more data or having available data.
Page 172: Block Diagram
GD32VW55x User Manual – DMA: Programmable length of data to be transferred, max to 65535. – Peripheral: The last request signal given to DMA from peripheral determines the end of transfer.  Support two data processing modes by use of the four-word depth 32-bit width FIFOs: –...
Page 173: Figure 10-2. Data Stream For Three Transfer Modes
GD32VW55x User Manual supports multiple data sizes, burst types, address generation algorithm, priority levels and several transfer modes to allow for flexible application by configuring the corresponding bits in DMA registers. All the DMA registers can be 32-bit configured through AHB slave interface. Three transfer modes are supported, including peripheral-to-memory, memory-to-peripheral and memory-to-memory, which is determined by the TM bits in the DMA_CHxCTL register, as listed in...
Page 174: Peripheral Handshake
GD32VW55x User Manual  Memory to peripheral: read data from memory through AHB master interface for memory, and write data to peripheral through AHB master interface for peripheral. Peripheral to memory: read data from peripheral through AHB master interface for ...
Page 175: Data Process
GD32VW55x User Manual Table 10-2. Peripheral requests to DMA Channel Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 TIMER0_CH0 ● ● TIMER1_TG TIMER2_TG TIMER2_CH1 TIMER0_CH1 TIMER0_CH2 ● ● I2C0_RX TIMER2_UP TIMER2_CH2 I2C0_RX I2C0_TX I2C0_TX ●...
Page 176: Table 10-3. Cnt Configuration
GD32VW55x User Manual incrementing burst for peripheral port and memory port. In single-data mode, only single burst type is supported and PBURST and MBURST are automatically locked as ‘00’ by hardware immediately after enable the DMA channel. In peripheral-to-memory or memory-to-peripheral mode, if PBURST is different from ‘00’, DMA responses a increasing burst transfer of 4, 8, 16-beat based on the PBURST bits for each peripheral request.
Page 177 GD32VW55x User Manual 8-bit 32-bit Multiple of 4 16-bit 32-bit Multiple of 2 Others Any value If the circular mode is enabled by setting the CMEN bit in the DMA_CHxCTL register. The number of data bytes must be an integer multiple of the byte number of a peripheral burst transfer and a memory burst transfer to gurantee an integrated memory and peripheral burst transfer: ⁄...
Page 178: Table 10-4. Fifo Counter Critical Value Configuration Rules
GD32VW55x User Manual Multi-data mode The multi-data mode is selected by configuring the MDMEN bit in the DMA_CHxFCTL register to ‘1’. In this mode, the DMA responds the source request when there is enough FIFO space for a source transfer, pushing the data reading from the source address into the FIFO. If the destination is a peripheral, the DMA responds the peripheral request when there is enough FIFO data for a peripheral burst transfer.
Page 179: Figure 10-4. Data Packing/Unpacking When Pwidth = '00
GD32VW55x User Manual Single-data mode The single-data mode is selected by configuring the MDMEN bit in the DMA_CHxFCTL register to ‘0’. In this mode, only single transfer is supported to implement the DMA data access, and the FIFO counter critical value configured in the FCCV bits of the DMA_CHxFCTL register has no meaning.
Page 180: Address Generation
GD32VW55x User Manual Figure 10-5. Data packing / unpacking when PWIDTH = ‘01’  PAIF = 0, MWIDTH = 8-bit read 0xB1B0[15:0] @0x0 write 0xB0[7:0] @0x0 write 0xB8[7:0] @0x8 word 4 read 0xB3B2[15:0] @0x2 write 0xB1[7:0] @0x1 write 0xB9[7:0] @0x9 read 0xB5B4[15:0] @0x4 write 0xB2[7:0] @0x2 write 0xB10[7:0] @0xA word 3...
Page 181: Circular Mode
GD32VW55x User Manual In the increasing mode, the next address is euqal to the current address plus 1 or 2 or 4, depending on the transfer data width. In multi-data mode with PBURST in the DMA_CHxCTL register different from ‘00’, if PAIF in the DMA_CHxCTL register is enabled, the next peripheral address increment is fixed to 4, and has nothing to do with the peripheral transfer data width.
Page 182: Transfer Flow Controller
GD32VW55x User Manual Figure 10-7. DMA operation of switch-buffer mode MBS = 0 transfer mode : peripheral-to-memory Enable the channel FIFO memory buffer 0 Peripheral push data pop data Memory 0 transfer: transfer finish transfer finish MBS = 0 MBS = 1 FIFO memory buffer 1 Peripheral...
Page 183: Transfer Finish
GD32VW55x User Manual  Memory-to-peripheral mode: In single-data mode, when the channel is enabled, DMA starts a single memory transfer and pushes the reading data into the FIFO immediately. During the transmission, the memory transfer is initiated only when the FIFO is empty. In multi-data mode, when the channel is enabled, DMA starts several single or burst transfers to fill up the FIFO whether the peripheral request is asserted or not.
Page 184 GD32VW55x User Manual  Memory-to-peripheral mode: If DMA is the transfer flow controller, when the CNT bits in the DMA_CHxCNT register reach zero, an end of transfer is achieved. If peripheral is the transfer flow controller, the DMA transfer is completed when the last peripheral request has been responded.
Page 185: Channel Configuration
GD32VW55x User Manual DMA. When this error occurs, the DMA operation is the same as it after the CHEN bit software cleared. For more information about the register access error, refer to section Error. Channel configuration 10.4.9. When starting a new DMA transfer, it is recommended to respect the following steps: Read the CHEN bit and judge whether the channel is enabled or not.
Page 186: Interrupts
GD32VW55x User Manual Configure the DMA_CHxM0ADDR or the DMA_CHxM1ADDR register to update the memory address pointer. Configure the DMA_CHxCNT with the number of the remaining data items. Configure the CHEN bit with ‘1’ in the DMA_CHxCTL register to restart the channel. 10.5.
Page 187: Exception
GD32VW55x User Manual  The CNT bits reach zero when DMA is the transfer flow controller.  When peripheral is the transfer flow controller, the last request is responded completely and the contents of the FIFO are entirely written into the memory in peripheral-to-memory mode.
Page 188: Error
GD32VW55x User Manual In memory-to-peripheral mode, when a peripheral request is valid and there is not enough data in the FIFO for the single or burst peripheral, a FIFO underrun condition is detected. This peripheral request is not responded until the data number in the FIFO is enough, and the accuracy of the data transmission will not be destroyed.
Page 189: Figure 10-8. System Connection Of Dma
GD32VW55x User Manual Figure 10-8. System connection of DMA Bus Matrix SRAM0 AHB1 QSPI AHB2 Memory port SRAM1 Peripheral port SRAM2 SRAM3 Peripheral APB1 request APB2...
Page 190: Register Definition
GD32VW55x User Manual 10.6. Register definition DMA base address: 0x4002 6000 Interrupt flag register 0 (DMA_INTF0) 10.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved FTFIF3 HTFIF3 TAEIF3 SDEIF3 Reserved FEEIF3 FTFIF2 HTFIF2 TAEIF2...
Page 191: Interrupt Flag Register 1 (Dma_Intf1)
GD32VW55x User Manual Interrupt flag register 1 (DMA_INTF1) 10.6.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved FTFIF7 HTFIF7 TAEIF7 SDEIF7 Reserved FEEIF7 FTFIF6 HTFIF6 TAEIF6 SDEIF6 Reserved FEEIF6 Reserved FTFIF5 HTFIF5 TAEIF5 SDEIF5...
Page 192: Interrupt Flag Clear Register 1 (Dma_Intc1)
GD32VW55x User Manual This register has to be accessed by word (32-bit). Reserved FTFIFC3 HTFIFC3 TAEIFC3 SDEIFC3 Reserved FEEIFC3 FTFIFC2 HTFIFC2 TAEIFC2 SDEIFC2 Reserved FEEIFC2 Reserved FTFIFC1 HTFIFC1 TAEIFC1 SDEIFC1 Reserved FEEIFC1 FTFIFC0 HTFIFC0 TAEIFC0 SDEIFC0 Reserved FEEIFC0 Bits Fields Descriptions 31:28 Reserved...
Page 193: Channel X Control Register (Dma_Chxctl) (X = 0
GD32VW55x User Manual 31:28 Reserved Must be kept at reset value. 27/21/11/5 FTFIFCx Clear bit for full transfer finish flag of channel x (x=4…7) 0: No effect 1: Clear full transfer finish flag 26/20/10/4 HTFIFCx Clear bit for half transfer finish flag of channel x (x=4…7) 0: No effect 1: Clear half transfer finish flag 25/19/9/3...
Page 194 GD32VW55x User Manual 101: Enable peripheral 5 110: Enable peripheral 6 111: Enable peripheral 7 These bits can NOT be written when CHEN is ‘1’. 24:23 MBURST[1:0] Transfer burst type of memory Software set and cleare. 00: single burst 01: INCR4 (4-beat incrementing burst) 10: INCR8 (8-beat incrementing burst) 11: INCR16 (16-beat incrementing burst) These bits can NOT be written when CHEN is ‘1’.
Page 195 GD32VW55x User Manual These bits can NOT be written when CHEN is ‘1’. PAIF Peripheral address increment fixed Software set and clear. 0: The peripheral address increment is determined by PWIDTH 1: The peripheral address increment is fixed to 4 This bit can NOT be written when CHEN is ‘1’.
Page 196 GD32VW55x User Manual This bit is automatically locked as ‘0’ by hardware immediately after enable CHEN if TFCS is configured to ‘1’. This bit is automatically locked as ‘1’ by hardware immediately after enable CHEN if SBMEN is configured to ‘1’. TM[1:0] Transfer mode Software set and clear.
Page 197: Channel X Counter Register (Dma_Chxcnt) (X = 0
GD32VW55x User Manual After a software clear operation, this bit is still read as 1 to indicate that there are memory or peripheral transfers still active until hardware has terminated all activity, at which point this bit is read as 0. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer.
Page 198: Channel X Memory 0 Base Address Register (Dma_Chxm0Addr) (X = 0
GD32VW55x User Manual These bits can NOT be written when CHEN in the DMA_CHxCTL register is ‘1’. When PWIDTH is 01 (16-bit), the LSB of these bits is ignored. Access is automatically aligned to a half word address. When PWIDTH is 10 (32-bit), the two LSBs of these bits are ignored. Access is automatically aligned to a word address.
Page 199: Channel X Fifo Control Register (Dma_Chxfctl) (X = 0
GD32VW55x User Manual M1ADDR[15:0] Bits Fields Descriptions 31:0 M1ADDR[31:0] Memory 1 base address When MBS in the DMA_CHxCTL register is read as to ‘1’, these bits specific the memory base address accessed by DMA during the transmission. These bits can NOT be written when CHEN in the DMA_CHxCTL register is ‘1’ and MBS in the DMA_CHxCTL register is read as ‘1’.
Page 200 GD32VW55x User Manual 100: FIFO Empty 101: FIFO Full 110~111: Reserved These bits specific the number of data stored in FIFO during the transmission. When MDMEN is configured to ‘0’, these bits has no meaning. MDMEN Multi-data mode enable Software set and clear. 0: Disable Multi-data mode 1: Enable Multi-data mode These bits can NOT be written when CHEN in the DMA_CHxCTL register is ‘1’.
Page 201: Debug (Dbg)
GD32VW55x User Manual Debug (DBG) 11.1. Overview The GD32VW55x series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the RISC-V module together with a daisy chained standard TAP controller. Debug functions are integrated into the RISC-V. The debug system supports standard JTAG debug.
Page 202: Debug Reset
GD32VW55x User Manual IR is 5-bit width, and the RISC-V JTAG IR is also 5-bit width. The BSD JTAG IDCODE is 0x790007A3. Debug reset 11.2.3. The System reset initializes the majority of the RISC-V. The NJTRST reset can reset JTAG TAP controller only.
Page 203: Register Definition
GD32VW55x User Manual 11.4. Register definition DEBUG base address: 0xE0044000 ID code register (DBG_ID) 11.4.1. Address offset: 0x00 Read only This register has to be accessed by word(32-bit) ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by software, These bits are unchanged constant Control register 0 (DBG_CTL0) 11.4.2.
Page 204: Control Register 1 (Dbg_Ctl1)
GD32VW55x User Manual DSLP_HOLD Deep-sleep mode hold bit This bit is set and reset by software 0: No effect 1: At the Deep-sleep mode, the clock of AHB bus and system clock are provided by CK_IRC16M SLP_HOLD Sleep mode hold bit This bit is set and reset by software 0: No effect 1: At the sleep mode, the clock of AHB is on.
Page 205: Control Register 2 (Dbg_Ctl2)
GD32VW55x User Manual WWDGT_HOLD WWDGT hold bit This bit is set and reset by software. 0: No effect 1: Hold the WWDGT counter clock for debugging when the core is halted. RTC_HOLD RTC hold bit This bit is set and reset by software. 0: No effect 1: Hold the RTC counter for debugging when the core is halted.
Page 206 GD32VW55x User Manual TIMER16_HOLD TIMER16 hold bit This bit is set and reset by software. 0: No effect 1: Hold the TIMER16 counter for debugging when the core is halted. TIMER15_HOLD TIMER15 hold bit This bit is set and reset by software. 0: No effect 1: Hold the TIMER15 counter for debugging when the core is halted.
Page 207: Analog To Digital Converter (Adc)
GD32VW55x User Manual Analog to digital converter (ADC) 12.1. Overview A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 9 external channels and 2 internal channels. The 11 ADC sampling channels all support a variety of operation modes. After sampling and conversion, the conversion results can be stored in the corresponding data registers according to the least significant bit(LSB) alignment or the most significant(MSB) bit alignment.
Page 208: Pins And Internal Signals
GD32VW55x User Manual Oversampling ratio adjustable from 2x to 256x. Programmable data shift up to 8-bits. ADC supply requirements: 1.62V to 3.6V, and typical power supply voltage is 3.3V.  ADC input range: 0 ≤ V ≤  12.3. Pins and internal signals Figure 12-1.
Page 209: Function Overview
GD32VW55x User Manual 12.4. Function overview Figure 12-1. ADC module block diagram Trig select DMA request Routine channels Interrupt Interrupt RVOF Channel Management generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO Routine data registers Over ADC_IN8 （16 bits） sampler SENSE REFINT TOVS OVSS[3:0]...
Page 210: Operation Modes
GD32VW55x User Manual channel is called routine channel. The RL[3:0] bits in the ADC_RSQ0 register specify the total conversion sequence length. The ADC_RSQ0~ADC_RSQ2 registers specify the selected channels of the routine sequence. Operation modes 12.4.4. Single operation mode In the single operation mode, the ADC performs conversion on the channel specified in the RSQ0[4:0] bits in ADC_RSQ2.
Page 211: Figure 12-3. Continuous Conversion Mode
GD32VW55x User Manual Figure 12-3. Continuous conversion mode Sample Routine trigger Convert Software procedure for continuous operation mode on a routine channel: Set the CTN bit in the ADC_CTL1 register; Configure RSQ0 with the analog channel number; Configure ADC_SAMPTx register; Configure ETMRC and ETSRC bits in the ADC_CTL1 register if it is needed;...
Page 212: Figure 12-4. Scan Operation Mode, Continuous Disable
GD32VW55x User Manual Figure 12-4. Scan operation mode, continuous disable · · · CH11 Routine trigger One circle of routine sequence, RL=8 Software procedure for scan operation mode on a routine sequence: Set the SM bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register; Configure ADC_RSQx and ADC_SAMPTx registers;...
Page 213: Conversion Result Threshold Monitor Function
GD32VW55x User Manual Configure DISNUM [2:0] bits in the ADC_CTL0 register; Configure ADC_RSQx and ADC_SAMPTx registers; Configure the ETMRC and ETSRC bits in the ADC_CTL1 register if it is needed; Prepare the DMA module to transfer data from the ADC_RDATA; Set the SWRCST bit, or generate an external trigger for theroutine sequence;...
Page 214: Sampling Time Configuration
GD32VW55x User Manual Sampling time configuration 12.4.7. The number of CK_ADC cycles which is used to sample the input voltage can be specified by the SPTn[2:0] bits in the ADC_SAMPT0 and ADC_SAMPT1 registers. And each channel can specify different sampling times. For 12-bit resolution, the total sampling and conversion time is “sampling time + 12”...
Page 215: Dma Request
GD32VW55x User Manual DMA request 12.4.9. The DMA request is used to transfer data for conversion of more than one channel. The DMA request of routine sequence is enabled by the DMA bit of ADC_CTL1 register. When this bit is set, the ADC generates a DMA request at the end of conversion of aroutine sequence. When this request is received, the DMA will transfer the converted data from the ADC_RDATA register to the destination location which is specified by the user.
Page 216: Programmable Resolution (Dres) - Fast Conversion Mode
GD32VW55x User Manual ADC and comparators. V is internally connected to the ADC_IN10 input channel. REFINT To use the temperature sensor: Configure the conversion sequence (ADC_IN9) and the sampling time (17.1μs) for the channel. Enable the temperature sensor by setting the TSVREN bit in ADC_CCTL. Start the ADC conversion by setting the ADCON bit or by the triggers.
Page 217: Figure 12-9. 20-Bit To 16-Bit Result Truncation
GD32VW55x User Manual ADC_OVSAMPCTL register. It can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits. It is configured through the OVSS[3:0] bits in the ADC_OVSAMPCTL register. Summation units can produce up to 20 bits (256 x 12-bit), which is first shifted right. The upper bits of the result are then truncated, keeping only the 16 least significant bits rounded to the nearest value using the least significant bits left apart by the shifting, before being finally transferred into the data register.
Page 218: Adc Interrupts
GD32VW55x User Manual indicates truncation) 1-bit 2-bit 3-bit 4-bit 5-bit 6-bit 7-bit 8-bit Oversa No-shift shift shift shift shift shift shift shift shift mpling OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= ratio data 0000 0001 0010 0011 0100 0101 0110 0111...
Page 219: Register Definition
GD32VW55x User Manual 12.5. Register definition ADC base address: 0x4001 2000 Status register (ADC_STAT) 12.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ROVF Reserved STRC Reserved rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions...
Page 220: Control Register 0 (Adc_Ctl0)
GD32VW55x User Manual ADC_WDLT and ADC_WDHT registers. Cleared by software writing 0 to it. Control register 0 (ADC_CTL0) 12.5.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). ROVFIE Reserved DRES RWDEN Reserved DISNUM [2:0] Reserved DISRC Reserved...
Page 221: Control Register 1 (Adc_Ctl1)
GD32VW55x User Manual 0: Scan operation mode disable 1: Scan operation mode enable Must be kept at reset value. Reserved WDEIE Interrupt enable for WDE 0: Interrupt disable 1: Interrupt enable EOCIE Interrupt enable for EOC 0: EOC interrupt disable 1: EOC interrupt enable WDCHSEL[4:0] Analog watchdog channel select...
Page 222 GD32VW55x User Manual Setting 1 on this bit starts a conversion of a routine sequence. It is set by software and cleared by software or by hardware after the conversion starts. External trigger mode for routine channel 29:28 ETMRC[1:0] 00: External trigger for routine channel disable 01: Rising edge of external trigger for routine channel enable 01: Falling edge of external trigger for routine channel enable 11: Rising and falling edge of external trigger for routine channel enable...
Page 223: Sample Time Register 0 (Adc_Sampt0)
GD32VW55x User Manual 0: DMA request disable 1: DMA request enable Reserved Must be kept at reset value. Continuous mode 0: Continuous operation mode disable 1: Continuous operation mode enable ADCON ADC ON. The ADC will be waked up when this bit is changed from low to high and take a stabilization time.
Page 224: Sample Time Register 1 (Adc_Sampt1)
GD32VW55x User Manual Sample time register 1 (ADC_SAMPT1) 12.5.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). SPT7[3:0] SPT6[3:0] SPT5[3:0] SPT4[3:0] SPT3[3:0] SPT2[3:0] SPT1[3:0] SPT0[3:0] Bits Fields Descriptions 31:28 SPT7[3:0] Refer to SPT0[3:0] description 27:24 SPT6[3:0] Refer to SPT0[3:0] description...
Page 225: Watchdog Low Threshold Register (Adc_Wdlt)
GD32VW55x User Manual Reserved WDHT [11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. High threshold for analog watchdog 11:0 WDHT[11:0] These bits define the high threshold for the analog watchdog. Watchdog low threshold register (ADC_WDLT) 12.5.7. Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 226: Routine Sequence Register 1 (Adc_Rsq1)
GD32VW55x User Manual Routine sequence length 23:20 RL[3:0] The total number of conversion in Routine sequence equals to RL[3:0] +1. 19:0 Reserved Must be kept at reset value. Routine sequence register 1 (ADC_RSQ1) 12.5.9. Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 227: Routine Data Register (Adc_Rdata)
GD32VW55x User Manual 19:15 RSQ3[4:0] Refer to RSQ0[4:0] description 14:10 RSQ2[4:0] Refer to RSQ0[4:0] description RSQ1[4:0] Refer to RSQ0[4:0] description RSQ0[4:0] The channel number (0..10) is written to these bits to select a channel as the nth conversion in the routine sequence. Routine data register (ADC_RDATA) 12.5.11.
Page 228: Commom Control Register (Adc_Cctl)
GD32VW55x User Manual 0: All oversampled conversions for a channel are done consecutively after a trigger 1: Each conversion needs a trigger for a oversampled channel and the number of triggers is determined by the oversampling ratio(OVSR[2:0]) Note: Software is allowed to write this bit only when ADCON=0 (which ensures that no conversion is ongoing).
Page 229 GD32VW55x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). TSVREN ADCCK[2:0] Reserved Reserved Reserved Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. TSVREN Channel 9 (temperature sensor) and 10 (internal reference voltage) enable of ADC. 0: Channel 9 and 10 of ADC disable 1: Channel 9 and 10 of ADC enable 22:19...
Page 230: Watchdog Timer (Wdgt)
GD32VW55x User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 231: Figure 13-1. Free Watchdog Timer Block Diagram
GD32VW55x User Manual Figure 13-1. Free watchdog timer block diagram Status: PUD 12-Bit IRC32K Reset Prescaler DownCounter /4/8 256 Reload Control register Reload Status: PUD register The free watchdog timer is enabled by writing the value 0xCCCC to the control register (FWDGT_CTL), then the counter starts counting down.
Page 232 GD32VW55x User Manual deepsleep / standby mode immediately, more than 3 IRC32K clock interval must be inserted in the middle of reload and deepsleep / standby mode commands by software setting.
Page 233: Register Definition
GD32VW55x User Manual Register definition 13.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CMD[15:0] Write only.
Page 234 GD32VW55x User Manual 000: 1 / 4 001: 1 / 8 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to wait until PUD bit is reset before changing the prescaler value.
Page 235 GD32VW55x User Manual Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. Free watchdog timer counter reload value update During a write operation to FWDGT_RLD register, this bit is set and the value read from FWDGT_RLD register is invalid. This bit is reset by hardware after the update operation of FWDGT_RLD register.
Page 236: Window Watchdog Timer (Wwdgt)
GD32VW55x User Manual 13.2. Window watchdog timer (WWDGT) Overview 13.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 237: Figure 13-2. Window Watchdog Timer Block Diagram
GD32VW55x User Manual Figure 13-2. Window watchdog timer block diagram PCLK1/4096 Prescaler /1/2/4/8 7-Bit Down Counter CNT[6]=0 WDGTEN Reset CNT>WIN Reset Window WIN Write WWDGT_CTL The watchdog is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register.
Page 238: Figure 13-3. Window Watchdog Timing Diagram
GD32VW55x User Manual Figure 13-3. Window watchdog timing diagram CNT[6:0] Start Start 0x7F Write CNT 0x3F CNT[6]=0 cause a reset Write WWDG_CTL when CNT>WIN cause a reset Calculate the WWDGT timeout by using the formula below. ×4096 ×2 × (ms) (13-1) WWDGT PCLK1...
Page 239: Register Definition
GD32VW55x User Manual Register definition 13.2.4. WWDG base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. WDGTEN Start the Window watchdog timer.
Page 240 GD32VW55x User Manual operation of 0 has no effect. PSC[1:0] Prescaler. The time base of the watchdog counter 00: (PCLK1 / 4096) / 1 01: (PCLK1 / 4096) / 2 10: (PCLK1 / 4096) / 4 11: (PCLK1 / 4096) / 8 WIN[6:0] The Window value.
Page 241: Real Time Clock (Rtc)
GD32VW55x User Manual Real time clock (RTC) 14.1. Overview The RTC provides a time which includes hour / minute / second / sub-second and a calendar includes year / month / day / week day. The time and calendar are expressed in BCD code except sub-second.
Page 242: Function Overview
GD32VW55x User Manual 14.3. Function overview Block diagram 14.3.1. Figure 14-1. Block diagram of RTC ALARM 1 Alarm-1 Flag ALARM 0 Alarm-0 Flag Alarm-0/1 Logic Output Block Diagram Selection Logic 512Hz RTC_CALIB RTC_OUT RTC_REFIN RTC_ALARM ck_apre (Default 256 Hz) ck_spre (Default 1 Hz) IRC32K 15-bit...
Page 243: Shadow Registers Introduction
GD32VW55x User Manual 1 ~ 32(configured in RCU_CFG0 register). In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler. Asynchronous prescaler is mainly used for reducing power consumption.
Page 244: Configurable Periodic Auto-Wakeup Counter
GD32VW55x User Manual Configurable periodic auto-wakeup counter 14.3.5. In the RTC block, there is a 16-bit down counter designed to generate periodic wakeup flag. This function is enabled by set the WTEN to 1 and can be running in power saving mode. Two clock sources can be chose for the down counter: 1) RTC clock divided by 2 / 4 / 8 / 16 Assume RTC clock comes from LXTAL (32.768 KHz), this can periodically assert wakeup...
Page 245: Calendar Reading
GD32VW55x User Manual Enter initialization mode (by setting INITM=1) and polling INITF bit until INITF=1. Program both the asynchronous and synchronous prescaler factors in RTC_PSC register. Write the initial calendar values into the shadow calendar registers (RTC_TIME and RTC_DATE), and use the CS bit in the RTC_CTL register to configure the time format (12 or 24 hours).
Page 246 GD32VW55x User Manual If the two values are not equal, a third reading should performed. The third value can be seen as the correct value. RSYNF is asserted once every 2 RTC clock and at this time point, the shadow registers will be updated to current time and date.
Page 247: Resetting The Rtc
GD32VW55x User Manual Resetting the RTC 14.3.8. There are two reset sources used in RTC unit: system reset and backup domain reset. System reset will affect calendar shadow registers and some bits of the RTC_STAT. When system reset is valid, the bits or registers mentioned before are reset to the default value. Backup domain reset will affect the following registers and system reset will not affect them: RTC current real-time calendar registers RTC Control register (RTC_CTL)
Page 248: Rtc Reference Clock Detection
GD32VW55x User Manual Shift operation only works correctly when REFEN=0. Software must not write to RTC_SHIFTCTL if REFEN=1. RTC reference clock detection 14.3.10. RTC reference clock detection is another way to increase the precision of RTC second. To enable this function, you should have an external clock source (50Hz or 60 Hz) which is more precise than LXTAL clock source.
Page 249: Rtc Smooth Digital Calibration
GD32VW55x User Manual effect of such configuration will make calendar to be updated sooner. When COSD=1, 1 ck_apre cycle is removed every minute for the first 2xCOSS minutes. The effect of such configuration will make calendar to be updated later. Only in initialization mode can configure coarse calibration and the function starts after clearing INITM bit.
Page 250 GD32VW55x User Manual So using FREQI can increase the RTC frequency by 488.5PPM. The combined using of CMSK and FREQI can adjust the RTC cycles from -511 to +512 cycles in the period time which means the calibration range is -487.1PPM to +488.5PPM with a resolution of about 0.954PPM.
Page 251: Time-Stamp Function
GD32VW55x User Manual  When the calibration period is 8 seconds(by setting CWND8 bit) In this configuration, CMSK[1:0] is fixed to 0 by hardware. Using exactly 8s period to measure the accuracy of the calibration 1Hz output can guarantee the measure is within 1.907PPM (0.5 RTCCLK cycles over 8s) Re-calibration on-the-fly When the INITF bit is 0, software can update the value of RTC_HRFC using following steps:...
Page 252: Calibration Clock Output
GD32VW55x User Manual can generate an interrupt if tamper interrupt enable (TPIE) is set. The backup registers are reset when a tamper detection event occurs except if the TAMPxNOER bit is set in the RTC_TAMP register. The backup registers and the device secrets erased by tamp_erase signal can be reset by software by setting the BKERASE bit in the RTC_TAMP register Timestamp on tamper event...
Page 253: Alarm Output
GD32VW55x User Manual RTC_CALIB output is corresponding to 512Hz.It’s recommend to using rising edge of RTC_CALIB output for there may be a light jitter on falling edge. When the COS bit is set to 1, the RTC_CALIB frequency is: rtcclk (14-5) rtc_calib ( FACTOR_A+1 ) ×(FACTOR_S+1)
Page 254 GD32VW55x User Manual write 1 in Alarm 0 ALRM0F ALRM0IE ALRM0FC write 1 in Alarm 1 ALRM1F ALRM1IE ALRM1FC Wakeup WTIE write 1 in WTFC Timestamp TSIE write 1 in TSFC Write 1 in Tamper x TPxF TPxIE TPxFC Note: (*)Only active when RTC clock source is LXTAL or IRC32K.
Page 255: Register Definition
GD32VW55x User Manual 14.4. Register definition RTC base address: 0x4000 2800 Time register (RTC_TIME) 14.4.1. Address offset: 0x00 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register is write protected and can only be written in initialization state. This register has to be accessed by word (32-bit).
Page 256: Control Register (Rtc_Ctl)
GD32VW55x User Manual This register has to be accessed by word (32-bit). Reserved YRT[3:0] YRU[3:0] DOW[2:0] MONT MONU[2:0] Reserved DAYT DAYU Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 Year tens in BCD code 19:16 YRU[3:0] Year units in BCD code 15:13 DOW[2:0]...
Page 257 GD32VW55x User Manual 1: RTC_OUT output to PA3 or PA8 30:24 Reserved Must be kept at reset value. COEN Calibration output enable 0: Disable calibration output 1: Enable calibration output 22:21 OS[1:0] Output selection This bit is used for selecting flag source to output 0x0: Disable output RTC_ALARM 0x1: Enable alarm0 flag output 0x2: Enable alarm1 flag output...
Page 258 GD32VW55x User Manual 1: Enable alarm interrupt ALRM0IE RTC alarm-0 interrupt enable 0: Disable alarm interrupt 1: Enable alarm interrupt TSEN Time-stamp function enable 0: Disable time-stamp function 1: Enable time-stamp function WTEN Auto-wakeup timer function enable 0: Disable function 1: Enable function ALRM1EN Alarm-1 function enable...
Page 259: Status Register (Rtc_Stat)
GD32VW55x User Manual 0x0:RTC Clock divided by 16 0x1:RTC Clock divided by 8 0x2:RTC Clock divided by 4 0x3:RTC Clock divided by 2 0x4:0x5: ck_spre (default 1Hz) clock 0x6:0x7: ck_spre (default 1Hz) clock and 2 is added to wake-up counter. Status register (RTC_STAT) 14.4.4.
Page 260 GD32VW55x User Manual Cleared by software writing 0. Wakeup timer flag Set by hardware when wakeup timer decreased to 0. Cleared by software writing 0. This flag must be cleared at least 1.5 RTC Clock periods before WTF is set to 1 again.
Page 261: Prescaler Register (Rtc_Psc)
GD32VW55x User Manual 1: Wakeup timer update is allowed ALRM1WF Alarm 1 configuration can be write flag Set by hardware if alarm register can be wrote after ALRM1EN bit has reset. 0: Alarm registers programming is not allowed 1: Alarm registers programming is allowed ALRM0WF Alarm 0 configuration can be write flag Set by hardware if alarm register can be wrote after ALRM0EN bit has reset.
Page 262: Coarse Calibration Register (Rtc_Cosc)
GD32VW55x User Manual WTRV[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 WTRV[15:0] Auto-wakeup timer reloads value. Every (WTRV[15:0]+1) ck_wut period the WTF bit is set after WTEN=1.The ck_wut is selected by WTCS[2:0] bits. Note: This configure case is forbidden: WTRV=0x0000 with WTCS[2:0]=0b011. This register can be written only when WTWF=1.
Page 263: Alarm 0 Time And Date Register (Rtc_Alrm0Td)
GD32VW55x User Manual 0x02:-4 PPM(approximate value) … 0x1F:-63 PPM(approximate value) Alarm 0 time and date register (RTC_ALRM0TD) 14.4.8. Address offset: 0x1C System reset: not effect Backup domain reset value: 0x0000 0000 This registe is write protected and can only be written in initialization state. This register has to be accessed by word (32-bit).
Page 264: Alarm 1 Time And Date Register (Rtc_Alrm1Td)
GD32VW55x User Manual 11:8 MNU[3:0] Minutes units in BCD code MSKS Alarm second mask bit 0: Not mask second field 1: Mask second field SCT[2:0] Second tens in BCD code SCU[3:0] Second units in BCD code Alarm 1 time and date register (RTC_ALRM1TD) 14.4.9.
Page 265: Write Protection Key Register (Rtc_Wpk)
GD32VW55x User Manual MSKM Alarm minutes mask bit 0: Not mask minutes field 1: Mask minutes field 14:12 MNT[2:0] Minutes tens in BCD code 11:8 MNU[3:0] Minutes units in BCD code MSKS Alarm second mask bit 0: Not mask second field 1: Mask second field SCT[2:0] Second tens in BCD code...
Page 266: Shift Function Control Register (Rtc_Shiftctl)
GD32VW55x User Manual 31:16 Reserved Must be kept at reset value. 15:0 SSC[15:0] Sub second value This value is the counter value of synchronous prescaler. Second fraction value is calculated by the below formula: Second fraction = ( FACTOR_S - SSC ) / ( FACTOR_S + 1 ) Shift function control register (RTC_SHIFTCTL) 14.4.12.
Page 267: Date Of Time Stamp Register (Rtc_Dts)
GD32VW55x User Manual this register. This register has to be accessed by word (32-bit). Reserved HRT[1:0] HRU[3:0] Reserved MNT[2:0] MNU[3:0] Reserved SCT[2:0] SCU[3:0] Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. AM / PM mark 0:AM or 24-hour format 1:PM 21:20 HRT[1:0]...
Page 268: Sub Second Of Time Stamp Register (Rtc_Ssts)
GD32VW55x User Manual 31:16 Reserved Must be kept at reset value. 15:13 DOW[2:0] Days of the week MONT Month tens in BCD code 11:8 MONU[3:0] Month units in BCD code Reserved Must be kept at reset value. DAYT[1:0] Day tens in BCD code DAYU[3:0] Day units in BCD code Sub second of time stamp register (RTC_SSTS)
Page 269: Tamper Register (Rtc_Tamp)
GD32VW55x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. FREQI Increase RTC frequency by 488.5PPM 0: No effect 1: One RTCCLK pulse is inserted every 2 pulses. This bit should be used in conjunction with CMSK bit. If the input clock frequency is 32.768KHz, the number of RTCCLK pulses added during 32s calibration window is (512 * FREQI) - CMSK CWND8...
Page 270 GD32VW55x User Manual 30:21 Reserved Must be kept at reset value. TP1NOER Tamper 1 no erase 0: Tamper 1 event erases the backup registers. 1: Tamper 1 event does not erase the backup registers TP0NOER Tamper 0 no erase 0: Tamper 0 event erases the backup registers. 1: Tamper 0 event does not erase the backup registers RTC_ALARM output type 0: Open-drain output type...
Page 271: Alarm 0 Sub Second Register (Rtc_Alrm0Ss)
GD32VW55x User Manual 0x7: Sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) TPTS Make tamper function used for timestamp function 0:No effect 1:TSF is set when tamper event detected even TSEN=0 Reserved Must be kept at reset value. TP1EG Tamper 1 event trigger edge If tamper detection is in edge mode(FLT =0): 0: Rising edge triggers a tamper detection event 1: Falling edge triggers a tamper detection event...
Page 272: Alarm 1 Sub Second Register (Rtc_Alrm1Ss)
GD32VW55x User Manual Reserved MSKSSC[3:0] Reserved Reserved SSC[14:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:24 MSKSSC[3:0] Mask control bit of SSC 0x0: Mask alarm sub second setting. The alarm asserts at every second time point if all the rest alarm fields are matched.
Page 273: Backup Registers (Rtc_Bkpx) (X = 0
GD32VW55x User Manual Reserved SSC[14:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:24 MSKSSC[3:0] Mask control bit of SSC 0x0: Mask alarm sub second setting. The alarm asserts at every second time point if all the rest alarm fields are matched. 0x1: SSC[0] is to be compared and all others are ignored 0x2: SSC[1:0] is to be compared and all others are ignored 0x3: SSC[2:0] is to be compared and all others are ignored...
Page 274 GD32VW55x User Manual Bits Fields Descriptions 31:0 DATA[31:0] Data These registers can be wrote or read by software. Tamper detection flag TPxF assertion will reset these registers.
Page 275: Timer (Timerx)
GD32VW55x User Manual Timer (TIMERx) Table 15-1. Timers (TIMERx) are divided into four sorts TIMER TIMER0 TIMER1/2 TIMER15/16 TIMER5 TYPE Advanced General-L0 General-L4 Basic Prescaler 16-bit 16-bit 16-bit 16-bit Counter 16-bit 32-bit(TIMER1/2) 16-bit 16-bit UP,DOWN, UP,DOWN, Count mode UP ONLY UP ONLY Center-aligned Center-aligned...
Page 276: Advanced Timer (Timerx, X=0)
GD32VW55x User Manual Advanced timer (TIMERx, x=0) 15.1. Overview 15.1.1. The advanced timer module (Timer0) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 277: Block Diagram
GD32VW55x User Manual Block diagram 15.1.3. Figure 15-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer. Figure 15-1. Advanced timer block diagram CI0F_ED,CI0FE0,CI1FE1 TRGO Trigger Selector CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler &Edge Detector CH2_IN CH3_IN...
Page 278: Figure 15-2. Normal Mode, Internal Clock Divided By 1
GD32VW55x User Manual introduced later. When the TSCFGy[3:0] (y=3,4,5) are setting to an available value, the internal clock TIMER_CK is the counter prescaler driving clock source. Figure 15-2. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG...
Page 279: Figure 15-3. Timing Chart Of Psc Value Change From 0 To 2
GD32VW55x User Manual Figure 15-3. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 280: Figure 15-5. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32VW55x User Manual Figure 15-4. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 15-5.
Page 281: Figure 15-6. Timing Chart Of Down Counting Mode, Psc=0/2
GD32VW55x User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter the counter will start counting down from the counter-reload value again and an underflow event will be generated.
Page 282: Figure 15-7. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32VW55x User Manual Figure 15-7. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 283: Figure 15-8. Timing Chart Of Center-Aligned Counting Mode
GD32VW55x User Manual Figure 15-8. Timing chart of center-aligned counting mode show some examples of the counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 15-8. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF...
Page 284: Figure 15-9. Repetition Timechart For Center-Aligned Counter
GD32VW55x User Manual of CREP is odd, and the counter is counting in center-aligned mode, the update event is generated (on overflow or underflow) depending on when the written CREP value takes effect. If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow.
Page 285: Figure 15-11. Repetition Timechart For Down-Counter
GD32VW55x User Manual Figure 15-11. Repetition timechart for down-counter TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 286: Figure 15-12. Channel Input Capture Principle
GD32VW55x User Manual Figure 15-12. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FE0 CI0FED Rising/Falling Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal One of channels’...
Page 287: Figure 15-13. Channel Output Compare Principle (With Complementary Output, X=0,1,2)
GD32VW55x User Manual Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 288: Figure 15-15. Output-Compare In Three Modes
GD32VW55x User Manual 2) Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), CHxNE=1 (the output of CHx_ON is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(high) level. When CH0_O and CH0_ON are output at the same time, the specific outputs of CH0_O and CH0_ON are related to the relevant bits (ROS, IOS, POE and DTCFG bits) in the TIMERx_CCHP register.
Page 289 GD32VW55x User Manual Figure 15-15. Output-compare in three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 290: Figure 15-16. Timing Chart Of Eapwm
GD32VW55x User Manual Figure 15-16. Timing chart of EAPWM Figure 15-17. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF CAM=2'b11 up/down CHxIF Channel output prepare signal Figure 15-13.
Page 291 GD32VW55x User Manual by setting the CHxCOMCTL field to 0x00, set to 1 by setting the CHxCOMCTL field to 0x01, set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07.
Page 292: Table 15-2. Complementary Outputs Controlled By Parameters
GD32VW55x User Manual Table 15-2. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off-state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 293: Figure 15-18. Complementary Output With Dead-Time Insertion
GD32VW55x User Manual Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for all channels expect for channel 3.
Page 294: Figure 15-19. Output Behavior Of The Channel In Response To A Break (The Break High Active)
GD32VW55x User Manual cannot be set both to active level when break occurs. The break sources are input break pin and HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is setting by the BRKP bit in TIMERx_CCHP.
Page 295: Figure 15-20. Counter Behavior With Ci0Fe0 Polarity Non-Inverted In Mode 2
GD32VW55x User Manual quadrature decoder mode. The quadrature decoder can be regarded as an external clock with a directional selection. This means that the counter counts continuously in the interval between 0 and the counter-period value. Therefore, TIMERx_CAR register must be configured before the counter starts to count.
Page 296: Figure 15-22. Hall Sensor Is Used To Bldc Motor
GD32VW55x User Manual Hall sensor function Hall sensor is generally used to control BLDC Motor; advanced timer can support this function. Figure 15-22. Hall sensor is used to BLDC motor show how to connect. And we can see we need two timers.
Page 297: Figure 15-23. Hall Sensor Timing Between Two Timers
GD32VW55x User Manual Figure 15-23. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_INPUT CH1_INPUT CH2_INPUT CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead -time) CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Master-slave management The TIMERx can be synchronized with a trigger in several modes including restart mode, pause mode...
Page 298: Figure 15-24. Restart Mode
GD32VW55x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 0111: CI1FE1 the trigger source, used. 1000: ETIFP configure the ETP for For the ETIFP, filter polarity selection and can be used by inversion. configuring ETFC and prescaler can be used by configuring ETPSC.
Page 299: Figure 15-26. Event Mode
GD32VW55x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Event mode ETPSC = 1, ETI is TSCFG5[3:0] = 4’b The counter will start ETP = 0, the polarity divided by 2. to count when a rising 1000 of ETI does not ETFC = 0, ETI does edge of trigger input...
Page 300 GD32VW55x User Manual Figure 15-27. Single pulse mode, TIMERx_CHxCV = 4, TIMERx_CAR=99 Timers interconnection The timers can be internally connected for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the master mode while configuring another timer to be in the slave mode.
Page 301: Figure 15-28. Trigger Mode Of Timer0 Controlled By Enable Signal Of Timer2
GD32VW55x User Manual Start TIMER2 by writing 1 to the CEN bit (TIMER2_CTL0 register). Figure 15-28. Trigger mode of TIMER0 controlled by enable signal of TIMER2 TIMER2 TIMER_CK CNT_REG TIMER0 TRGIF CNT_REG In this example, the update event can also be used as trigger source instead of enable signal. Refer to Figure 15-29.
Page 302: Figure 15-30. Pause Mode Of Timer0 Controlled By Enable Signal Of Timer2
GD32VW55x User Manual by 3 from TIMER_CK (f /3). Steps are shown as follows: PSC_CLK TIMER_CK Configure TIMER2 in master mode and output enable signal as trigger output (MMC=3’b001 in the TIMER2_CTL1 register). 2. Configure TIMER0 to get the input trigger from TIMER2, configure TIMER0 in pause mode (TSCFG5 [3:0] = 0011 in the_ SYSCFG_TIMERxCFG register).
Page 303: Figure 15-32. Trigger Timer0 And Timer2 By The Ci0 Signal Of Timer2
GD32VW55x User Manual  Using an external trigger to start two timers synchronously. The start of TIMER0 is triggered by the enable signal of TIMER2, and TIMER2 is triggered by its CI0 input rising edge. To ensure that two timers start synchronously, TIMER2 must be configured in master/slave mode.
Page 304 GD32VW55x User Manual transfer), the timer sends only one DMA request. While if TIMERx_DMATC is not 0, such as 3 (4 transfers), then timer will send 3 more requests to DMA, and DMA will access timer’s registers DMATA+0x4, DMATA+0x8 and DMATA+0xC at the next 3 accesses to TIMERx_DMATB.
Page 305: Timerx Registers(X=0)
GD32VW55x User Manual TIMERx registers(x=0) 15.1.5. TIMER0 access base address: 0x4001 0000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits Fields Descriptions 31:10 Reserved...
Page 306 GD32VW55x User Manual After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is automatically modified by hardware and read only. Single pulse mode.
Page 307 GD32VW55x User Manual Reserved Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output Refer to ISO0N bit...
Page 308 GD32VW55x User Manual counter resert source: Master timer generate a reset the UPG bit in the TIMERx_SWEVG register is set 001: Enable. When a conter start event occurs, a TRGO trigger signal is output. The counter start source : CEN control bit is set The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output.
Page 309 GD32VW55x User Manual This register has to be accessed by word (32-bit) Reserved SMC1 ETPSC[1:0] ETFC[3:0] Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level . 1: ETI is active at falling edge or low level .
Page 310 GD32VW55x User Manual EXTFC[3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time.
Page 311 GD32VW55x User Manual 1: enabled CMTDEN Commutation DMA request enable 0: disabled 1: enabled CH3DEN Channel 3 capture/compare DMA request enable 0: disabled 1: enabled CH2DEN Channel 2 capture/compare DMA request enable 0: disabled 1: enabled CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN...
Page 312 GD32VW55x User Manual CH0IE Channel 0 capture/compare interrupt enable 0: disabled 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CH3OF...
Page 313 GD32VW55x User Manual 1: An active level has been detected. TRGIF Trigger interrupt flag This flag is set by hardware on trigger event and cleared by software. When the slave mode controller is enabled in all modes but pause mode, an active edge on trigger input generates a trigger event.
Page 314 GD32VW55x User Manual Reserved BRKG TRGG CMTG CH3G CH2G CH1G CH0G Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. BRKG Break event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the POEN bit is cleared and BRKIF flag is set, related interrupt or DMA transfer can occur if enabled.
Page 315 GD32VW55x User Manual 1: Generate a channel 1 capture or compare event Update event generation This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared if the center-aligned or up counting mode is selected, else (down counting) it takes the auto-reload value.
Page 316 GD32VW55x User Manual 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS. Note: When CH1MS[1:0]=11, it is working only if an internal trigger input is selected, through TSCFG7[3:0] bit-field in SYSCFG_TIMERxCFG (x=0) register.
Page 317 GD32VW55x User Manual 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 318 GD32VW55x User Manual 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 319 GD32VW55x User Manual Refer to CH0COMCEN description 14:12 CH3COMCTL[2:0] Channel 3 compare output control Refer to CH0COMCTL description CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description CH3COMFEN Channel 3 output compare fast enable Refer to CH0COMFEN description CH3MS[1:0] Channel 3 mode selection This bit-field specifies the direction of the channel and the input signal selection.
Page 320 GD32VW55x User Manual than TIMERx_CH2CV, and high otherwise. When counting down, O2CPRE is high when the counter is larger than TIMERx_CH2CV, and low otherwise. If configured in PWM mode, the O2CPRE level changes only when the output compare mode is adjusted from “Timing” mode to “PWM” mode or the comparison result changes.
Page 321 GD32VW55x User Manual Refer to CH0CAPPSC description CH3MS[1:0] Channel 3 mode selection Same as Output compare mode CH2CAPFLT[3:0] Channel 2 input capture filter control The CI2 input signal can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the CI2 input signal according to and record the number of times of the same level of the signal.
Page 322 GD32VW55x User Manual This register has to be accessed by word (32-bit). Reserved CH3NP Reserved CH3P CH3EN CH2NP CH2NEN CH2P CH2EN CH1NP CH1NEN CH1P CH1EN CH0NP CH0NEN CH0P CH0EN Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH3NP Channel 3 complementary output polarity Refer to CH0NP description...
Page 323 GD32VW55x User Manual 1: Channel 0 complementary output low level is active level When channel 0 is configured in input mode, together with CH0P, this bit is used to define the polarity of CI0. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 or 10.
Page 324 GD32VW55x User Manual CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 325 GD32VW55x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Counter repetition register (TIMERx_CREP) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 326 GD32VW55x User Manual 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 327 GD32VW55x User Manual 31:16 Reserved Must be kept at reset value. 15:0 CH2VAL[15:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 2 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 328 GD32VW55x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value POEN Primary output enable The bit can be set to 1 by: - Software - Hardware if OREN is set to 1 at the next update event.. The bit can be cleared to 0 by: - Software - Valid fault input (asynchronous).
Page 329 GD32VW55x User Manual This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. Idle mode “off-state” enable When POEN bit is reset (Idle mode), this bit can be set to enable the “off-state” for the channels which has been configured in output mode.
Page 330 GD32VW55x User Manual This register has to be accessed by word (32-bit). Reserved Reserved DMATC[4:0] Reserved DMATA [4:0] Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed defines the number(n) of the register that DMA will access(R/W), n = (DMATC [4:0] +1).
Page 331 GD32VW55x User Manual Configuration register (TIMERx_CFG) Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CHVSEL OUTSEL Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software.
Page 332: General Level0 Timer (Timerx, X=1, 2)
GD32VW55x User Manual General level0 timer (TIMERx, x=1, 2) 15.2. Overview 15.2.1. The general level0 timer module (Timer1, 2) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 333: Function Overview
GD32VW55x User Manual Figure 15-33. General Level 0 timer block diagram CI0F_ED,CI0FE0,CI1FE1 TRGO Trigger Selector CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN External Trigger Input logic TIMERx_CHxCV Counter Polarity selection Edge detector PSC_CLK Prescaler TIMER_CK DMA REQ/ACK Filter TIMERx_CH0...
Page 334: Figure 15-34. Normal Mode, Internal Clock Divided By 1
GD32VW55x User Manual Figure 15-34. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  TSCFG6[3:0] are setting to an available value (external clock mode 0). External input pin is selected as timer clock source.
Page 335: Figure 15-35. Timing Chart Of Psc Value Change From 0 To 2
GD32VW55x User Manual Figure 15-35. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 336: Figure 15-36. Timing Chart Of Up Counting Mode, Psc=0/2
GD32VW55x User Manual Figure 15-36. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 15-37.
Page 337: Figure 15-38. Timing Chart Of Down Counting Mode,Psc=0/2
GD32VW55x User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter restarts to count again from the counter-reload value. The update event is generated at each counter underflow.
Page 338: Figure 15-39. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32VW55x User Manual Figure 15-39. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 339: Figure 15-40. Timing Chart Of Center-Aligned Counting Mode
GD32VW55x User Manual Figure 15-40. Timing chart of center-aligned counting mode show some examples of the counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 15-40. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF...
Page 340: Figure 15-41. Channel Input Capture Principle
GD32VW55x User Manual generated if enabled by CHxIE = 1. Figure 15-41. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P TIMER_CK CI0FE0 Rising/Falling CI0FED Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0CAPPSC CH0MS TIMERx_CC_INT Capture INT From Other Channal One of channels’...
Page 341: Figure 15-42. Channel Output Compare Principle (X=0,1,2,3)
GD32VW55x User Manual TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 342: Figure 15-43. Output-Compare In Three Modes
GD32VW55x User Manual Step2: Compare mode configuration. * Set the shadow enable mode by CHxCOMSEN * Set the output mode (Set/Clear/Toggle) by CHxCOMCTL. * Select the active high polarity by CHxP * Enable the output by CHxEN Step3: Interrupt/DMA-request enables configuration by CHxIE/CxCDE Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV.
Page 343: Figure 15-44. Timing Chart Of Eapwm
GD32VW55x User Manual The CAPWM period is determined by 2*TIMERx_CAR, and duty cycle is determined by 2*TIMERx_CHxCV. Figure 15-45. Timing chart of CAPWM shows the CAPWM output and interrupts waveform. If TIMERx_CHxCV is greater than TIMERx_CAR, the output will be always active under PWM mode0 (CHxCOMCTL==3’b110).
Page 344: Table 15-5. Examples Of Slave Mode
GD32VW55x User Manual Channel output prepare signal , when the 0,1,2,3) As is shown in Figure 15-42. Channel output compare principle (x= TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function.
Page 345: Figure 15-46. Restart Mode
GD32VW55x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 0101: CI0F_ED and inversion. CHxCAPFLT, no 0110: CI0FE0 If ETIFP is selected as prescaler can be 0111: CI1FE1 the trigger source, used. 1000: ETIFP configure the ETP for For the ETIFP, filter polarity selection and can be used by...
Page 346: Figure 15-47. Pause Mode
GD32VW55x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 15-47. Pause mode TIMER_CK CNT_REG CI0FE0 TRGIF Event mode ETPSC = 1, ETI is TSCFG5[3:0] = 4’b The counter will start ETP = 0, the polarity divided by 2. to count when a rising 1000 of ETI does not...
Page 347: Figure 15-49. Single Pulse Mode, Timerx_Chxcv = 4, Timerx_Car=99
GD32VW55x User Manual In the single pulse mode, the trigger active edge which sets the CEN bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value. In order to reduce the delay to a minimum value, the user can set the CHxCOMFEN bit in each TIMERx_CHCTL0/1 register.
Page 348 GD32VW55x User Manual If one more time DMA request event coming, TIMERx will repeat the process as above. Timer debug mode When the RISCV halted, and the TIMERx_HOLD configuration bit in DBG_CTL0 register set to 1, the TIMERx counter stops.
Page 349: Timerx Registers(X=1, 2)
GD32VW55x User Manual TIMERx registers(x=1, 2) 15.2.5. TIMER1 access base address: 0x4000 0000 TIMER2 access base address: 0x4000 0400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE...
Page 350 GD32VW55x User Manual can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is automatically modified by hardware and read only.
Page 351 GD32VW55x User Manual This register has to be accessed by word (32-bit). Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, CH1 and CH2 pins is selected as channel 0 trigger input.
Page 352 GD32VW55x User Manual 0: When capture or compare event occurs, the DMA request of channel x is sent 1: When update event occurs, the DMA request of channel x is sent. Reserved Must be kept at reset value. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit)
Page 353 GD32VW55x User Manual 11: The prescaler is 8. 11:8 ETFC[3:0] External trigger filter control The external trigger can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the external trigger signal according to f and record the number of times of the same level of the signal.
Page 354 GD32VW55x User Manual Reserved TRGDEN Reserved CH3DEN CH2DEN CH1DEN CH0DEN UPDEN Reserved TRGIE Reserved CH3IE CH2IE CH1IE CH0IE UPIE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. TRGDEN Trigger DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value.
Page 355 GD32VW55x User Manual CH1IE Channel 1 capture/compare interrupt enable 0: disabled 1: enabled CH0IE Channel 0 capture/compare interrupt enable 0: disabled 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 356 GD32VW55x User Manual This flag is set by hardware on trigger event and cleared by software. When the slave mode controller is enabled in all modes but pause mode, an active edge on trigger input generates a trigger event. When the slave mode controller is enabled in pause mode both edges on trigger input generates a trigger event.
Page 357 GD32VW55x User Manual 31:7 Reserved Must be kept at reset value. TRGG Trigger event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_STAT register is set, related interrupt or DMA transfer can occur if enabled.
Page 358 GD32VW55x User Manual CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control...
Page 359 GD32VW55x User Manual 011: Toggle on match. O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV. 100: Force low. O0CPRE is forced to low level. 101: Force high. O0CPRE is forced to high level. 110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller than TIMERx_CH0CV, and low otherwise.
Page 360 GD32VW55x User Manual 31:16 Reserved Must be kept at reset value. 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0] Channel 1 input capture prescaler Refer to CH0CAPPSC description CH1MS[1:0] Channel 1 mode selection Same as Output compare mode CH0CAPFLT[3:0] Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit-field configure the...
Page 361 GD32VW55x User Manual Channel control register 1 (TIMERx_CHCTL1) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH3COM CH3COM CH3COM CH2COM CH2COM CH2COM CH3COMCTL[2:0] CH2COMCTL[2:0] CH3MS[1:0] CH2MS[1:0] CH3CAPFLT[3:0] CH3CAPPSC[1:0] CH2CAPFLT[3:0] CH2CAPPSC[1:0] Output compare mode: Bits Fields Descriptions...
Page 362 GD32VW55x User Manual CH2COMCTL[2:0] Channel 2 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE. In addition, the high level of O0CPRE is the active level, and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits. 000: Timing mode.
Page 363 GD32VW55x User Manual TIMERx_CHCTL2 register is reset).). 00: Channel 2 is programmed as output mode 01: Channel 2 is programmed as input mode, IS2 is connected to CI2FE2 10: Channel 2 is programmed as input mode, IS2 is connected to CI3FE2 11: Channel 2 is programmed as input mode, IS2 is connected to ITS.
Page 364 GD32VW55x User Manual 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 365 GD32VW55x User Manual Refer to CH0EN description CH1NP Channel 1 complementary output polarity Refer to CH0NP description Reserved Must be kept at reset value CH1P Channel 1 capture/compare function polarity Refer to CH0P description CH1EN Channel 1 capture/compare function enable Refer to CH0EN description CH0NP Channel 0 complementary output polarity...
Page 366 GD32VW55x User Manual This register has to be accessed by word(32-bit) CNT[31:16] CNT[15:0] Bits Fields Descriptions 31:0 CNT[31:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 367 GD32VW55x User Manual CARL[15:0] Bits Fields Descriptions 31:0 CARL[31:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) (x=1,2) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) CH0VAL[31:16] CH0VAL[15:0] Bits...
Page 368 GD32VW55x User Manual 31:0 CH1VAL[31:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 369 GD32VW55x User Manual When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 370 GD32VW55x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed. The transfer Timer is calculated by hardware, and ranges from 0 to DMATC.
Page 371 GD32VW55x User Manual Reserved CHVSEL Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored 0: No effect Reserved...
Page 372: General Level4 Timer (Timerx, X=15,16)
GD32VW55x User Manual General level4 timer (TIMERx, x=15,16) 15.3. Overview 15.3.1. The general level4 timer module (TIMER15, TIMER16) is a one-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The general level4 timer has a 16-bit counter that can be used as an unsigned counter.
Page 373: Function Overview
GD32VW55x User Manual of the general level4 timer. Figure 15-50. General level4 timer block diagram Input Logic Synchronizer&Filter CH0_IN Edge selector Prescaler &Edge Detector TIMERx_CHxCV CK_TIMER Counter PSC_CLK Counter Control TIMER_CK DMA REQ/ACK TIMERx_CH0 TIMERx_UP DMA controller req en/direct req set Register /Interrupt APB BUS Output Logic...
Page 374: Figure 15-51. Timing Chart Of Internal Clock Divided By 1
GD32VW55x User Manual Figure 15-51. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 375: Figure 15-53. Up-Counter Timechart, Psc=0/2
GD32VW55x User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again and an overflow event will be generated.
Page 376: Figure 15-54. Up-Counter Timechart, Change Timerx_Car On The Go
GD32VW55x User Manual Figure 15-54. Up-counter timechart, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 377: Figure 15-55. Repetition Timechart For Up-Counter
GD32VW55x User Manual Figure 15-55. Repetition timechart for up-counter TIMER_CK PSC_CLK 98 99 0 97 98 99 0 98 99 98 99 0 CNT_REG 98 99 0 98 99 0 Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels...
Page 378: Figure 15-56. Channel Input Capture Principle
GD32VW55x User Manual principle Figure 15-56. input capture Channel Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FE0 CI0FED Rising/Falling Capture Clock Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal Channels’ input signals (CIx) is the TIMERx_CHx signal. First, the channel input signal (CIx) is synchronized to TIMER_CK domain, and then sampled by a digital filter to generate a filtered input signal.
Page 379: Figure 15-57. Channel Output Compare Principle (With Complementary Output, X=0)
GD32VW55x User Manual Channel output compare function Channel principle Figure 15-57. output compare (with complementary output, x=0) OxCPRE Capture/ compare register CNT>CHxCV Output Output enable CHxCV CHx_O Compare complementary and polarity CNT=CHxCV output control protection selector CHx_ON register CHxP,CHxNP CNT<CHxCV CHxCOMCTL CHxE,CHxNE &Dead-Time...
Page 380: Figure 15-58. Output-Compare Under Three Modes
GD32VW55x User Manual * Enable the output by CHxEN Step3: Interrupt/DMA-request enables configuration by CHxIE/CHxDEN Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV About the CHxVAL; you can change it on the go to meet the waveform you expected. Step5: Start the counter by CEN.
Page 381 GD32VW55x User Manual Figure 15-59. PWM mode timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF Channel output prepare signal Figure 15-57. Channel output compare principle (with complementary As is shown in output, x=0).When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 382: Table 15-6. Complementary Outputs Controlled By Parameters
GD32VW55x User Manual Table 15-6. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off-state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 383: Figure 15-60. Complementary Output With Dead-Time Insertion
GD32VW55x User Manual Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for channel 1.
Page 384: Figure 15-61. Output Behavior In Response To A Break(The Break High Active)
GD32VW55x User Manual HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is setting by the BRKP bit in TIMERx_CCHP. When a break occurs, the POEN bit is cleared asynchronously, the output CHx_O and CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0.
Page 385: Figure 15-62. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X99
GD32VW55x User Manual the counter will be stopped and its value held. If the CEN bit is automatically cleared to 0 by a hardware update event, the counter will be reinitialized. In the single pulse mode, the trigger active edge which sets the CEN bit to 1 will enable the counter.
Page 386 GD32VW55x User Manual Timer debug mode When the RISCV halted, and the TIMERx_HOLD configuration bit in DBG_CTL1 register set to 1, the TIMERx counter stops.
Page 387: Timerx Registers(X=15, 16)
GD32VW55x User Manual TIMERx registers(x=15, 16) 15.3.5. TIMER15 access base address: 0x4001 8000 TIMER16 access base address: 0x4001 8400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CKDIV[1:0] ARSE Reserved...
Page 388 GD32VW55x User Manual 1: This event generates update interrupts or DMA requests: The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values.
Page 389 GD32VW55x User Manual 1: When POEN bit is reset, CH0_O is set high The CH0_O output changes after a dead-time if CH0_ON is implemented. This bit can be modified only when PROT [1:0] bits in TIMERx_CCHP register is 00. Reserved Must be kept at reset value DMAS DMA request source selection...
Page 390 GD32VW55x User Manual 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CMTIE Commutation interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CH0IE Channel 0 capture/compare interrupt enable 0: disabled...
Page 391 GD32VW55x User Manual 1: Over capture interrupt occurred Reserved Must be kept at reset value. BRKIF Break interrupt flag When the break input is inactive, the bit is set by hardware. When the break input is inactive, the bit can be cleared by software. 0: No active level break has been detected.
Page 392 GD32VW55x User Manual 31:8 Reserved Must be kept at reset value BRKG Break event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the POEN bit is cleared and BRKIF flag is set, related interrupt or DMA transfer can occur if enabled.
Page 393 GD32VW55x User Manual CH0COM CH0COM Reserved CH0COMCTL[2:0] Reserved CH0MS[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:7 Reserved Must be kept at reset value CH0COMCTL[2:0] Channel 0 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE.
Page 394 GD32VW55x User Manual 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 395 GD32VW55x User Manual 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 396 GD32VW55x User Manual 1: Channel 0 complementary output enabled CH0P Channel 0 capture/compare function polarity When channel 0 is configured in output mode, this bit specifies the output signal polarity. 0: Channel 0 high level is active level 1: Channel 0 low level is active level When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity.
Page 397 GD32VW55x User Manual the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock.
Page 398 GD32VW55x User Manual Counter repetition register (TIMERx_CREP) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CREP[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate.
Page 399 GD32VW55x User Manual Complementary channel protection register (TIMERx_CCHP) Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved POEN OAEN BRKP BRKEN PROT[1:0] DTCFG[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value POEN Primary output enable The bit can be set to 1 by:...
Page 400 GD32VW55x User Manual 1: Break inputs enabled This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00. Run mode “off-state” enable When POEN bit is set (Run mode), this bit can be set to enable the “off-state” for the channels which has been configured in output mode.
Page 401 GD32VW55x User Manual 3’b110 (32+ DTCFG[4:0]) * t DTS_CK 3’b111 (32+ DTCFG[4:0]) * t DTS_CK Note: 1. t is the period of DTS_CK which is configured by CKDIV[1:0] in DTS_CK TIMERx_CTL0. 2. This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00.
Page 402 GD32VW55x User Manual DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed. The transfer Timer is calculated by hardware, and ranges from 0 to DMATC.
Page 403: Basic Timer (Timerx, X=5)
GD32VW55x User Manual Basic timer (TIMERx, x=5) 15.4. Overview 15.4.1. The basic timer module (Timer5) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request. Characteristics 15.4.2. ...
Page 404: Figure 15-64. Timing Chart Of Internal Clock Divided By 1
GD32VW55x User Manual Figure 15-64. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 405: Figure 15-66. Timing Chart Of Up Counting Mode, Psc=0/2
GD32VW55x User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again.The update event is generated at each counter overflow.
Page 406: Figure 15-67. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32VW55x User Manual Figure 15-67. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 407: Timerx Registers(X=5)
GD32VW55x User Manual TIMERx registers(x=5) 15.4.5. TIMER5 access base address: 0x4000 1000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved ARSE Reserved UPDIS Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 408 GD32VW55x User Manual The counter generates an overflow or underflow event The slave mode controller generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the slave mode controller does not generate an update event, but the counter and prescaler are initialized.
Page 409 GD32VW55x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value.
Page 410 GD32VW55x User Manual Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared.
Page 411 GD32VW55x User Manual This register has to be accessed by word (32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 412: Universal Synchronous/Asynchronous Receiver /Transmitter (Usart)
GD32VW55x User Manual Universal synchronous/asynchronous receiver /transmitter (USART) 16.1. Overview The Universal Synchronous / Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK (PCLK1, PCLK2 and CK_USART0 available only for USART0) to produces a dedicated wide range baudrate clock for the USART transmitter and receiver.
Page 413 GD32VW55x User Manual  Parity control Transmits parity bit. – Checks parity of received data byte. – LIN break generation and detection.   IrDA support.  Synchronous mode and transmitter clock output for synchronous transmission.  ISO 7816-3 compliant smartcard interface Character mode (T=0).
Page 414: Function Overview
GD32VW55x User Manual 16.3. Function overview The interface is externally connected to another device by the main pins listed in Table 16-1. Description of USART important pins. Table 16-1. Description of USART important pins Type Description Input Receive Data Output I/O (single- Transmit Data.
Page 415: Baud Rate Generation
GD32VW55x User Manual In transmission and reception, the number of stop bits can be configured by the STB[1:0] bits in the USART_CTL1 register. Table 16-2. Configuration of stop bits STB[1:0] stop bit length (bit) usage description Default value Smartcard mode for receiving Normal USART and single-wire modes Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1.
Page 416: Usart Transmitter
GD32VW55x User Manual Get the value of USART_BAUD by calculating the value of USARTDIV: If USARTDIV=30.37, then INTDIV=30 (0x1E). 16*0.37=5.92, he nearest integer is 6, so FRADIV=6 (0x6). USART_BAUD=0x1E6. roundness of Note: If the FRADIV is 16 (overflow), the carry must be added to the integer part.
Page 417: Usart Receiver
GD32VW55x User Manual Figure 16-3. USART transmit procedure Write data0 to Write data2 to Write data1 to USART_TDATA by USART_TDATA by USART_TDATA by DMA or software DMA or software DMA or software set by set by set by hardware hardware hardware data0 data1...
Page 418: Figure 16-4. Oversampling Method Of A Receive Frame Bit (Osb=0)
GD32VW55x User Manual frame bit is 0, the frame bit is confirmed as a 0, else 1. If the value of the three samples of any bit are not the same, whatever it is a start bit, data bit, parity bit or stop bit, a noisy error (NERR) status will be generated for the frame.
Page 419: Use Dma For Data Buffer Access
GD32VW55x User Manual Use DMA for data buffer access 16.3.5. To reduce the burden of the processor, DMA can be used to access the transmitting and receiving data buffer. The DENT bit in USART_CTL2 is used to enable the DMA transmission, and the DENR bit in USART_CTL2 is used to enable the DMA reception.
Page 420: Hardware Flow Control
GD32VW55x User Manual Figure 16-6. Configuration step when using DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal SRAM as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 421: Multi-Processor Communication
GD32VW55x User Manual RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full. CTS flow control The USART transmitter monitors the nCTS input pin to decide whether a data frame can be transmitted.
Page 422 GD32VW55x User Manual The idle frame wake up method is selected by default. If the RWU bit is reset, an idle frame is detected on the RX pin, the IDLEF bit inUSART_STAT will be set. If the RWU bit is set, an idle frame is detected on the RX pin, the hardware clears the RWU bit and exits the mute mode.
Page 423: Figure 16-9. Break Frame Occurs During Idle State
GD32VW55x User Manual Figure 16-9. Break frame occurs during idle state As shown in Figure 16-10. Break frame occurs during a frame, if a break frame occurs during a frame on the RX pin, the FERR status will be asserted for the current frame. Break frame occurs during a frame Figure 16-10.
Page 424: Figure 16-11. Example Of Usart In Synchronous Mode
GD32VW55x User Manual Figure 16-11. Example of USART in synchronous mode Figure 16-12. 8-bit format USART synchronous waveform (CLEN=1) IrDA SIR ENDEC mode 16.3.10. The IrDA mode is enabled by setting the IREN bit in USART_CTL2. The LMEN, STB[1:0], CKEN bits in USART_CTL1 and HDEN, SCEN bits in USART_CTL2 should be cleared in IrDA mode.
Page 425: Figure 16-13. Irda Sir Endec Module
GD32VW55x User Manual Figure 16-13. IrDA SIR ENDEC module Inside chip Outside chip RX pin Receive Decoder Infrared Normal IREN USART TX pin Transmit Encoder SIR MODULE In IrDA mode, the polarity of the TX and RX pins is different. The TX pin is usually at low state, while the RX pin is usually at high state.
Page 426: Figure 16-15. Iso7816-3 Frame Format
GD32VW55x User Manual Half-duplex communication mode 16.3.11. The half-duplex communication mode is enabled by setting the HDEN bit in USART_CTL2. The LMEN, CKEN bits in USART_CTL1 and SCEN, IREN bits in USART_CTL2 should be cleared in half-duplex communication mode. Only one wire is used in half-duplex mode. The TX and RX pins are connected together internally.
Page 427 GD32VW55x User Manual During USART transmission, if a parity error event is detected, the smartcard may NACK the current frame by pulling down the TX pin during the last 1 bit time of the stop bits. The USART can automatically resend data according to the protocol for SCRTNUM times. An interframe gap of 2.5 bits time will be inserted before the start of a resented frame.
Page 428 GD32VW55x User Manual programming the BL value. However, before the start of the block, the maximum value of BL (0xFF) may be programmed. The real value will be programmed after the reception of the third character. The total block length (including prologue, epilogue and information fields) equals BL+4. The end of the block is signaled to the software through the EBF flag and interrupt (when EBIE bit is set).
Page 429: Figure 16-16. Usart Receive Fifo Structure
GD32VW55x User Manual Figure 16-16. USART receive FIFO structure Rx Module Rx shift register Rx FIFO EN FIFO 0 Rx Buffer FIFO 1 FIFO 2 FIFO 3 If the software read receive data buffer in the routing of the RBNE interrupt, the RBNEIE bit should be reset at the beginning of the routing and set after all of the receive data is read out.
Page 430 GD32VW55x User Manual Interrupt event Event flag Enable Control bit Transmission complete TCIE Received data ready to be RBNE read RBNEIE Overrun error detected ORERR Receive FIFO full RFFINT RFFIE Idle line detected IDLEF IDLEIE Parity error flag PERR PERRIE Break detected flag in LIN LBDF LBDIE...
Page 431: Figure 16-17. Usart Interrupt Mapping Diagram
GD32VW55x User Manual Figure 16-17. USART interrupt mapping diagram RFFINT RFFIE IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE FERR NERR ORERR ERRIE LBDF LBDIE USART_INT AMIE RTIE EBIE WUIE TCIE TBEIE CTSF CTSIE...
Page 432 GD32VW55x User Manual 16.4. Register definition USART0 base address: 0x4000 4800 UART1 base address: 0x4000 4400 UART2 base address: 0x4001 1000 Control register 0 (USART_CTL0) 16.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EBIE RTIE...
Page 433 GD32VW55x User Manual OVSMOD Oversample mode 0: Oversampling by 16 1: Oversampling by 8 This bit must be kept cleared in LIN, IrDA and smartcard modes. This bit field cannot be written when the USART is enabled (UEN=1). AMIE ADDR match interrupt enable 0: ADDR match interrupt is disabled 1: ADDR match interrupt is enabled Mute mode enable...
Page 434 GD32VW55x User Manual 1: An interrupt will occur whenever the ORERR bit is set or the RBNE bit is set in USART_STAT. IDLEIE IDLE line detected interrupt enable 0: IDLE line detected interrupt disabled 1: An interrupt will occur whenever the IDLEF bit is set in USART_STAT. Transmitter enable 0: Transmitter is disabled 1: Transmitter is enabled...
Page 435 GD32VW55x User Manual received character (8-bit) is compared to the ADDR[7:0] value and AMF flag is set on matching. This bit field cannot be written when both reception (REN=1) and USART (UEN=1) are enabled. RTEN Receiver timeout enable 0: Receiver timeout function disabled 1: Receiver timeout function enabled This bit is reserved in UART1 and UART2.
Page 436 GD32VW55x User Manual This bit field cannot be written when the USART is enabled (UEN=1). CKEN CK pin enable 0: CK pin disabled 1: CK pin enabled This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved in UART1 and UART2. Clock polarity 0: Steady low value on CK pin outside transmission window in synchronous mode 1: Steady high value on CK pin outside transmission window in synchronous...
Page 437 GD32VW55x User Manual Reserved Must be kept at reset value. Control register 2 (USART_CTL2) 16.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved WUIE WUM[1:0] SCRTNUM[2:0] Reserved DDRE OVRD CTSIE CTSEN RTSEN DENT DENR...
Page 438 GD32VW55x User Manual Reserved Must be kept at reset value. Driver enable polarity mode 0: DE signal is active high 1: DE signal is active low This bit field cannot be written when the USART is enabled (UEN=1) Driver enable mode This bit is used to activate the external transceiver control, through the DE signal, which is output on the RTS pin.
Page 439 GD32VW55x User Manual 0: RTS hardware flow control disabled 1: RTS hardware flow control enabled, data can be requested only when there is space in the receive buffer This bit field cannot be written when the USART is enabled (UEN=1). DENT DMA enable for transmission 0: DMA mode is disabled for transmission...
Page 440 GD32VW55x User Manual Baud rate generator register (USART_BAUD) 16.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). This register cannot be written when the USART is enabled (UEN=1). Reserved BRR [15:4] BRR[3:0] Bits Fields Descriptions...
Page 441 GD32VW55x User Manual PSC[7:0] Prescaler value for dividing the system clock In IrDA Low-power mode, the division factor is the prescaler value. 00000000: Reserved - do not program this value 00000001: divides the source clock by 1 00000010: divides the source clock by 2 In IrDA normal mode, 00000001: can be set this value only In smartcard mode, the prescaler value for dividing the system clock is stored in...
Page 442 GD32VW55x User Manual 23:0 RT[23:0] Receiver timeout threshold These bits specify receiver timeout value in terms of number of baud clocks. In standard mode, the RTF flag is set if no new start bit is detected for more than the RT value after the last received character. In smartcard mode, the CWT and BWT are implemented by this value.
Page 443 GD32VW55x User Manual Status register (USART_STAT) 16.4.8. Address offset: 0x1C Reset value: 0x0000 00C0 This register has to be accessed by word (32-bit). Reserved Reserved CTSF LBDF RBNE IDLEF ORERR NERR FERR PERR Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. Receive enable acknowledge flag This bit, which is set/reset by hardware, reflects the receive enable state of the USART core logic.
Page 444 GD32VW55x User Manual register when wakeup on IDLEIE mode is selected. Send break flag 0: No break character is transmitted 1: Break character will be transmitted This bit indicates that a send break character was requested. Set by software, by writing 1 to the SBKCMD bit in the USART_CMD register. Cleared by hardware during the stop bit of break transmission.
Page 445 GD32VW55x User Manual 1: A change occurred on the nCTS status line. An interrupt will occur if the CTSIE bit is set in USART_CTL2 Set by hardware when the nCTS input toggles. Cleared by writing 1 to CTSC bit in USART_INTC register. LBDF LIN break detected flag 0: LIN Break is not detected...
Page 446 GD32VW55x User Manual ORERR Overrun error 0: No Ooverrun error is detected 1: Overrun error is detected. An interrupt will occur if the RBNEIE bit is set in USART_CTL0. In multibuffer communication, an interrupt will occur if the ERRIE bit is set in USART_CTL2. Set by hardware when the word in the receive shift register is ready to be transferred into the USART_RDATA register while the RBNE bit is set.
Page 447 GD32VW55x User Manual Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. Wakeup from deep-sleep mode clear Writing 1 to this bit clears the WUF bit in the USART_STAT register. This bit is reserved in UART1 and UART2. 19:18 Reserved Must be kept at reset value.
Page 448 GD32VW55x User Manual Writing 1 to this bit clears the PERR bit in the USART_STAT register. Receive data register (USART_RDATA) 16.4.10. Address offset: 0x24 Reset value: Undefined This register has to be accessed by word (32-bit). Reserved Reserved RDATA[8:0] Bits Fields Descriptions 31:9...
Page 449 GD32VW55x User Manual This register must be written only when TBE bit in USART_STAT register is set. USART coherence control register (USART_CHC) 16.4.12. Address offset: 0xC0 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved EPERR Reserved...
Page 450 GD32VW55x User Manual RFFINT Receive FIFO full interrupt flag 14:12 RFCNT[2:0] Receive FIFO counter number Receive FIFO full flag 0: Receive FIFO not full 1: Receive FIFO full Receive FIFO empty flag 0: Receive FIFO not empty 1: Receive FIFO empty RFFIE Receive FIFO full interrupt enable 0: Receive FIFO full interrupt disable...
Page 451: Figure 17-1. I2C Module Block Diagram
GD32VW55x User Manual Inter-integrated circuit interface (I2C) 17.1. Overview The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard mode, fast mode and fast mode plus as well as CRC calculation and checking, SMBus (system management bus), and PMBus (power management bus).
Page 452: Table 17-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32VW55x User Manual Figure 17-1. I2C module block diagram PEC register SDA Controller CRC Calculation / Analog Digital Check Noise Noise filter filter Wakeup on Receive address macth Data Register Shift Register Transmit SCL Controller Data Analog Register Digital Noise Noise filter filter...
Page 453: Figure 17-2. Data Validation
GD32VW55x User Manual with: : SCL low time : SCL high time HIGH : When the filters are enabled, represent the delays by the analog filter and digital filter. filters Analog filter delay is maximum 260ns. Digital filter delay is DNF[3:0] x tI2CCLK The period of PCLK clock tPCLK match the conditions as follows: ...
Page 454: Figure 17-3. Start And Stop Condition
GD32VW55x User Manual Figure 17-3. START and STOP condition START STOP Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device.
Page 455: Figure 17-5. I2C Communication Flow With 7-Bit Address (Master Transmit)
GD32VW55x User Manual Figure 17-5. I2C communication flow with 7-bit address (Master Transmit) Start Slave address …… W(0) DATA0 DATAN Stop data transfer (N+1 bytes) From master to slave From slave to master Figure 17-6. I2C communication flow with 7-bit address (Master Receive) In 10-bit addressing mode, the HEAD10R bit can configured to decide whether the complete address sequence must be executed, or only the header to be sent.
Page 456: Figure 17-9. Data Hold Time
GD32VW55x User Manual Noise filter 17.3.3. The noise filters must be configured before setting the I2CEN bit in I2C_CTL0 register if it is necessary. The analog noise filter is present on the SDA and SCL inputs by default. The analog filter requires the suppression of spikes with a pulse width up to 50ns in fast mode and fast mode plus.
Page 457: Figure 17-10. Data Setup Time
GD32VW55x User Manual Figure 17-10. Data setup time SU;DAT When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is t = SDADELY * t where t = (PSC+1) * t SDADELY I2CCLK I2CCLK SDADELY...
Page 458: Table 17-2. Data Setup Time And Data Hold Time
GD32VW55x User Manual Table 17-2. Data setup time and data hold time Standard Fast mode Fast mode SMBus Symbol Parameter mode plus Unit Data hold time HD;DAT Data valid time 3.45 0.45 VD;DAT Data setup time SU;DAT Rising time of 1000 1000 SCL and SDA...
Page 459: Figure 17-11. Data Transmission
GD32VW55x User Manual Figure 17-11. Data transmission SCL Stretch Shift register write data1 write data2 data0 data1 data2 I2C_TDATA Data Reception When receiving data, the SDA input fills the shift register. After the 8th SCL pulse, the complete data byte is received. If RBNE=0 (I2C_RDATA register is empty), the data in the shift register is moved into I2C_RDATA register.
Page 460: Table 17-3. Communication Modes To Be Shut Down
GD32VW55x User Manual Table 17-3. Communication modes to be shut down Working mode Action Master mode NACK, STOP and RESTART generation Slave receiver mode ACK control SMBus mode PEC generation/checking The byte counter is always used in master mode. It is disabled in slave mode by default, but it can be enabled by software by setting the SBCTL (slave byte control) bit in the I2C_CTL0 register.
Page 461 GD32VW55x User Manual I2C slave mode 17.3.7. Initialization When works in slave mode, at least one slave address should be enabled. Slave address 1 can be programmed in I2C_SADDR0 register and slave address 2 can be programmed in I2C_SADDR1 register. ADDRESSEN in I2C_SADDR0 register and ADDRESS2EN in I2C_SADDR1 register should be set when the corresponding address is used.
Page 462 GD32VW55x User Manual  In slave transmitting mode, the data should be written in the I2C_TDATA register before the first SCL pulse corresponding to its transfer occurs. Or else the OUERR bit in the I2C_STAT register will be set, if the ERRIE bit is set, an interrupt will be generated. When the STPDET bit is set and the first data transmission starts, OUERR bit in the I2C_STAT register will also be set.
Page 463: Figure 17-13. I2C Initialization In Slave Mode
GD32VW55x User Manual Figure 17-13. I2C initialization in slave mode START I2CEN=0 Configure DNF[3:0] in I2C_CTL0 Configure PSC[3:0], SDADELY[3:0], SCLDELY[3:0] in I2C_TIMING Configure SS in I2C_CTL0 I2CEN=1 Clear ADDRESSEN in I2C_SADDR0 Clear ADDRESS2EN in I2C_SADDR1 Configure ADDRESS[9:0], ADDFORMAT and ADDRESSEN in I2C_SADDR0, ADDRESS2[7:1], ADDMSK2[2:0] and ADDRESS2EN in I2C_SADDR1, ADDM[6:0] in I2C_CTL2...
Page 464: Figure 17-14. Programming Model For Slave Transmitting When Ss=0
GD32VW55x User Manual In this case, the data in I2C_TDATA register can not be flushed in ADDSEND interrupt service routine. So the first data byte to be sent must be programmed in the I2C_TDATA register previously.  This data can be the data written in the last TI event of the last transfer. ...
Page 465: Figure 17-15. Programming Model For Slave Transmitting When Ss=1
GD32VW55x User Manual Figure 17-15. Programming model for slave transmitting when SS=1 I2C Line State Hardware Action Software Flow I2C initialization IDLE Set TBE Write DATA(1) to I2C_TDATA Master generates START condition Master sends Address read READDR and TR in Set ADDSEND Slave sends Acknowledge I2C_STAT, clear ADDSEND...
Page 466: Figure 17-16. Programming Model For Slave Receiving
GD32VW55x User Manual Figure 17-16. Programming model for slave receiving I2C Line State Hardware Action Software Flow IDLE Master generates START Software initialization condition Master sends Address Slave sends Acknowledge read READDR and TR in Set ADDSEND I2C_STAT, clear ADDSEND SCL stretched by slave (only when SS=0) Master sends DATA(1)
Page 467: Figure 17-17. I2C Initialization In Master Mode
GD32VW55x User Manual (PSC+1) x t I2CCLK The t depends on the SCL falling slope, delay by input analog and digital noise filter and SYNC1 SCL synchronization with I2CCLK clock, which generally 2 to 3 I2CCLK periods. The t SYNC2 depends on the SCL rising slope, delay by input analog and digital noise filter and SCL synchronization with I2CCLK clock, which generally 2 to 3 I2CCLK periods.
Page 468: Figure 17-18. Programming Model For Master Transmitting (N<=255)
GD32VW55x User Manual transmission. If the TIE bit in I2C_CTL0 register is set, an interrupt will be generated. The bytes to be transferred is programmed in BYTENUM[7:0] in I2C_CTL0 register. If the bytes to be transferred is greater than 255, RELOAD bit in I2C_CTL0 register must be set to enable the reload mode.
Page 469: Figure 17-19. Programming Model For Master Transmitting (N>255)
GD32VW55x User Manual Figure 17-19. Programming model for master transmitting (N>255) Software Flow I2C Line State Hardware Action Software initialization RELOAD =1 IDLE BYTENUM[7:0]=0xFF Master generates START N=N-255 condition Set START Master sends Address Slave sends Acknowledge Write DATA(1) to Set TI I2C_TDATA Wait for ACK from slave...
Page 470: Figure 17-20. Programming Model For Master Receiving (N<=255)
GD32VW55x User Manual Figure 17-20. Programming model for master receiving (N<=255) I2C Line State Hardware Software Flow Action Software initialization AUTOEND=0 BYTENUM[7:0]=N IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) ……（Data transmission）...
Page 471: Figure 17-21. Programming Model For Master Receiving (N>255)
GD32VW55x User Manual Figure 17-21. Programming model for master receiving (N>255) Hardware I2C Line State Software Flow Action Software initialization RELOAD =1 BYTENUM[7:0]=0xFF N=N-255 IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) ……（Data transmission）...
Page 472 GD32VW55x User Manual specifications. I2C devices that can be accessed through one of the SMBus protocols are compatible with the SMBus specifications. I2C devices that do not adhere to these protocols cannot be accessed by standard methods as defined in the SMBus and Advanced Configuration and Power Management Interface (abbreviated to ACPI) specifications.
Page 473: Table 17-5. Smbus With Pec Configuration
GD32VW55x User Manual In order to enable the t , the BUSTOA[11:0] must be programmed with the timer to check TIMEOUT the t parameter. To detect SCL low level timeout, the TOIDLE bit must be configured to TIMEOUT "0". Then set TOEN in the I2C_TIMEOUT register to enable the timer. If the low level time of SCL is greater than (BUSTOA + 1) x 2048 x t , the TIMEOUT flag is set in the I2C_STAT I2CCLK...
Page 474 GD32VW55x User Manual the same time. Only the device(s) which pulled SMBALERT# low will acknowledge the Alert Response Address. When SMBHAEN is 0, it is configured as a slave device, the SMBA pin is pulled low by setting the SMBALTEN bit in the I2C_CTL0 register. Meanwhile the Alert Response Address is enabled.
Page 475: Figure 17-22. Smbus Master Transmitter And Slave Receiver Communication Flow
GD32VW55x User Manual BYTENUM=0x1 and PECTRANS bit is set at the same time, the contents of the I2C_PEC register are automatically transferred. If the automatic end mode is selected (AUTOEND=1), the SMBus master automatically sends the STOP condition after the PEC byte. If the automatic end mode is not selected (AUTOEND=0), the SMBus master can send a RESTART condition after the PEC.
Page 476: Figure 17-23. Smbus Master Receiver And Slave Transmitter Communication Flow
GD32VW55x User Manual master is greater than BYTENUM-1, the total number of TI interrupts will be BYTENUM-1, and the contents of the I2C_PEC register will be transmitted automatically. Note: After the RELOAD bit is set, the PECTRANS cannot be changed. Figure 17-23.
Page 477: Table 17-6. I2C Error Flags
GD32VW55x User Manual I2C error and interrupts 17.3.13. The I2C error flags are listed in Table 17-6. I2C error flags. Table 17-6. I2C error flags I2C Error Name Description BERR Bus error LOSTARB Arbitration lost OUERR Overrun/Underrun flag PECERR CRC value doesn’t match TIMEOUT Bus timeout in SMBus mode SMBALT...
Page 478 GD32VW55x User Manual 17.4. Register definition I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 Control register 0 (I2C_CTL0) 17.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by word (32-bit) SMBALT SMBDAE SMBHAE Reserved PECEN GCEN WUEN...
Page 479 GD32VW55x User Manual 1: Slave will response to a General Call WUEN Wakeup from Deep-sleep mode enable 0: Wakeup from Deep-sleep mode disable. 1: Wakeup from Deep-sleep mode enable. Note: WUEN can be set only when DNF[3:0] = 0000. This bit is reserved in I2C1. Whether to stretch SCL low when data is not ready in slave mode.
Page 480 GD32VW55x User Manual 0: Transfer complete interrupt is disabled 1: Transfer complete interrupt is enabled STPDETIE Stop detection interrupt enable 0: Stop detection (STPDET) interrupt is disabled 1: Stop detection (STPDET) interrupt is enabled NACKIE Not acknowledge received interrupt enable 0: Not acknowledge (NACK) received interrupt is disabled 1: Not acknowledge (NACK) received interrupt is enabled ADDMIE...
Page 481 GD32VW55x User Manual Cleared by hardware in the following cases: When PEC byte is transferred or ADDSEND bit is set or STOP condition is detected or I2CEN=0. 0: Don’t transfer PEC value 1: Transfer PEC Note: This bit has no effect when RELOAD=1, or SBCTL=0 in slave mode. AUTOEND Automatic end mode in master mode 0: TC bit is set when the transfer of BYTENUM[7:0] bytes is completed.
Page 482 GD32VW55x User Manual 1: START will be sent HEAD10R 10-bit address header executes read direction only in master receive mode 0: The 10 bit master receive address sequence is START + header of 10-bit address (write) + slave address byte 2 + RESTART + header of 10-bit address (read). 1: The 10 bit master receive address sequence is RESTART + header of 10-bit address (read).
Page 483 GD32VW55x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. ADDRESSEN I2C address enable 0: I2C address disable. 1: I2C address enable. 14:11 Reserved Must be kept at reset value. ADDFORMAT Address mode for the I2C slave 0: 7-bit address 1: 10-bit address Note: When ADDRESSEN is set, this bit should not be written.
Page 484 GD32VW55x User Manual Defines which bits of ADDRESS2[7:1] are compared with an incoming address byte, and which bits are masked (don’t care). 000: No mask, all the bits must be compared. n(001~110): ADDRESS2[n:0] is masked. Only ADDRESS2[7:n+1] are compared. 111: ADDRESS2[7:1] are masked. All 7-bit received addresses are acknowledged except the reserved address (0b0000xxx and 0b1111xxx).
Page 485 GD32VW55x User Manual mode and in slave mode when SS = 0. = SDADELY x t SDADELY 15:8 SCLH[7:0] SCL high period SCL high period can be generated by configuring these bits. = (SCLH+1) x t SCLH Note: These bits can only be used in master mode. SCLL[7:0] SCL low period SCL low period can be generated by configuring these bits.
Page 486 GD32VW55x User Manual 1: SCL timeout detection is enabled 14:13 Reserved Must be kept at reset value. TOIDLE Idle clock timeout detection 0: BUSTOA is used to detect SCL low timeout 1: BUSTOA is used to detect both SCL and SDA high timeout when the bus is idle Note: This bit can be written only when TOEN =0.
Page 487 GD32VW55x User Manual 1: I2C communication active. Reserved Must be kept at reset value. SMBALT SMBus Alert When SMBHAEN=1, SMBALTEN=1, and a SMBALERT event (falling edge) is detected on SMBA pin, this bit will be set by hardware. It is cleared by software by setting the SMBALTC bit.
Page 488 GD32VW55x User Manual zero value. 0: When RELOAD=1, transfer of BYTENUM[7:0] bytes is not completed 1: When RELOAD=1, transfer of BYTENUM[7:0] bytes is completed Transfer complete in master mode This bit is set by hardware when RELOAD=0, AUTOEND=0 and data of BYTENUM[7:0] bytes have been transferred.
Page 489 GD32VW55x User Manual the next data to be sent is written in the I2C_TDATA register. This bit can be set by software in order to empty the I2C_TDATA register. 0: I2C_TDATA is not empty 1: I2C_TDATA is empty Status clear register (I2C_STATC) 17.4.8.
Page 490 GD32VW55x User Manual Software can clear the ADDSEND bit of I2C_STAT by write 1 to this bit Reserved Must be kept at reset value. PEC register (I2C_PEC) 17.4.9. Address offset: 0x20 Reset value: 0x0000 0000 This register can be accessed by word (32-bit) Reserved Reserved PECV[7:0]...
Page 491 GD32VW55x User Manual This register can be accessed by word (32-bit) Reserved Reserved TDATA [7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TDATA[7:0] Transmit data value Control register 2 (I2C_CTL2) 17.4.12. Address offset: 0x90 Reset value: 0x0000 0000 This register can be accessed by word (32-bit) Reserved ADDM[6:0]...
Page 492: Figure 18-1. Block Diagram Of Spi
GD32VW55x User Manual Serial peripheral interface (SPI) 18.1. Overview The SPI module can communicate with external devices using the SPI protocol. The serial peripheral interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode. Both full-duplex and simplex communication modes are supported, with hardware CRC calculation and checking.
Page 493: Table 18-1. Spi Signal Description
GD32VW55x User Manual SPI signal description 18.3.2. Table 18-1. SPI signal description Pin name Direction Description Master: SPI clock output Slave: SPI clock input Master: Data reception line Slave: Data transmission line MISO Master with bidirectional mode: Not used Slave with bidirectional mode: Data transmission and reception line.
Page 494: Figure 18-2. Spi Timing Diagram In Normal Mode
GD32VW55x User Manual Figure 18-2. SPI timing diagram in normal mode sample SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) SCK (CKPH=1 CKPL=1) MOSI LF=1 FF16=0 MISO In normal mode, the length of data is configured by the FF16 bit in the SPI_CTL0 register. Data length is 16 bits if FF16=1, otherwise is 8 bits.
Page 495: Table 18-3. Nss Function In Master Mode
GD32VW55x User Manual fault flag CONFERR. If the application wants to use NSS line to control the SPI slave, NSS should be configured to hardware output mode (SWNSSEN=0, NSSDRV=1). NSS goes low after SPI is enabled. The application may also use a general purpose IO as NSS pin to realize more flexible NSS. Table 18-3.
Page 496 GD32VW55x User Manual Mode Description Register configuration Data pin usage MSTMOD = 1 Master reception with RO = 1 MOSI: Not used unidirectional connection BDEN = 0 MISO: Reception BDOEN: Don’t care MSTMOD = 1 Master transmission with RO = 0 MOSI: Transmission bidirectional connection BDEN = 1...
Page 497: Figure 18-3. A Typical Full-Duplex Connection
GD32VW55x User Manual Figure 18-3. A typical full-duplex connection Slave Master MISO MISO MOSI MOSI Figure 18-4. A typical simplex connection (Master: Receive, Slave: Transmit) Slave Master MISO MISO MOSI MOSI Figure 18-5. A typical simplex connection (Master: Transmit only, Slave: Receive) Master Slave MISO...
Page 498 GD32VW55x User Manual SPI initialization sequence Before transmitting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise, ignore this step.
Page 499: Figure 18-7. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32VW55x User Manual frame, while in full-duplex master mode (MFD), hardware only receives the next data frame when the transmit buffer is not empty. SPI operation sequence in different modes (Not TI mode) In full-duplex mode, either MFD or SFD, the RBNE and TBE flags should be monitored and then follow the sequences described above.
Page 500: Figure 18-9. Timing Diagram Of Ti Slave Mode
GD32VW55x User Manual In master TI mode, SPI can perform continuous or non-continuous transfer. If the master writes SPI_DATA register fast enough, the transfer is continuous, otherwise non-continuous. In non-continuous transfer, there is an extra header clock cycle before each byte. While in continuous transfer, the extra header clock cycle only exists before the first byte and the following bytes’...
Page 501 GD32VW55x User Manual MRU MRB After getting the second last RBNE flag, read out this data and delay for a SCK clock time and then, disable the SPI by clearing SPIEN bit. Wait until the last RBNE flag is set and read out the last data.
Page 502 GD32VW55x User Manual enabled, the software does not need to set the CRCNT bit, and the hardware will handle the CRC transmission and verification automatically. Note: When SPI is in slave mode and CRC function is enable, the CRC calculator is sensitive to input SCK clock whether SPI is enable or not.
Page 503: Table 18-5. Spi Interrupt Requests
GD32VW55x User Manual incorrect NSS behavior, for example: toggles at the middle bit of a byte.  CRC error (CRCERR) When the CRCEN bit is set, the CRC calculation result of the received data in the SPI_RCRC register is compared with the received CRC value after the last data, the CRCERR is set when they are different.
Page 504 GD32VW55x User Manual 18.4. Register definition SPI base address: 0x4001 3000 Control register 0 (SPI_CTL0) 18.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved SWNSS BDEN BDOEN CRCEN CRCNT FF16 SWNSS SPIEN...
Page 505 GD32VW55x User Manual 1: 16-bit data frame format Receive only mode When BDEN is cleared, this bit determines the direction of transfer. 0: Full-duplex mode 1: Receive-only mode SWNSSEN NSS software mode enable 0: NSS hardware mode. The NSS level depends on NSS pin. 1: NSS software mode.
Page 506 GD32VW55x User Manual Control register 1 (SPI_CTL1) 18.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved TBEIE RBNEIE ERRIE TMOD Reserved NSSDRV DMATEN DMAREN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 507 GD32VW55x User Manual DMAREN Receive buffer DMA enable 0: Receive buffer DMA is disabled. 1: Receive buffer DMA is enabled, when the RBNE bit in SPI_STAT is set, there will be a DMA request on corresponding DMA channel. Status register (SPI_STAT) 18.4.3.
Page 508 GD32VW55x User Manual 0: The SPI_RCRC value is equal to the received CRC data at last. 1: The SPI_RCRC value is not equal to the received CRC data at last. This bit is set by hardware and cleared by writing 0. Reserved Must be kept at reset value.
Page 509 GD32VW55x User Manual Reserved CRCPOLY[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CRCPOLY[15:0] CRC polynomial value These bits contain the CRC polynomial and they are used for CRC calculation. The default value is 0007h. RX CRC register (SPI_RCRC) 18.4.6.
Page 510 GD32VW55x User Manual TX CRC register (SPI_TCRC) 18.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved TCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 TCRC[15:0] TX CRC value When the CRCEN bit of SPI_CTL0 is set, the hardware computes the CRC value of the...
Page 511: Table 19-1. Qspi Signal Description
GD32VW55x User Manual Quad-SPI interface (QSPI) 19.1. Overview The QSPI is a specialized interface that communicate with flash memories. This interface supports single, dual or quad SPI FLASH. It can operate in normal mode, read polling mode and memory map mode. 19.2.
Page 512: Figure 19-1 Qspi Diagram
GD32VW55x User Manual Pin name Direction Description function dual mode: connect HOLD pin of flash, control “hold” function quad mode: data intput or output Figure 19-1 QSPI diagramshows the block diagram of the QSPI unit. Figure 19-1 QSPI diagram Register/mode configure RX FIFO TX FIFO...
Page 513: Figure 19-2 Qspi Command Format
GD32VW55x User Manual Figure 19-2 QSPI command format Alternate Dummy Data Instruction Address The commands and the corresponding configuration are shown in Table 19-2. QSPI command description. Table 19-2. QSPI command description Send Command Configuration Note information 8-bit QSPI_TCFG register defines the instruction instruction instruction and signal line mode...
Page 514: Table 19-3. Qspi Singnal Line Modes
GD32VW55x User Manual QSPI signal line modes 19.3.3. Each of the instruction, address, alternate-byte, or data phase can be configured separately into signal line modes by setting IMOD / ADDRMOD / ALTEMOD / DATAMOD. Table 19-3. QSPI singnal line modes Signal line modes Single line mode Dual line mode...
Page 515 GD32VW55x User Manual space (range from 0x9000 0000 to 0x97FF FFFF) and can be accessed as an internal memory. Normal mode 19.4.1. The write operation in normal mode is selected by configuring the FMOD[1:0] in QSPI_TCFG register to “00”. The data to be transmitted is written into QSPI_DATA. The read operation in normal mode is selected by setting the FMOD[1:0] in QSPI_TCFG register to “01”, and the data to be received is read from QSPI_DATA.
Page 516: Table 19-4. Ahb Write Access Mode And Number Of Bytes Add To Fifo
GD32VW55x User Manual Table 19-4. AHB write access mode and number of bytes add to FIFO AHB write access mode Number of bytes add to FIFO 32-bit 4 bytes 16-bit 2 bytes 8-bit 1 byte Note: When the AHB write access mode is 8-bit or 16-bit, the least significant bytes are valid in QSPI_DATA register.
Page 517 GD32VW55x User Manual Memory map mode 19.4.3. The memory map mode can be selected by configuring the FMOD[1:0] to “11”. In memory map mode, the external flash memory is considered as internal memory, no more than 128MB can be addressed even if the external memory is larger. The memory map mode can not access the address no more than 128MB but outside the range which is specified by FMSZ.
Page 518: Table 19-5. Terr And Ahb Error Conditions
GD32VW55x User Manual beneficial to sample data later because of the external signal delays. The sample edge can be shifted half one of SCK cycle using SSAMPLE bit. The DMA request is enabled by setting the DMAEN bit in QSPI_STAT register. The FIFO threshold level is configured in FTL[3:0] bits in QSPI_CTL register.
Page 519 GD32VW55x User Manual...
Page 520 GD32VW55x User Manual 19.8. Register definition QSPI base address: 0x4002 5800 Control register (QSPI_CTL) 19.8.1. Address offset: 0x00 Reset value: 0x0000 0010 This register has to be accessed by word (32-bit). PSC[7:0] RPMM RPMS Reserved TMOUTIE RPMFIE FTIE TCIE TERRIE TMOUTE SCKDVALUE[3:0] FTL[3:0]...
Page 521 GD32VW55x User Manual TMOUTIE Timeout interrupt enable 0: disable timeout interrupt 1: enable timeout interrupt RPMFIE Read polling mode match interrupt enable 0: disable read polling mode match interrupt 1: enable read polling mode match interrupt FTIE FIFO threshold interrupt enable 0: disable FIFO threshold interrupt 1: enable FIFO threshold interrupt TCIE...
Page 522 GD32VW55x User Manual allow the data to be sampled later. 0: No delay 1: 1/2 cycle delay 2: 1 cycle delay 3: Reserved These bits can be modified only when BUSY = 0. TMOUTEN Timeout counter enable In memory map mode (FMOD = 11). When setting this bit, the chip select output (CSN) will be high if there is no access after a certain amount of time which specified by TMOUTCYC[15:0].
Page 523 GD32VW55x User Manual Reserved CSHC[2:0] Reserved CKMOD Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. 20:16 FMSZ[4:0] Flash memory size [FMSZ+1] These bits defines the size of external memory. And the number of bytes is 2 FMSZ+1 is the number of address bits in the flash memory. In normal mode, the flash memory capacity can be up to 4GB, while it is limited to 128MB in memory map mode.
Page 524 GD32VW55x User Manual Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 FL[4:0] FIFO level These bits is used to configure the number of valid bytes which are being stored in the FIFO in normal mode. In memory map mode and in read polling mode, FL is 0. Reserved Must be kept at reset value.
Page 525 GD32VW55x User Manual Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. TMOUTC Clear timeout flag Writing 1 to this bit clears the TMOUT bit in the QSPI_STAT register. RPMFC Clear read polling mode match flag Writing 1 to this bit clears the RPMF bit in the QSPI_STAT register. Reserved Must be kept at reset value.
Page 526 GD32VW55x User Manual 0xFFFF FFFF: undefined length, all bytes defined by FMSZ[4:0] in QSPI_DCFG register until the end of flash memorywill be transferred. If FMSZ[4:0] is 0x1F, it will continue reading indefinitely. When in memory map mode, these bits have no effect. These bits can be modified only when BUSY = 0.
Page 527 GD32VW55x User Manual Reserved Must be kept at reset value. 22:18 DUMYC[4:0] Number of dummy cycles These bits define the duration of the dummy phase. These bits can be modified only when BUSY = 0. 17:16 ALTESZ[1:0] Alternate bytes size 00: 8-bit alternate byte 01: 16-bit alternate bytes 10: 24-bit alternate bytes...
Page 528 GD32VW55x User Manual Address register (QSPI_ADDR) 19.8.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). ADDR[31:16] ADDR[15:0] Bits Fields Descriptions 31:0 ADDR[31:0] Address to be send to the external Flash memory When BUSY=0 or in memory mapped mode, writing values to these bits will be ignored.
Page 529 GD32VW55x User Manual DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] Data that will be interacting with flash memory. In write operation of normal mode, the data written to this register will be stored in the FIFO before sending to the flash memory. If the FIFO is full, a write operation will be stopped and wait until the FIFO has enough space.
Page 530 GD32VW55x User Manual MATCH[31:16] MATCH[15:0] Bits Fields Descriptions 31:0 MATCH[31:0] Status match in read polling mode Expected value to be compared with the value in the QSPI_STATMK register to get a match. These bits can be modified only when BUSY = 0. Interval register (QSPI_INTERVAL) 19.8.12.
Page 531 GD32VW55x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 TMOUTCYC[15:0] Timeout cycle When the FIFO is full in memory map mode, these bits indicate how many SCK cycles the QSPI waits for next access. In this duration, CSN keeps low. These bits can be modified only when BUSY = 0.
Page 532 GD32VW55x User Manual Cryptographic Acceleration Unit (CAU) 20.1. Overview The cryptographic acceleration unit (CAU) is used to encipher and decipher data with DES, Triple-DES or AES (128, 192, or 256) algorithms. It is fully compliant implementation of the following standards: ...
Page 533: Figure 20-1. Datam No Swapping And Half-Word Swapping
GD32VW55x User Manual and OFB modes.  8*32-bit input and output FIFO.  Multiple data types are supported, including No swapping, Half-word swapping Byte swapping and Bit swapping.  Data can be transferred by DMA, CPU during interrupts, or without both of them. 20.3.
Page 534: Figure 20-2. Datam Byte Swapping And Bit Swapping
GD32VW55x User Manual Figure 20-2. DATAM Byte swapping and Bit swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Byte swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Bit swapping Initialization vectors 20.3.2. The initialization vectors are used in CBC, CTR, GCM, GMAC, CCM, CFB and OFB modes to XOR with data blocks.
Page 535 GD32VW55x User Manual CAU_ CAU_ CAU_ CAU_ CAU_ CAU_ CAU_ CAU_ CAU_GCMCC CAU_GCMCT STAT0 DMAEN INTEN INTF STAT1 KEY0...3 IV0...1 MCTXS0...7 XS0...7 AHB BUS CAU_DI CAU_DO Input FIFO Output FIFO Config 8*32 8*32 Data swapping Data swapping Cryptographic acceleration(DES / TDES / AES) DES / TDES cryptographic acceleration processor 20.4.1.
Page 536: Figure 20-4. Des / Tdes Ecb Encryption
GD32VW55x User Manual DES / TDES ECB encryption The 64-bit input plaintext is first obtained after data swapping according to the data type. When the TDES algorithm is configured, the input data block is read in the DEA and encrypted using KEY1.
Page 537: Figure 20-5. Des / Tdes Ecb Decryption
GD32VW55x User Manual Figure 20-5. DES / TDES ECB decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt SWAP CAU_DO Plaintext DES / TDES CBC encryption The input data of the DEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors.
Page 538: Figure 20-6. Des / Tdes Cbc Encryption
GD32VW55x User Manual Figure 20-6. DES / TDES CBC encryption CAU_DI Plaintext DATAM SWAP CAU_IV0(H/L) KEY1 DEA, encrypt KEY2 DEA, decrypt KEY3 DEA, encrypt SWAP CAU_DO Ciphertext DES / TDES CBC decryption In DES / TDES CBC decryption, when the TDES algorithm is configured, the first ciphertext block is used directly after data swapping according to the data type, it is read in the DEA and decrypted using KEY3.
Page 539: Figure 20-7. Des / Tdes Cbc Decryption
GD32VW55x User Manual Figure 20-7. DES / TDES CBC decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt CAU_IV0(H/L) SWAP CAU_DO Plaintext AES cryptographic acceleration processor 20.4.2. The AES cryptographic acceleration processor consists of three components, including the AES algorithm (AEA), multiple keys and the initialization vectors or Nonce.
Page 540: Figure 20-8. Aes Ecb Encryption
GD32VW55x User Manual Figure 20-8. AES ECB encryption CAU_DI Plaintext DATAM SWAP CAU_KEY0...3 AEA, encrypt SWAP CAU_DO Ciphertext AES-ECB mode decryption First of all, the key derivation must be completed to prepare the decryption keys, the input key of the key schedule is the same to that used in encryption. The last round key obtained from the above operation is then used as the first round key in the decryption.
Page 541: Figure 20-10. Aes Cbc Encryption
GD32VW55x User Manual AES-CBC mode encryption The input data of the AEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors. The XOR result of the swapped plaintext data block and the 128-bit initialization vector CAU_IV0..1 is read in the AEA and encrypted using the 128-, 192-, 256-bit key.
Page 542: Figure 20-11. Aes Cbc Decryption
GD32VW55x User Manual plaintext is also obtained after data swapping according to the data type. The procedure of AES CBC mode decryption is illustrated in Figure 20-11. AES CBC decryption. Figure 20-11. AES CBC decryption CAU_DI Ciphertext DATAM SWAP CAU_KEY0..3 AEA, decrypt CAU_IV0..1(H/L) SWAP...
Page 543 GD32VW55x User Manual Figure 20-13. AES CTR encryption / decryption Plaintext/ CAU_DI Ciphertext DATAM SWAP CAU_IV0..1(H/L) AEA, encrypt/ CAU_KEY0..3 decryp SWAP Ciphertext CAU_DO Plaintext AES-GCM mode The AES Galois / counter mode (GCM) can be used to encrypt or authenticate message, then ciphertext and tag can be obtained.
Page 544 GD32VW55x User Manual Repeat (h) until all AAD data are supplied, wait until BUSY bit is cleared. 3. GCM encryption / decryption phase This phase must be performed after GCM AAD phase. In this phase, the message is authenticated and encrypted / decrypted. Configure GCM_CCMPH[1:0] bits to ‘10’.
Page 545 GD32VW55x User Manual 1. CCM prepare phase In this phase, B0 packet (the first packet) is programmed into the CAU_DI register. CAU_DO never contain data in this phase. (a) Clear the CAUEN bit to make sure CAU is disabled. (b) Configure the ALGM[3:0] bits to ‘1001’. (c) Configure GCM_CCMPH[1:0] bits to ‘00’.
Page 546 GD32VW55x User Manual (q) Wait until the ONE flag is set to 1, and then read CAU_DO 4 times. The output corresponds to the authentication tag. (r) Disable the CAU AES-CFB mode The Cipher Feedback (CFB) mode is a confidentiality mode that features the feedback of successive ciphertext segments into the input blocks of the forward cipher to generate output blocks that are exclusive-ORed with the plaintext to produce the ciphertext, and the decryption process is similar to the encryption described before.
Page 547 GD32VW55x User Manual Decryption 1. Disable the CAU by resetting the CAUEN bit in the CAU_CTL register. 2. Select and configure the key length with the KEYM bits in the CAU_CTL register if AES algorithm is chosen. 3. Configure the CAU_KEY0..3(H / L) registers according to the algorithm. 4.
Page 548 GD32VW55x User Manual CAU, the interrupt is used to indicate the situation of the input and output FIFO. Any of input and output FIFO interrupt can be enabled or disabled by configuring the Interrupt Enable register CAU_INTEN. Value 1 of the register enable the interrupts. Input FIFO interrupt The input FIFO interrupt is asserted when the number of words in the input FIFO is less than four words, then ISTA is asserted.
Page 549 GD32VW55x User Manual When data transfer is done by CPU access to CAU_DI and CAU_DO: 1. When the data transfer is done by CPU access, then wait for the fourth read of the CAU_DO register and before the next CAU_DI write access so that the message is suspended at the end of a block processing.
Page 550 GD32VW55x User Manual 20.9. Register definition CAU secure access base address: 0x4C06 0000 Control register (CAU_CTL) 20.9.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ALGM[3] Reserved GCM_CCMPH[1:0] CAUEN FFLUSH Reserved KEYM[1:0] DATAM[1:0] ALGM[2:0]...
Page 551 GD32VW55x User Manual 11: never use DATAM[1:0] Data swapping type mode configuration, must be configured when BUSY = 0 00: No swapping 01: Half-word swapping 10: Byte swapping 11: Bit swapping ALGM[2:0] Encryption / decryption algorithm mode bit 0 to bit 2 These bits and bit 19 of CAU_CTL must be configured when BUSY = 0 0000: TDES-ECB with CAU_KEY1, 2, 3.
Page 552 GD32VW55x User Manual This register has to be accessed by word (32-bit). Reserved Reserved BUSY Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. BUSY Busy bit 0: No processing. This is because: - CAU is disabled by CAUEN = 0 or the processing has been completed. - No enough data or no enough space in the input / output FIFO to perform a data block 1: CAU is processing data or key derivation.
Page 553 GD32VW55x User Manual DI[31:16] DI[15:0] Bits Fields Descriptions 31:0 DI[31:0] Data input Write these bits will write data to IN FIFO, read these bits will return IN FIFO value if CAUEN is 0, or it will return an undefined value Data output register (CAU_DO) 20.9.4.
Page 554 GD32VW55x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. DMAOEN DMA output enable 0: DMA for OUT FIFO data is disabled 1: DMA for OUT FIFO data is enabled DMAIEN DMA input enable 0: DMA for IN FIFO data is disabled 1: DMA for IN FIFO data is enabled Interrupt enable register (CAU_INTEN) 20.9.6.
Page 555 GD32VW55x User Manual Reserved OSTA ISTA Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. OSTA OUT FIFO interrupt status 0: OUT FIFO interrupt status not pending 1: OUT FIFO interrupt status pending ISTA IN FIFO interrupt status 0: IN FIFO interrupt not pending 1: IN FIFO interrupt flag pending Interrupt flag register (CAU_INTF)
Page 556 GD32VW55x User Manual In TDES mode, CAU_KEY1, CAU_KEY2 and CAU_KEY3 are used. In AES-128 mode, KEY2H[31:0] || KEY2L[31:0] is used as AES_KEY[0:63], and KEY3H[31:0] || KEY3L[31:0] is used as AES_KEY[64:127]. In AES-192 mode, KEY1H[31:0] || KEY1L[31:0] is used as AES_KEY[0:63], KEY2H[31:0] || KEY2L[31:0] is used as AES_KEY[64:127], and KEY3H[31:0] || KEY3L[31:0] is used as AES_KEY[128:191].
Page 557 GD32VW55x User Manual CAU_KEY1L Address offset: 0x2C Reset value: 0x0000 0000 KEY1L[31:16] KEY1L[15:0] CAU_KEY2H Address offset: 0x30 Reset value: 0x0000 0000 KEY2H[31:16] KEY2H[15:0] CAU_KEY2L Address offset: 0x34 Reset value: 0x0000 0000 KEY2L[31:16] KEY2L[15:0] CAU_KEY3H Address offset: 0x38 Reset value: 0x0000 0000 KEY3H[31:16] KEY3H[15:0]...
Page 558 GD32VW55x User Manual CAU_KEY3L Address offset: 0x3C Reset value: 0x0000 0000 KEY3L[31:16] KEY3L[15:0] Bits Fields Descriptions KEY0...3(H / L) The key for DES, TDES, AES 31:0 Initial vector registers (CAU_IV0…1(H / L)) 20.9.10. Address offset: 0x40 to 0x4C Reset value: 0x0000 0000 This registers have to be accessed by word (32-bit), and all of them must be written when BUSY is 0.
Page 559 GD32VW55x User Manual IV0L[15:0] CAU_IV1H Address offset: 0x48 Reset value: 0x0000 0000 IV1H[31:16] IV1H[15:0] CAU_IV1L Address offset: 0x4C Reset value: 0x0000 0000 IV1L[31:16] IV1L[15:0] Bits Fields Descriptions IV0...1(H / L) The initialization vector for DES, TDES, AES 31:0 GCM or CCM mode context switch register x (CAU_GCMCCMCTXSx) (x 20.9.11.
Page 560 GD32VW55x User Manual 31:0 CTXx[31:0] The internal status of the CAU core. Read and save the register data when a high- priority task is coming to be processed, and restore the saved data back to the registers to resume the suspended processing. Note: These registers are used only when GCM, GMAC, or CCM mode is selected.
Page 561: Figure 21-1. Datam No Swapping And Half-Word Swapping
GD32VW55x User Manual Hash Acceleration Unit (HAU) 21.1. Overview The hash acceleration unit is used for information security. The secure hash algorithm (SHA- 1, SHA-224, SHA-256), the message-digest algorithm (MD5) and the keyed-hash message authentication code (HMAC) algorithm are supported for various applications. The digest will be computed and the length is 160 / 224 / 256 / 128 bits for a message up to (2 - 1) bits computed by SHA-1, SHA-224, SHA-256 and MD5 algorithms respectively.
Page 562: Figure 21-2. Datam Byte Swapping And Bit Swapping
GD32VW55x User Manual types. Figure 21-1. DATAM No swapping and Half-word swapping word0 word0 WORD 0 (MSB) word1 word1 WORD 1 word2 word2 WORD 2 word3 word3 WORD 3 (LSB) No swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Half-word swapping Figure 21-2.
Page 563: Figure 21-3. Hau Block Diagram
GD32VW55x User Manual 21.4. HAU core The hash acceleration unit is used to compute condensed information of input messages with secure hash algorithms. The digest result has a length of 160 / 224 / 256 / 128 bits for a message up to (264-1) bits computed by SHA-1, SHA-224, SHA256 and MD5 algorithms respectively.
Page 564 GD32VW55x User Manual configured as the 64-bit length value above, and CALEN bit in the HAU_CFG register can be set 1 to start the calculation of the digest of the last block. Data Padding Example: The input message is “HAU”, which ASCII hexadecimal code is: 484155 Then the VBL bits in the HAU_CFG register is set as decimal 24 because of the valid bit length.
Page 565 GD32VW55x User Manual When CPU is used to transfer data without DMA:  The intermediate block computing can be started when HAU_DI is filled with another new word of the next block.  The last block computing can be started when CALEN bit in the HAU_CFG register is 1. Hash mode 21.4.3.
Page 566 GD32VW55x User Manual When suspending the current task, it is necessary to save the context of the current task from registers to memory, and then the task can be resumed by restoring the context from memory to the HAU registers. The following steps can be performed to complete the HAU process of the suspended data blocks.
Page 567 GD32VW55x User Manual 8. Resume the previous core state. Restore the content from memory to HAU_CTXS0 ~ HAU_CTXS37 (HAU_CTXS0 ~ HAU_CTXS53 when HMAC operation is to be resumed) registers. 9. Set DMAE bit of HAU_CTL register to 1, continue the operation from where it suspended before.
Page 568 GD32VW55x User Manual 21.7. Register definition HAU base address: 0x4C06 0400 HAU control register (HAU_CTL) 21.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ALGM[1] Reserved Reserved DINE NWIF[3:0] ALGM[0] DATAM[1:0] DMAE START Reserved...
Page 569 GD32VW55x User Manual ALGM[0] Algorithm selection bit 0 This bit and bit 18 of CTL are written by software to select the SHA-1, SHA-224, SHA256 or the MD5 algorithm: 00: Select SHA-1 algorithm 01: Select MD5 algorithm 10: Select SHA224 algorithm 11: Select SHA256 algorithm HAU mode selection, must be changed when no computation is processing 0: HASH mode selected...
Page 570 GD32VW55x User Manual This register has to be accessed by word (32-bit). DI[31:16] DI[15:0] Bits Fields Descriptions 31:0 DI[31:0] Message data input When write to these registers, the current content pushed to IN FIFO and new value updates. When read, returns the current content. HAU configuration register (HAU_CFG) 21.7.3.
Page 571 GD32VW55x User Manual 0x1F: Only bits [31:1] of the last data written to HAU_DI after data swapping are valid Note: These bits must be configured before setting the CALEN bit. HAU data output register (HAU_DO0…7) 21.7.4. Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) The data output registers are read only registers.
Page 572 GD32VW55x User Manual HAU_DO3 Address offset: 0x18 and 0x31C DO3[31:16] DO3[15:0] HAU_DO4 Address offset: 0x1C and 0x320 DO4[31:16] DO4[15:0] HAU_DO5 Address offset: 0x324 DO5[31:16] DO5[15:0] HAU_DO6 Address offset: 0x328 DO6[31:16] DO6[15:0] HAU_DO7 Address offset: 0x32C...
Page 573 GD32VW55x User Manual DO7[31:16] DO7[15:0] Bits Fields Descriptions 31:0 DO0..7[31:0] Message digest result of hash algorithm HAU interrupt enable register (HAU_INTEN) 21.7.5. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CCIE DIIE Bits...
Page 574 GD32VW55x User Manual Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. BUSY Busy bit 0: No processing 1: Data block is in process DMAS DMA status 0: DMA is disabled (DMAE = 0) and no transfer is processing 1: DMA is enabled (DMAE = 1) or a transfer is processing Digest calculation completion flag 0: Digest calculation is not completed...
Page 575: Figure 22-1. Pkcau Module Block Diagram
GD32VW55x User Manual Public Key Cryptographic Acceleration Unit (PKCAU) Overview 22.1. Public key encryption is also called asymmetric encryption, asymmetric encryption algorithms use different keys for encryption and decryption. The Public Key Cryptographic Acceleration Unit (PKCAU) can accelerate RSA (Rivest, Shamir and Adleman), Diffie-Hellmann (DH key exchange) and ECC (elliptic curve cryptography) in GF(p) (Galois domain).
Page 576 GD32VW55x User Manual Figure 22-1. PKCAU module block diagram PKCAU registers Control/status clear PKCAU_CTL Control PKCAU_STAT logic status PKCAU_STATC interrupt PKCAU PKCAU RAM core (3584 bytes) Operands 22.3.1. If the RSA operand size is ROS, the modulus length is ML, then the data size is ROS = (ML/32+1) words.
Page 577: Figure 22-2. Flow Chart Of Rsa Algorithm
GD32VW55x User Manual Figure 22-2. Flow chart of RSA algorithm Alice Save public Generate key from Bob key pairs message message encryption Public key decryption Private key algorithm from Bob algorithm from Bob ciphertext ciphertext A complete public key crypto system includes key pairs (public and private keys), encryption algorithms and decryption algorithms.
Page 578: Figure 22-3. Flow Chart Of Ecdsa Sign
GD32VW55x User Manual key. The decryption process is m = c mod n. ECC algorithm 22.3.3. Suppose the message is M, d is the private key, G is the base point of the chosen elliptic curve, Q is a point of the chosen elliptic curve,with a prime order n. The hash function is HASH(), z is the Ln leftmost bits of HASH (M), where Ln is the bit length of the order n.
Page 579: Figure 22-4. Flow Chart Of Ecdsa Verification
GD32VW55x User Manual ECDSA verification Before verifying the signature, be sure to get the signer's public key, message, and signature. The process to generate ECDSA signature is shown in Figure 22-4. Flow chart of ECDSA verification. Figure 22-4. Flow chart of ECDSA verification start 0<r<n and 0<s<n? Calculate w=s...
Page 580: Figure 22-5. Arithmetic Addition
GD32VW55x User Manual MODSEL[5:0] Operation modes 000001 calculate Montgomery parameter only 000010 modular exponentiation (the Montgomery parameter must be preloaded) 000111 RSA CRT exponentiation 001000 Modular inversion 001001 Arithmetic addition 001010 Arithmetic subtraction 001011 Arithmetic multiplication 001100 Arithmetic comparison 001101 Modular reduction 001110 Modular addition...
Page 581: Figure 22-6. Arithmetic Subtraction
GD32VW55x User Manual Figure 22-6. Arithmetic subtraction PKCAU RAM offset address output offset address input 0x400 0x404 Operand length L 0x408 0x8B4 Operand A 0xA44 Operand B 0xBD0 0xBD0 0≤A<2 , 0≤B<2 , 0≤result<2 , 0<L≤3136. Arithmetic multiplication The arithmetic multiplication operation is selected by configuring MODSEL[5:0] in PKCAU_CTL register as "001011".
Page 582: Figure 22-8. Arithmetic Comparison
GD32VW55x User Manual comparison. If A=B, the operation result is “result =0x0”; If A>B, the operation result is “result =0x1”; If A<B, the operation result is “result =0x2”. Figure 22-8. Arithmetic comparison PKCAU RAM Offset address input output Offset address 0x400 0x404 Operand length L...
Page 583: Figure 22-10. Modular Addition
GD32VW55x User Manual Modular addition The modular addition operation is selected by configuring MODSEL[5:0] in PKCAU_CTL register as "001110". The operation declaration is shown in Figure 22-10. Modular addition. The operation result is “result = A+B mod n”. Figure 22-10. Modular addition PKCAU RAM Offset address Offset address...
Page 584: Figure 22-11. Modular Subtraction
GD32VW55x User Manual Figure 22-11. Modular subtraction PKCAU RAM Offset address output input Offset address 0x400 0x404 Modulus length M 0x408 0x8B4 Operand A 0xA44 Operand B 0xBD0 0xBD0 A-B mod n 0xD5C / A-B+n mod n Modulus n 0≤A<n, 0≤B<n, 0≤result<n, 0<n<2 , 0<M≤3136.
Page 585: Figure 22-13. Mutual Mapping Between Montgomery Domain And Natural Domain
GD32VW55x User Manual Montgomery multiplication Suppose A, B and C are in natural domain. “x” function is Montgomery multiplication operation. The two main uses of this opreation are as follows: 1. Mutual mapping between Montgomery domain and natural domain. As is shown in Figure 22-13.
Page 586: Figure 22-14. Montgomery Multiplication
GD32VW55x User Manual Figure 22-14. Montgomery multiplication PKCAU RAM Offset address output input Offset address 0x400 0x404 Modulus length M 0x408 0x8B4 Operand A 0xA44 0xBD0 Operand B AxB mod n 0xD5C Modulus n 0≤A<n, 0≤B<n, 0<n<2 , 0<M≤3136 (n must be odd integer). Modular exponentiation Normal mode The Modular exponentiation of normal mode operation is selected by configuring...
Page 587: Figure 22-16. Modular Exponentiation Of Fast Mode
GD32VW55x User Manual in PKCAU_CTL register as "000010". The operation declaration is shown in Figure 22-16. Modular exponentiation of fast mode. The operation result is “result = A mod n”. Figure 22-16. Modular exponentiation of fast mode Offset address input output Offset address 0x400...
Page 588: Figure 22-18. Rsa Crt Exponentiation
GD32VW55x User Manual 2． If the modulus n is not prime, only when the greatest common divisor of A and n is 1, the modular inversion output is valid. RSA CRT exponentiation The RSA CRT exponentiation operation is selected by configuring MODSEL[5:0] in PKCAU_CTL register as "000111".
Page 589: Table 22-3. Range Of Parameters Used By Rsa Crt Exponentiation Operation
GD32VW55x User Manual Table 22-3. Range of parameters used by RSA CRT exponentiation operation Parameters Range 0≤d <2 Operand d 0≤d <2 Operand d 0<q <2 Operand q Input 0<p<2 Prime p 0<q<2 Prime q 0≤A<2 Operand A result = A mod pq 0≤result<pq Output...
Page 590: Figure 22-19. Point On Elliptic Curve Fp Check
GD32VW55x User Manual Figure 22-19. Point on elliptic curve Fp check Offset address output input Offset address 0x400 0x400 result 0x404 0x404 Modulus length M 0x408 Sign of curve coefficient 0x40C Curve coefficient |a| 0x460 Curve modulus 0x55C x coordinate of point P 0x5B0 y coordinate of point P 0x7FC...
Page 591: Figure 22-20. Ecc Scalar Multiplication Of Normal Mode
GD32VW55x User Manual Figure 22-20. ECC scalar multiplication of normal mode Offset address output input Offset address 0x400 Length of scalar multiplier k 0x404 Modulus length 0x408 Sign of curve coefficient a 0x40C Curve coefficient |a| 0x460 Curve modulus p 0x508 scalar multiplier k 0x55C...
Page 592: Figure 22-22. Ecdsa Sign
GD32VW55x User Manual Table 22-6. Range of parameters used by ECC scalar multiplication Parameters Range Length of scalar 0<LEN≤640 multiplier k (LEN) 0<M≤640 Modulus length M Sign of curve 0x0: positive coefficient a 0x1: negative input Curve coefficient |a| Absolute value |a|<p Odd prime 0<p≤2 Curve modulus p 0≤k<2...
Page 593: Table 22-7. Range Of Parameters Used By Ecdsa Sign
GD32VW55x User Manual Figure 22-22. ECDSA sign PKCAU RAM Offset address output input Offset address 0x400 Curve prime order n length 0x404 Curve modulus p length M 0x408 Sign of curve coefficient a 0x40C Curve coefficient |a| 0x460 Curve modulus p 0x508 Integer k 0x55C...
Page 594: Figure 22-23. Ecdsa Verification
GD32VW55x User Manual Parameters Range 0<r<n Signature part r 0<s<n Signature part s 0x0: no error Signature result: 0x1: Signature part r is 0 ERROR output 0x2: Signature part s is 0 Curve point kG 0≤x <n coordinate x Curve point kG 0≤y <n coordinate y...
Page 595: Table 22-8. Range Of Parameters Used By Ecdsa Verification
GD32VW55x User Manual of parameters used by ECDSA verification. Table 22-8. Range of parameters used by ECDSA verification Parameters Range Curve prime order n 0<LEN≤640 length (LEN) Curve modulus p 0<M≤640 length (M) Sign of curve 0x0: positive coefficient a 0x1: negative Curve coefficient |a| Absolute value |a|<p...
Page 596: Table 22-9. Modular Exponentiation Computation Times
GD32VW55x User Manual 2. Load the initial data into PKCAU RAM at offset address 0x400; 3. Specify the operation to be performed in MODSEL[5:0] bits in PKCAU_CTL register, then set START bit in PKCAU_CTL register; 4. Wait for the ENDF bit set in PKCAU_STAT register; 5.
Page 597: Table 22-10. Ecc Scalar Multiplication Computation Times
GD32VW55x User Manual Exponent Operand length (in bits) Mode length (in bits) 1024 2048 3072 13651000 Normal 182783000 3072 Fast 181953000 44905000 Table 22-10. ECC scalar multiplication computation times Modulus length (in bits) Mode Normal 626000 951000 1997000 3617000 5762000 13134000 Fast 623000...
Page 598: Table 22-14. Pkcau Interrupt Requests
GD32VW55x User Manual  End of operation flag (ENDF) When the operation specified in MODSEL[5:0] bits in the PKCAU_CTL register is completed, the ENDF bit will be set. If the ENDIE bit in PKCAU_CTL register is set, an interrupt will be generated.
Page 599 GD32VW55x User Manual Register definition 22.4. PKCAU base address: 0x4C06 1000 Control register (PKCAU_CTL) 22.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by word (32-bit) ADDRER RAMERR Reserved Reserved ENDIE Reserved PKCAUE Reserved MODSEL[5:0] Reserved START Bits Fields...
Page 600 GD32VW55x User Manual 001010: Arithmetic subtraction 001011: Arithmetic multiplication 001100: Arithmetic comparison 001101: Modular reduction 001110: Modular addition 001111: Modular subtraction 010000: Montgomery multiplication 100000: Montgomery parameter computation then ECC scalar multiplication 100010: ECC scalar multiplication only (Montgomery parameter must be loaded first) 100100: ECDSA sign 100110: ECDSA verification...
Page 601 GD32VW55x User Manual 0: No address error. 1: The accessed address exceeds the expected range of PKCAU RAM, an address error occurs. RAMERR PKCAU RAM error 0: No PKCAU RAM error. 1: When the PKCAU core is using the RAM, AHB accesses the PKCAU RAM, a PKCAU RAM error occurs.
Page 602 GD32VW55x User Manual Software can clear the ENDF bit in PKCAU_STAT by writing 1 to this bit. Reserved Must be kept at reset value. 16:0...
Page 603: Figure 23-1. Ifrp Output Timechart 1
GD32VW55x User Manual Infrared ray port (IFRP) 23.1. Overview Infrared ray port (IFRP) is used to control infrared light LED, and send out infrared data to implement infrared ray remote control. There is no register in this module, which is controlled by TIMER15 and TIMER16. The IFRP_OUT pin can be configured by GPIO alternate function selected register.
Page 604: Figure 23-2. Ifrp Output Timechart 2
GD32VW55x User Manual Figure 23-2. IFRP output timechart 2 TIMER16_CH0 TIMER15_CH0 IFRP_OUT Note: Carrier (TIMER15_CH0)’s duty cycle can be changed, and IFRP_OUT has inverted relationship with TIMER16_CH0 when TIMER15_CH0 is high. Figure 23-3. IFRP output timechart 3 TIMER16_CH0 TIMER15_CH0 IFRP_OUT Note: IFRP_OUT will keep the integrity of TIMER16_CH0, even if evelope signal (TIMER15_CH0) is no active.
Page 605 GD32VW55x User Manual Wireless 24.1. Overview The GD32VW55x is a highly integrated Wireless System-on-Chip (SoC) that includes an RISC-V processor with a single stream Wi-Fi6 MAC and PHY, BLE5 link layer and modem, RF transceiver, a power amplifier (PA), and a receive low-noise amplifier (LNA). It is an optimized SoC designed for a broad array of smart devices for Internet of Things (IoT) applications.
Page 606 GD32VW55x User Manual  Hardware engine for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, and support for key management. Programmable independent basic service set (IBSS) or infrastructure basic service set  or Access Point functionality. Wi-Fi PHY Single antenna 1x1 stream in 20MHz channels. ...
Page 607 GD32VW55x User Manual  Long range coded PHY.  Data rate: 250, 500, 1000 and 2000kbps. 24.4. Radio Radio is shared between Wi-Fi and BLE.  Fractional-N for multiple reference clock support.  Integrated PA with power control.  Optimized Tx gain distribution for linearity and noise performance. ...
Page 608: Table 25-1. List Of Abbreviations Used In Register
GD32VW55x User Manual Appendix 25.1. List of abbreviations used in register Table 25-1. List of abbreviations used in register abbreviations for Descriptions registers read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit. write-only (w) Software can only write to this bit.
Page 609 GD32VW55x User Manual Glossary Descriptions programming) JTAG protocol, or the boot loader while the device is mounted on the user application board. Option bytes Product configuration bits stored in the Flash memory. Advanced high-performance bus. Advanced peripheral bus. Read-as-zero. Writes ignored. RAZ/WI Read-as-zero, writes ignored.
Page 610: Table 26-1. Revision History
GD32VW55x User Manual Revision history Table 26-1. Revision history Revision No. Description Date Initial Release. Oct.13, 2023...
Page 611 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.

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