Pll Section - Kenwood TM-201A Service Manual

TM-201A
» CIRCUIT DESCRIPTION
> TX SECTION
The signal trom cha microshone 's amcii
(NJMS558S) on the "°B™ unit (X53-1340-11,
611, before being sicde limited by O39 {MC911) where IDC
(instantaneous deviation controll 's provided to prevent over
deviation. Then LPF lowpass filter) O54 (NJM 4598S) filters
the higher frequencies and phase-modulates the transmitter
PLL loop.
The phase-modulated &M signal is assed through VCO buf-
fer Q45 (2SC26éaY) before being amplified by drive O46
(28C2347) and O47 (2SC2538) to yield the output for the Tinput Zvect 3vcc2 Gout §GNno
Final unit.
Tne signal tec co we Final unit (X45-1990-11) is power
amplified by power hybrid Q1 (M57737). The signal 's then
Fig. 5 Power module M57737 equivalent circuit
> being apctied to differential amplifier pair Q50 and O51. The PLL SECTION
Za=zins02 | 40W
Table 4 Power Module M57737 max rating and electrical
characteristic
ifferential amplifier controls Q49 (2SA1015Y) ara Qs8 The PLL c i r c u i t ' s comprised of swo loons: one for transmission
(2SC880: ana varies the voltage at Q1 pin 2 on the Fina} uAit
and one for reception. Tha biock diagram is given in Fig.6
and at 027 on unit "8", theraby controlling the output | Receiver PLL
transmitter. The signal generated by RX VCO 027 [2SK125) on "A" unit
(X44-1530-14) (133.305-137.295 MHz) is mixed by
022 (2SC2668Y) to become a PLL signal at 10.97-
14.96 Miz. This is amplified by 023 (2SC266BY) and then
input to PD {phase detector) IC Q19 (MC145155PI. The
> : | © 40.1116 MHz heterodyne signal generated by Q20
| 1 (2$C2668Y) is tripled to 122.335MHz by Q21
@ H ©) (2SC2787L) before being input to mixer transistor Q22
+ | When the PLL IF signal is input to 019 (pin 9), it i s divided by
on 2 rato of N=2194~2592, specified by the data from
] @ microprocessor Q1 (yPO7508G-534), Simultaneousiy, the
© a 10.24 MHz signal generated 2y 030 is buffered by Q31 and
\ Hl | is then divided by 1/2048 to become the 5 kHz reference
Heat} Q- comparison signal
ora) x | i 'on The phase compared output signal is passed through LPF
Y a ok 025 and 026 (2SC2459BL) ard 's applied as the VCO con.
b aa 2 ; a trol voltage to varicap D012 {1$2208), then 'ocked to the
desired frequency. If the PLL loop uniocks, the unlock signal
from Q19 (pin 8) turns off Q24 (2SC2258Y), which in turn
054, 55) stops the operation of VCO buffer amplifier 029.
Fig. 4 NJM45585 (B
Transmitter PLL
The signal generated by TX VCO Q4¢ (2SK125) on 8'" unit
(144 00-145 990 MHz) is mixed with the RX PLL outout signal
(133.305-136.295 MHz) at mixer Q36 (2SC2668YIt0
become a 10.695 MHz signal. This is amoiitied by 036
3
wes