Summary of Contents for SD Association SD-501
- Page 1 SD Card Specification Simplified Version of: Part E1 SD Input/Output (SDIO) Card Specification Version 1.00 October, 2001 SD Association Copyright 2000, 2001 SD Association...
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Page 2: Revision History
SDIO Simple Specification Version 1.0 DO NOT COPY ©Copyright SD Association, 2000, 2001 Revision History Date Version Changes compared to previous issue October, 2001 Base version initial release Conditions for publication Publisher and Copyright Holder: SD Association 719 San Benito St. Suite C Hollister, CA 95023 Phone: +1 831 636 7322 Fax: +1 831 623 2248... -
Page 3: Table Of Contents
Table of Contents General Description... 1 SDIO features ... 1 Primary Reference Document ... 1 SDIO Signaling Definition ... 2 SDIO Card Types ... 2 SDIO Card modes ... 2 2.2.1 SPI (Card mandatory support) ... 2 2.2.2 1-bit SD data transfer mode (Card mandatory support) ... 2 2.2.3 4-bit SD data transfer mode (mandatory for High-Speed cards, optional for Low-Speed) ... - Page 4 10.2 SDIO Power Consumption... 18 10.3 SDIO Current ... 18 Abbreviations and Terms ... 19 SD and SPI Command List ... A Normative References ...C Example SDIO Controller Design ...D Table 1 SDIO pin definitions ... 3 Table 2 Unsupported SD Memory Commands ... 7 Table 3 SDIO exceptions to SD physical section 8.1 requirements ...
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Page 5: General Description
General Description The SDIO (Secure Digital I/O) card is based on and compatible with the SD memory card. This compatibility includes mechanical, electrical, power, signaling and software. The intent of the SDIO card is to provide high-speed data I/O with low power consumption for mobile electronic devices. A primary goal is that an SDIO card inserted into a non-SDIO aware host will cause no physical damage or disruption of that device or it’s software. -
Page 6: Sdio Signaling Definition
IO devices with a minimum of hardware. The Low-Speed cards support such functions as modems, bar-code scanners, GPS receivers etc. If a card is a ‘Combo card’ (memory plus SDIO) then Full-Speed and 4-bit operation is mandatory for both the memory and SDIO portions of the card. -
Page 7: Signal Pins
Signal Pins Figure 1 Signal connection to two 4-bit SDIO cards SD 4-bit mode CD/DAT[3] Data line 3 Command line VSS1 Ground Supply voltage Clock VSS2 Ground DAT[0] Data line 0 DAT[1] Data line 1 or Interrupt (optional) DAT[2] Data line 2 or Read Wait (optional) It is recommended that multi-slot hosts intending to support SDIO (SDIO aware) provide a separate CLK to... -
Page 8: Sdio Card Initialization
SDIO Card Initialization Differences in I/O card initialization A requirement for the SDIO specification is that an SDIO card must not cause non-I/O aware hosts to fail when inserted. In order to prevent operation of I/O Functions in non-I/O aware hosts, a change to the SD card identification mode flowchart is needed. -
Page 9: Figure 2 Card Initialization Flow In Sd Mode (Sdio Aware Host)
if N R o r (F = 0 & M P = 1 ) if O C R in v a lid & M P = 1 if tim e o u t IO R D Y tim e o u t in d ic a te s IO fa ilu re {M E M = 0 } R e in it... -
Page 10: Figure 3 Card Initialization Flow In Spi Mode (Sdio Aware Host)
if IR or (F=0 & MP=1) if OCR invalid & MP=1 No voltage compare performed by card for CMD5 if (IR or timeout) & MP=1 if IORDY if PI=0 and MP=1 {MEM=0} Reinit Memory Get MemoryOCR OCR Valid if IR if MEMRDY MEM=1 IO=0,MEM=1 Card... -
Page 11: Differences With Sd Memory Specification
Differences with SD Memory Specification Unsupported SD Memory commands Several commands required for SD Memory devices are not supported by either SDIO-only cards or the I/O portion of Combo cards. Some of these commands have no use in SDIO devices such as Erase commands and thus are not supported in SDIO. -
Page 12: Bus Width
Bus Width For a SD memory card, the bus width for SD mode is set using ACMD6. The SDIO card uses a write to the CCCR using CMD52 to select bus width. In the case of a combo card, both selection methods exist. In this case, the host shall set the bus width in both locations by issuing both the ACMD6 and the CCCR write using CMD52 with the same width before starting any data transfers. -
Page 13: New I/O Read/Write Commands
New I/O Read/Write Commands Two additional data transfer instructions have been added to support I/O. IO_RW_DIRECT, a direct I/O command similar to the MMC 'Fast I/O' command, and IO_RW_EXTENDED, which allows fast access with byte or block addresses. Both commands are in class 9 (I/O Commands). IO_RW_DIRECT command (CMD52) The IO_RW_DIRECT is the simplest means to access a single register within the total 128K of register space in any I/O function, including the common I/O area (CIA). -
Page 14: Sdio Card Internal Operation
SDIO Card Internal Operation I/O access differs from memory in that the registers can be written and read individually and directly without a FAT file structure or the concept of blocks (although block access is supported). These registers allow access to the I/O data, control of the I/O function and report on status or transfer I/O data to/from the host. -
Page 15: Suspend/Resume
Suspend/Resume Within a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that must share access to the SD bus. In order to allow the sharing of access to the host among multiple devices, SDIO and combo cards can implement the optional concept of suspend/resume. -
Page 16: Sdio Fixed Internal Map
SDIO Fixed Internal Map The SDIO card has a fixed internal register space and a Function unique area. The fixed area contains information about the card and certain mandatory and optional registers in fixed locations. The fixed locations allow any host to obtain information about the card and perform simple operations such as enable in a common manner. -
Page 17: Card Common Control Registers (Cccr)
Card Common Control Registers (CCCR) The Card Common Control Registers allow for quick host checking and control of an I/O card’s enable and interrupts on a per card (master) and per function basis. The bits in the CCCR are mixed Read/Write and read only. -
Page 18: Sdio Interrupts
SDIO Interrupts In order to allow the SDIO card to interrupt the host, an interrupt function is added to a pin on the SD interface. Pin number 8, which is used as DAT[1] when operating in the 4-bit SD mode, is used to signal the card’s interrupt to the host. -
Page 19: Sdio Physical Properties
SDIO Physical Properties SDIO Size The SDIO card is compatible with host sockets designed for SD memory cards. In addition, the SDIO cards can be extended to allow for external connectors, antennas etc. With the exception of the write protect switch, all SDIO cards must meet the mechanical specifications described in the SD Physical spec version 1.01 for that portion of the card that is not extended. -
Page 20: Sdio Mechanical Extensions
SDIO Mechanical Extensions In order to implement some function in the SD card form factor, some extensions to the standard card size and constructions may be needed. There are two areas of extension defined for SDIO devices. Both of these extensions are optional, and may be used by card vendors based upon their needs. -
Page 21: Figure 5 Sdio Mechanical Extensions
SDIO Simple Specification Version 1.0 DO NOT COPY ©Copyright SD Association, 2000, 2001 Figure 5 SDIO Mechanical Extensions... -
Page 22: 10. Sdio Power
10. SDIO Power 10.1 SDIO Card Initialization Voltage SDIO cards follow the same voltage and current requirements as SD memory cards. This means that an SDIO or combo card must allow basic communication with the card at an initial voltage range of 2.0 to 3.6V. This basic communication is defined as: CMD5 with arg=0, CMD0, CMD15 and CMD58. -
Page 23: Abbreviations And Terms
Abbreviations and Terms Block A number of bytes, basic data transfer unit CCCR Common Card Control Registers Connect/Disconnect Common Information Area Card IDentification number register Card Information Structure Clock signal Command line or SD bus command (if extended CMDXX) Combo Card A card that includes both SDIO and SD memory Cyclic Redundancy Check Chip or Card Select... - Page 24 Read After Write Relative Card Address register Resume Re-starting the temporarily halted data transfer Reserved for Future Use. Normally Read-Only and set to 0 Read Only Memory Read Wait Control SD Configuration Register Secure Digital SD Association SDCLK SD clock signal SDIO Secure Digital I/O SDIO aware...
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Page 25: A.1 Sd And Spi Command List
A.1 SD and SPI Command List Table 4 and Table 5 show the commands that are supported by SD memory and SDIO devices in both SPI and SD modes. If a command is not identified as either mandatory or optional, then it is not supported by that device. -
Page 26: Table 5 Spi Mode Command List
Supported Abbreviation Commands CMD0 GO_IDLE_STATE CMD1 SEND_OP_COND CMD5 IO_SEND_OP_COND CMD9 SEND_CSD CMD10 SEND_CID CMD12 STOP_TRANSMISSION CMD13 SEND_STATUS CMD16 SET_BLOCKLEN CMD17 READ_SINGLE_BLOCK CMD18 READ_MULTIPLE_BLOCK CMD24 WRITE_BLOCK CMD25 WRITE_MULTIPLE_BLOCK CMD27 PROGRAM_CSD CMD28 SET_WRITE_PROT CMD29 CLR_WRITE_PROT CMD30 SEND_WRITE_PROT CMD32 ERASE_WR_BLK_START CMD33 ERASE_WR_BLK_END CMD38 ERASE CMD42 LOCK_UNLOCK... -
Page 27: B.1 Normative References
SDIO Simple Specification Version 1.0 DO NOT COPY ©Copyright SD Association, 2000,2001 Appendix B (Normative) B.1 Normative References The following documents are referenced by this specification. The reader is directed to the respective owners to obtain copies. 1) SD Memory Card Specifications Part 1 PHYSICAL LAYER SPECIFICATION Version 1.01 September 2000 2) SD Memory Card Specifications... -
Page 28: C.1 Example Sdio Controller Design
C.1 Example SDIO Controller Design Figure 6 shows an example of an SDIO controller design. In this example, two independent state machines are used. The first is the Bus State machine, which communicates with the host and maintains bus states. Figure 7 shows an example state table for this machine. -
Page 29: Figure 8 State Diagram For Function State Machine
Power on, IO Reset from any state Go Inactive request Read Complete Abort asserted CMD53 Read Read Not Ready IOEN=1 IORDY=1 RF=0 EX=1 Read Data Continue Read Transfer Ready Multiple Read Data Transfer State IOEN=1 IORDY=1 RF=1 EX=1 Figure 8 State Diagram for Function State Machine Disable State IOEN=0 IORDY=0...
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