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TX-40ESR500
9 Block Diagram
9.1.
Main Block Diagram
* For UK/Continental
Onboard
Single
Tuner
IEC
EXT_IFAGC1
IF1
TU-IIC1
41MHz
* For DACH/New Zealand
* For Australia
<
ODU_ON
>
ODU_DET
REG
S15.7
BE-IIC
LNB
DiSEqC1
LNB
S3.3/S1.8
S3.3/S1.8
S3.3/S1.8
Onboard
Onboard
Single
Single
Tuner
Tuner
TU-IIC1
TU-IIC1
EXT_IFAGC1
EXT_IFAGC1
IF1
IF1
IF1
IEC
IEC
IFAGC2
IFAGC2
IFAGC2
F
I_1
Q_1
AV2018
SAT_AGC2
S3.3/ S1.2
S3.3/ S1.2
<
FE_XRST
<
FE_XRST
EXT_IFAGC1
BE-IIC
IF1
BE-IIC
DVB-T2/T/C
TU-IIC1
DVB-T2/T/C
TU_Serial_TS1
DEMOD
DVB-S/S2
TU_Serial_TS1
SAT_AGC2
DEMOD
1
(TU_Para_TS1)
I_1
(TU_Para_TS1)
1
FEAINP
Q_1
Low-IF
DiSEqC1
FEAINN
IF1
IFAGC2
41MHz
DEMOD
Analog AV
CVBS
SCART_CVBS
Input
Non Use
Y
(CVBS)
YPbPr
R
Pb
Non Use : SCART_RGB, FB, SLOW,
L
Pr
Non Use
COMP_DET
SCART_CVBS OUT
Non Use
L/R in
Head
AUDIO OUT
Phone
Non Use
S3.3
HP
HP OUT
Head Phone L/R
Driver
OPT
Optical OUT
ARC OUT
Rx0
HDMI1
HDMI1.4
HDCP1.4
DDC1 > MT5581
HPD1 < MT5581
HDMI_5V_DET1 > MT5581
Rx1
HDMI2
HDMI1.4
DDC2 > MT5581
HDCP1.4
HPD2 < MT5581
* Only Australia/New Zealand
HDMI_5V_DET2 > MT5581
Rx2
HDMI3
HDMI1.4
DDC3 > MT5581
CEC
HDCP1.4
HPD3 < MT5581
HDMI_5V_DET3 > MT5581
S3.3
P15V
Lch:10W
I2S AMP
I2S(MCLK/LRCLK/BCLK/SDAT)
YDA176-QZ
XRST/#AMP_MUTE
(YAMAHA)
Rch:10W
#SOS
24
3W+3W
K-PCB
LUMINANCE
Sensor
AI_SENSOR
>
S3.3
16MHz
Card I/F
BCAS
CLK
RST
* Only UK/Continental/DACH
CLE
DATA
S5
INT
CI_POWER_ON
>
<
CI_OCP
CI
Power
Circuit
Transport
CI+
Stream
DATAIN[7:0]
CLKIN
SYNCIN
VAL_IN
IRQ
EA[14:0]
DATAIN[7:0]
DATAOUT[7:0]
WAIT
RESET
CLKIN
CLKOUT
CD1
CE1/WE
SYNCIN
SYNCOUT
CD2
OE/IOWR
(eMMC)
TU_Serial_TS1 / TU_Serial_TS1_JP
Wired OR
VAL_IN
VALOUT
(TU_Para_TS1)
IORD
STB1.05
S1.0
S3.3
S1.8
Internal CI
SPI-IF
controller
SAW
ADC
FLT
DTV
Decoder
ATSC
SUB
Trans Port Demux
DVB-T/C
MAIN
3D/2D NR
Color
Space
ATV
Scaler
Convert
Decoder
AV Decoder
Digital SIF
HEVC/ VP9
2Dto3D
Digital CVBS
Dec video
Dec
Main
TV Decoder
Audio
IMGRSZ
B2R
SCE
CVBS VFE
ADC
[0]
VBI/COMB
Sub
V-SW
External Video(Analog)
Scaler
ADC
RGB/YUV
[3:1]
Processor
External Video(HDMI)
VDAC
CVBS
TV Encorder
OSD
3D GPU
Graphics
Audio
Graphic Processor
A-SW
ADC
ARM11
GPU
DSP
DAC
For Audio
ARM Mali-450 432MHz
VDOIN
SPDIF
SW
UART
UART
EDID0
UART-DMA(NonUse)
UART-PD(TK serial / uP Debug)
UART-DBG(Soft Debug)
Host CPU
MT5581P
IIC
EDID1
ARM Coretex-A7
HDMI
BE_IIC0
IIC
Rx
Quad Core
BE_IIC1
VGA-IIC(NonUse)
924MHz
MUX
x3
EDID2
Standby CPU
8bit-CPU
Turbo8032
Common-Reset
uP
24MHz
STB5V
<
KEY1
P15V
CONTROL PANEL KEY
<
KEY3
Main SW Soft Control
Paragon
Reset
<
TV_SOS
Circuit
AMP/HP MUTE
Analog
MONITOROUT MUTE
ASIC
STB3.3
OVP
Safety
SOS
Circuit
LED Information
REMOCON
<
MON_MUTE
Reciever
<
SP_HP_MUTE
G_LED_ON >
PWMA
R_LED_ON >
PWM_ENB
>
RMIN
>
SDVOLC
PWMOUT
32
S3.3
Debug
eMMC
Connector
32Gb
SCLK
MMCCLK
SDI
MMCCMD
SDO
XERST
(DDR)
CE#1
MMCDAT0-7
S1.5
DDR3
SPI-IF
eMMC-IF
4Gbx16
S1.5
2pcs
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
x16
x16
DDR3
x16
x32bit
Controller
1800MHz(DDR)
LCD
Panel
P15
Local
Scannig PWM
PANEL
P12
Power
Dimming
PANEL_VCC_ON
DCDC
BL_ON
>
LED Driver
BL_SOS
<
LVDS
Gamma
LVDS
T-CON
Tx
FHD model : Dual
HD model : Single
USB2.0-IF
USB2.0
(Port 0)
S5
USB-IF
USB*VBUS >
USB2.0-IF
USB
USB2.0
< OCP*
Power SW
(port1)
USB-1
S5
USB2.0
ARM
USB*VBUS >
(Port 2)
USB
< OVCUR*
Power SW
USB-2
USB2.0
USB2.0-IF
(Port3)
S5
For Wake up On Wireless
SD-IF
ETHER-IF
HDD-USB
Power SW
IEEE802.11n
Wireless UNIT
WOW_ON_IRQ <
< WOW_PWR_ON
> WOW_OVP
ETHER
TX_P/N, RX P/N
S3.3/1.8
10/100M
100Base-T
For Wake up On LAN
S3.3
STB-IIC
EEP
16k
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