Kenwood TM-2550A Service Manual page 5

TM-2550A/E,2530A
CIRCUIT DESECRIPTION
|
|
if
High/Low power swithing is accomplished by applying a
ground to pin number
1 of connector (2) on the FINAL
Item Symbol | Tc(°C) Condition Rating
Operating Vee 25 17V
DC current
Iec
25
7A
Operating case temp.
| Tc (op)
—30~ + 110°C
Storage temp.
Tstg
—40~ + 110°C
Power input Pin 25 Zg = Zi = 502 0.4W
Power output Po 25 Zg = ZI = 502 40W
lik
Lo Le
@IinPpuT @Vcci @Vcc2 @MouT @Gnod
Fig.4 M57737 Equivalent circuit
Item Symbol | Te (°C) Rating
Operating voltage Vee 25 17V.
DC current icc 25 14A
Operating case temp. | Tc (op) —30~ + 110°C
Storage temp. Tstg —40~ + 110°C
Table5 M57726 Max. rating (TM-2550A/E Final unit Q1)
Value
Item Symbol | Tc (°C) Condition
Min.
Typ.
Vcc = 12.5V.
F = 144~148MHz,
PIN =O0.4W,
ZL = ZG = 502
Power output Po 25 43W
47W
Vee = 12.5V,
F = 144~148MHz,
PIN = 0.4W,
ZL = ZG = 502
Total efficiency nT 25 50%
54%
Table 6 ™M57726 Electrical characteristic
H
1,
@in @vcci1 @Vcc2 Mout Ono
Fig.5 M57726 Equivalent circuit
PLL CIRCUIT
The PLL circuit is divided into two main loops : transmit
and receive.
Receive PLL Loop
The signal generated by the RX VCO (Voltage Controlled
Oscillator) Qi6 : 2SK192A(GR)*P is applied to buffer
amplifier Q17 : 2SC2668(Y) and mixed with the HET
(Heterodyne) signal by Q21 : 2SC2668(Y) where it be-
comes the PLL IF signal (K,M 13.015 to 15.010MHz, T,W
12.865 to 19.86MHz). This PLL IF signal is then amplified
by 020 : 2SC2668(Y} and applied to the Phase Detector
{C2 : MC145155P*K where it is divided to obtain a 5kHz
signal. The divide ratio is determined by Serial Data from
the CONTROL unit. This 5kHz signal is compared with the
5kHz reference signal obtained by dividing the 10.240 MHz
Reference signal.
The Phase Detector compares the phase of these two signals
and transmits an error control signal to the VCO. The cont-
rol signal is filtered by an Active Low Pass filter composed
of 013 : 2SK30A(O) and Q14: 2SC2458(Y) to remove
any AC fluctuations to obtain a DC correction voltage. The
correction voltage is used to change the capacitance of
Varactor Diode D5 : 1SV50, which varies the output of the
RX VCO to lock it on frequency.
If the phase difference is too great to be corrected by the
control voltage applied to D5, an unlock signal is generated
by the Phase Detector. This signal turns OFF Q15 :
2SC2458(Y) which turns OFF output amplifier O18 :
2SC2668(Y) to prevent operation outside the authorized
limits.
The PLL HET Oscillator, Q19 : 2SC2668(Y) oscillates at
39.48MHz. This signal is applied to frequency tripler Q22 :
2SC2688(Y) to obtain a signal of 118.44MHz which is
applied to mixer Q21.