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4. Tuner/CI Block Diagram
TDSQ-
+3.3V_D_Demod
+3.3V_TU
G501D
+1.8_TU
[+3.3V_S2_DEMOD] 32
[+3.3V_TUNER] 5
[+.1.8V_TUNER] 7
[+1.23V_S2_DEMOD] 30
[S2_F22_OUTPUT] 33
[LNB] 36
[S2_SCL] 34
[S2_SDA] 35
[RESET] 2
[SLC] 3
33Ω
[SDA] 4
[ERROR] 16
[SYNC] 17
[VALID] 18
[MCLK] 19
[D0-7] 20-27
[S2_RESET] 31
IF_P
[T/C_DIF[P]] 10
IF_N
[T/C_DIF[N]] 11
TUNER_SIF(for T2/C/S)
TU_CVBS(for
T2/C/S) IF_AGC
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+1.23V_D_Demod
+3.3V_NORMAL
3.3K Ω
LNB_TX
10 [TONECTRL]
LNB_OUT
2 [LNB]
7 [SCL]
22 Ω
I2C_SCL4
8 [SDA]
I2C_SDA4
AP6 [SCL3]
AR6 [SDA3]
/TU_RESET1
AG24 [ADIN6_SRV]
AF19[OPCTRL1]
33 Ω
AJ19 [OPCTRL0]
IC2_SDA6
IC2_SCL6
FE_DEMOD1_TS_SYNC
R29 [DEMOD_TSSYNC]
P27 [DEMOD_TSVAL]
FE_DEMOD1_TS_VAL
P30 [DEMOD_TSCLK]
FE_DEMOD1_TS_CLK
FE_DEMOD1_TS_DATA [0-7]
[DEMOD_TSDATA0-7]
/S2_RESET
AM18 [ADIN7_SRV]
ADCINP_DEMOD
AM27 [ADCINP_DEMOD]
Attenuator
ADCINN_DEMOD
AN27 [ADCINN_DEMOD]
PCM_5V_CTL
LNB
IC6900
A8303SESTR-TB
LGE 2122
F28[TCON12]
L33[SPI_CLK]
L30[SPI_CLK1]
M27[PVR_TS_VAL]
M31[CI_TSCLK]
N34[SPI_DATA]
N35[SPI_CLE]
CI_ADDR[0-14]
[GPIO0-14]
CI_DATA[0-7]
[GPIO26-33]
T34[DEMOD_RST]
P34[PVR_TSDATA1]
N36[CI_INT]
P33[PVR_TSDATA0]
R36[CI_TSVAL]
R37[CI_TSSYNC]
MTK5398_TS_CLK
R33[PVR_TSSYNC]
MTK5398_TS_VAL
R3[PVR_TSCLK]
MTK5398_TS_SYNC
R35[CI_TSDATA0]
MT5398_TS_IN[0-7]
[GPIO34-41]
MT5398_TS_OUT[0-7]
[GPIO18-25]
+5V_CI_ON
CI 5V
Power detect
+5V_CI_ON
+3.3V_NORMAL
10K Ω
47K Ω
/CI_CD1
/CI_CD2
CI_VS1
/PCM_CE1
/PCM_CE2
/PCM_IOWR
/PCM_IORD
CI_A_ADDR[0-14]
CI_A_DATA[0-7]
PCM_RST
/PCM_WAIT
PCM_INPACK
/PCM_A_REG
/PCM_IRQA
/PCM_OE
/PCM_WE
CI_TS_CLK
CI_TS_VAL
CI_TS_SYNC
CI_TS_DATA[0-7]
47 Ω
CI_MDI[0-7]
47 Ω
CI Slot
VCC
CI_DET1
CI_DET2
VS1
CARD_EN1
CARD_EN2
IOWD
IORD
ADDR[0-14]
DAT[0-7]
CI_RESET
CI_WAIT
INPACK
REG
/IRQA
O_EN
WR_EN
TS_OUT_CLK
TS_OUT_VAL
TS_OUT_SYNC
TS_OUT[0-7]
TS_IN[0-7]
LGE Internal Use Only
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