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• Pin Function
(
No.
Pin Name
Function
1
RA9
2
RA10
3
RA11
4
RA12
Address
signal outputs
to data
buffer
RAM.
5
RA13
6
RA14
7
RA15
8
vss
GND.
9
100
10 101
11
102
12
103
13
104
Data
signals of data buffer
RAM.
14 105
15
106
16 107
(
17 VDD
Power
supply voltage.
18
vss
GND.
.
19
HD1
I
20
HD2
21
HD2
Host
data signals.
22
HD3
23
vss
GND
24
HD4
25
HD5
26
HD6
Host
data signals.
27
HD7
28
vss
G
ND.
29
N.C
.
No connection.
30
vss
GND.
31
vss
GND.
32
N.C.
No
connection.
33
N.C.
No
connection.
34
N.C.
No
connection.
35
N.C.
No
connection.
36
vss
GND
37
ENABLE
C hip
select
signal input
from
the
host.
38
CMD
Comm
and/data
selection signal input
of
the host.
39
RAMSL
Switch
the
DRAM
and
SRAM.
40
vss
GND
41
VDD
Power
supply voltage.
42
HWA
Data writing
signal input
of
the
host.
43
HAD
Data reading
signal
input
of
the
host.
WAIT
Wait
signal
to
the
host.
44
DRQ
signal
is
obtained by
switching.
45
DTEN
Data enable
signal
output.
46 STEN
Status enable
signal output.
EOP
End
of
process
signal output.
47
Use
for
transferring the
OMA of
data.
48
N.C
.
No
connection.
49
N.C
.
No
connection
.
No.
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DR- UA124X- 2, DR- UA124X- 3
DR- UA124X- 5
Pin Name
Function
SELDRQ
Data
transfer
mode
selection
to
the
host.
RD
Data
reading signal input of the
microcomputer.
WR
Data
writing signal input of the
microcomputer.
cs
Chip select signal input from the microcomputer.
RS
Register
selection signal
input.
VDD
Power
supply
voltage.
vss
GND.
DO
01
02
03
04
Data
signal pins of the
microcomputer.
05
06
07
vss
GND.
INT
Interrupt reguirement
signal output
to the
microcomputer.
SWAIT
SUB - CPU wait signal.
TES TO
TEST1
Input
pins
for
the
test.
TEST2
Normally,
fi
x to
"L".
TEST3
EXCK
WFCK
SBSO
SUB
-
CODE input/output.
SCOR
VDD
Power
supply
voltage.
SDATA
Serial
data
input.
BCK
Serial
data
input
clock.
LACK
44.1
KHz
strobe signal
input.
C2PO
C2 pointer
input.
vss
GND.
XTALCK
Input of
the X' tal
oscillation
circuit.
XTAL
Output
of
the X 'ta! oscillation circuit.
MCK
Divisive
output of X'TALCK.
RESET
Reset
pin.
Reset
for "L"
level.
RCS
Chi
p
select to
the
RAM.
RWE
Data
writing
signal
to the RAM.
ROE
Data reading signal from the
RAM.
VDD
Power supply
voltage.
vss
GND.
RAO
RA1
RA2
RAJ
RA4
Address
signal
outputs to the data
buffer
RAM.
RAS
RA6
RA7
vss
GND.
RAB
Address
signal
output
to the data
buffer RAM.
33
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