Intel GIGA GD16556 Manual
Intel GIGA GD16556 Manual

Intel GIGA GD16556 Manual

2.5 gbit/s transponder chip set with digital "wrapping"

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an Intel company
General Description
The GD16556 and GD16557 constitute a
high performance multi-bitrate tran-
sponder chip set designed for Optical
Network applications. The devices are
available with either LVDS or LVPECL
low-speed I/Os.
The chip set is compatible with the line
rates:
SDH STM-1 / SONET OC3
u
SDH STM-4 / SONET OC12
u
SDH STM-16 / SONET OC48
u
Gigabit Ethernet
u
Switching between the bit rates is possi-
ble on-the-fly through select pins.
The chip set is designed for interconnect-
ing the high-speed line interface to stan-
dard CMOS ASICs or FPGAs. The
on-chip VCO and PLL blocks eliminate
external high-speed clock signals and
complicated timing relations.
Digital "Wrapping" Modes
GD16556 and GD16557 are capable of
transmitting and receiving data at in-
creased rates if overhead is needed for
16
STM-1 / OC3
STM-4 / OC12
STM-16 / OC48
GD16556
Gigabit
CDR &
Ethernet
DeMUX 1:16
Times:
1,
15/14,
16/15,
32/31
Line
Side
STM-1 / OC3
STM-4 / OC12
GD16557
STM-16 / OC48
Jitter
Gigabit
Cleaner &
Ethernet
MUX 16:1
Times:
1,
15/14,
16/15,
32/31
VCXO
system level service purposes. The de-
vices can operate with STM-1 (OC3),
STM-4 (OC12), STM-16 (OC48) and
Gigabit Ethernet line rates multiplied by a
fraction. Fractions available are 32/31,
16/15 and 15/14. Thus, for example, data
might be transmitted (or received) at a
rate of 32/31 times 2.488 Gbit/s with a
high- speed clock of 2.568 GHz. The
fractions are available through selection
of programmable dividers.
Signal Levels and Power Supply
Low speed interfaces are LVDS/LVPECL
compatible. The high-speed output from
the transmitter GD16557 is of CML-type
(open collector). Select pins are LVTTL
compatible.
Low power consumption is achieved by a
single +3.3 V power supply and by omit-
ting all circuitry, which can easily be im-
plemented in the low speed system
ASIC.
The devices are housed in 100 pin TQFP
EDQUAD thermal enhanced packages.
16
System
ASIC
Clock
Clock
VCXO
Clock
Clock
16
16
System
ASIC
Clock
Clock
Clock
Clock
STM-1/OC3
GD16557
STM-4/OC12
Jitter
STM-16/OC48
Cleaner &
Gigabit
MUX 16:1
Ethernet
System
Side
STM-1/OC3
STM-4/OC12
GD16556
STM-16/OC48
CDR &
Gigabit
DeMUX 1:16
Ethernet
2.5 Gbit/s
Transponder
Chip Set with
Digital "Wrapping"
GD16556/GD16557*
Preliminary
Features
General
SDH (SONET) STM-1(OC3) /
l
STM-4(OC12) / STM-16(OC48) / GE
compatible
True on-the-fly multi-bit rate operation
l
Bypass for non-compatible bit rates
l
Loop-back for system test mode
l
Overhead data rate capability
l
– 15/14 (7% overhead)
– 16/15 (6% overhead)
– 32/31 (3% overhead)
LVDS/LVPECL low-speed I/O
l
Single power supply: +3.3 V
l
100 pin TQFP EDQUAD packages
l
GD16556 (Receiver)
Clock and Data Recovery
l
1:16 Demultiplexer
l
Differential input with 5 mV
l
sensitivity
Loss of signal monitor
l
Bit consecutive monitor
l
Lock detect monitor
l
Power dissipation: 1.3 W (typ.)
l
GD16557 (Transmitter)
16:1 Multiplexer
l
Optional double PLL jitter-clean up
l
Counter or forward clocked
l
low-speed interface
PLL lock-detect
l
Power dissipation: 1.3 W (typ.)
l
Applications
Digital "Wrappers"
l
Optical Networking
l
Transponders
l
SDH/SONET FEC out-of-band
l
systems
Network interconnects
l
Gateways
l
Datacom
l
*: Patent pending
Data Sheet Rev.: 23
PP

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Summary of Contents for Intel GIGA GD16556

  • Page 1 2.5 Gbit/s Transponder Chip Set with Digital “Wrapping” an Intel company GD16556/GD16557* Preliminary General Description Features General The GD16556 and GD16557 constitute a system level service purposes. The de- high performance multi-bitrate tran- vices can operate with STM-1 (OC3), sponder chip set designed for Optical...
  • Page 2: Functional Details

    Functional Details General The transmitter and receiver chip set is GD16556 GD16557 optimised for transponder solutions and Data Data 2.488 Gbit/s DO0/N DI0/N DO/N Optical Network interconnects such as 2.488 GHz DO15/N DI15/N CKO/N bridges and gateways. The intended System 32/31 DI/N ASIC...
  • Page 3 sures that the transponder system meets (prescalers). By proper setting of the the jitter specifications. dividers the transponder system will com- ply with bit rates equal to a standard bit The core circuit is illustrated on Figure 2 rate ( STM-1 / OC3, STM-4 / OC12, For simplicity the system ASIC and con- STM-16 / OC48, GE) multiplied by a frac- nections to this device have been omit-...
  • Page 4: Practical Considerations

    Practical Considerations The PCB Layout The PCB must be designed with shortest Output Input possible conductors for the data inter- faces and clock distribution. Design these connections as transmission lines. LVDS LVDS The LVTTL compatible select pins are supplied with an on-chip pull-up resistor (Figure 4) given a default “1"...
  • Page 5: Clock Generator Circuit

    The Receiver – GD16556 General Clock Generator Circuit Hence, the overall transponder system will be well within the jitter specifications. The GD16556 is an on-the-fly program- The clock generator circuit in the mable multi-bitrate CDR and 1:16 de- Select pins are LVTTL compatible. The GD16556 contains two independent di- multiplexer with emphasis put on tran- LVTTL inputs are internally pulled high...
  • Page 6 Assume the incoming line rate equals The binary output of either the PFD or LOCK_DET is asserted (set HIGH) if the 32/31 times 2.488 Gbit/s. Thus, the VCO the Bang-Bang Phase Detector (depend- VCO frequency differs from the reference frequency should equal 2.568 GHz. The ing of the mode of the lock-detection cir- frequency by ±500 ppm.
  • Page 7: Data Input

    This has been realised by counting the false bit transitions. If this counter runs out within a time period the BEF flag is From LINE set. The length of the counter may be set by external select signals (SBER0 and SBER1).
  • Page 8 The Transmitter – GD16557 General Digital “Wrapping” Modes In non-transponder applications the GD16557 may be operated with jitter The GD16557 is an on-the-fly program- The fraction is chosen by the signals clean-up (including VCXO) or without mable multi-bitrate multiplexer with em- MSEL1 and MSEL2.
  • Page 9 Forward Clocking Scheme This resulting jitter free VCO (locked to Leakage current can occur from the the VCXO) is locked to the forward clock charge pump in PFD1 or from input leak- GD16557 has been designed as a re- using PFD1 as shown below. This en- age current into the VCXO.
  • Page 10 +3.3V Supply +5V Supply CHAP GD16557 GD16578 VCXOCHAP 50 Line DINQ XCK1 XCK1N DINT VCXO CHAP 100nF VCOCHAP 20mA 2.4kW Figure 16.GD16557/GD16578 DC-connection VDDA VCTL +3.3V Supply -5.2V Supply Figure 19.GD16557 - Loop filters GD16557 GD16578 Note: Values for “R1” and “C1” de- pend on the specific VCXO.
  • Page 11: Lock Detect

    Lock Detect wide (typ. 2 MHz) for suppression of the intrinsic phase noise present in the VCO. Each PLL is equipped with a LVTTL lock detect output that signals whether or not the PLL is locked. A logic “1" indicates no Jitter Generation lock and a logic ”0"...
  • Page 12 Standard Bit Rate “Wrap” fraction VCXO Centre GD16556 select pin settings GD16557 select pin settings Frequency RSEL1/2 MSEL1/2 RSEL1/2 MSEL1/2 [MHz] STM-1 / OC 3 38,880000 “10" “11" “10" “11" None. STM-4 / OC 12 38,880000 “01" “11" "01" "11" Only standard bit STM-16 / OC 48 38,880000...
  • Page 13 Standard Bit Rate “Wrap” fraction VCXO Centre GD16556 select pin settings GD16557 select pin settings Frequency RSEL1/2 MSEL1/2 RSEL1/2 MSEL1/2 [MHz] STM-1 / OC 3 40,134194 “10" "11" “10" "10" STM-4 / OC 12 40,134194 "01" "11" "01" "10" 32/31 on receiving side STM-16 / OC 48 40,134194...
  • Page 14 Pin List GD16556 - Receiver (continued on next page) Mnemonic: Pin No.: Pin Type: Description: DI, DIN 16, 14 ANALOG input Differential AC or DC coupled data inputs to the Limiting Amplifier. Pins DI/DIN may be swapped with pins DIREF/DIREFN respec- tively.
  • Page 15 Mnemonic: Pin No.: Pin Type: Description: CKREFB, CKREFBN 81, 80 LVDS input Differential. CDR reference clock. In transponder systems CKREFA or CKREFB should be connected to the output signal RECCK from the GD16557 device. The input impedance is 100 W differential.
  • Page 16 Package Pinout - GD16556 VDDV CKON CDRSEL MSEL1 LBCKN MSEL2 LBCK LBEN VDDO VDDL DO0N VDDL VEEL DO1N DIREFN DO2N VEEL DO3N DIREF DO4N BPEN DO5N SBER0 SBER1 DO6N LD_SEL DO7N Figure 23.Package pinout, 100 pin. Top view. Data Sheet Rev.: 23 GD16556/GD16557* Page 16 of 28...
  • Page 17 Pin List GD16557 - Transmitter (continued on next page) Mnemonic: Pin no.: Pin type: Description: DI0N 34, 35 LVDS input Differential data inputs. The input impedance is 100 W differential. DI1N 36, 37 (Terminated on-chip with 100 W resistor). DI2N 38, 39 DI3N 40, 41...
  • Page 18 Mnemonic: Pin no.: Pin type: Description: VCTL ANALOG input. Voltage Control pin for VCO. Connect the VCO loop-filter to this pin. VCXOCHAP PCMOS output. Connect the VCXO loop-filter to this pin. This output will source current when the VCXO increases the frequency and sink current when the VCXO decreases the frequency.
  • Page 19 Package Pinout - GD16557 VEEA BPEN CKIN PHA1 PHA2 RECCK RSEL1 RECCKN RSEL2 CKON DI15N DI15 DI14N DI14 DI13N DI13 DI12N DI12 DI11N VCMLT1 DI11 DI10N DI10 LBCK DI9N VCMLT2 LBCKN DI8N LBEN Figure 24.Package Pinout, 100 pin. Top view. Data Sheet Rev.: 23 GD16556/GD16557* Page 19 of 28...
  • Page 20: Maximum Ratings

    Maximum Ratings These are the limits beyond which the component may be damaged. All voltages in the table refer to V All output signal currents in the table are defined positive out of the pin. Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT: Power supply...
  • Page 21 DC Chararacteristics = -5 °C to +75 °C (For /ECL version T = -5 °C to +90 °C). CASE CASE All voltages in the table are referred to V EE . All input signal and power currents in the table are defined positive into the pin. All output signal currents are defined positive out of the pin.
  • Page 22 Note 3: All LVTTL inputs are provided with an internal pull-up resistor R = 16 kW connected to V giving a default logic “1" LVTTL when not connected. Note 4: Under the condition of typical supply voltage (3.3 V). Note 5: The LVDS input is LVPECL compatible.
  • Page 23 AC Characteristics - General = -5 °C to +75 °C (For /ECL version T = -5 °C to +90 °C). CASE CASE Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT: LVDS rise time Note 1 LVDS LVDS fall time Note 1 LVDS LVPECL rise time Note 3...
  • Page 24 AC Characteristics - GD16556 = -5 °C to +75 °C (For /ECL version T = -5 °C to +90 °C). CASE CASE Figure 25.Low-speed Output Timing. LBCK LBCKN Figure 26.Loop-back Timing. Symbol: Characteristic: Conditions: MIN.: TYP.: MAX.: UNIT: Jitter transfer Note 1 TRANSFER Jitter transfer...
  • Page 25 ITU-T Specs. ITU-T Specs. 20dB/dec. 0.15 100k Figure 27.Jitter Transfer Figure 28.Jitter Tolerance with 2 dB Power Penalty @ BER = 1E-10 Data Sheet Rev.: 23 GD16556/GD16557* Page 25 of 28...
  • Page 26 AC Characteristics - GD16557 = -5 °C to +75 °C (For /ECL version T = -5 °C to +90 °C). CASE CASE CNTCK CNTCK CNTCK CNTCK CNTCK CNTCK PHA1,2 = 1,1 DIxx PHA1,2 = 0,0 DIxx PHA1,2 = 1,0 DIxx PHA1,2 = 0,1 DIxx Figure 29.Low-speed input timing.
  • Page 27: Package Outline

    Package Outline Figure 32.100 pin TQFP-EDQUAD. All dimensions are in mm. Device Marking GD16556/<Option> GD16557/<Option> <Design ID> <Design ID> <Wafer ID>-<Wafer Lot#> <Wafer ID>-<Wafer Lot#> <Assembly Lot#>-<YYWW> <Assembly Lot#>-<YYWW> <FPO #> <FPO #> Pin 1 - Mark Pin 1 - Mark Figure 33.Device marking.
  • Page 28: External References

    GD16557/ECL-100BA Transmitter with LVPECL I/O 100 pin TQFP-EDQUAD -5...+90 °C GD16556/GD16557*, Data Sheet Rev.: 23 - Date: 3 June 2002 an Intel company Distributor: The information herein is assumed to be Mileparken 22, DK-2740 Skovlunde reliable. GIGA assumes no responsibility...

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