an Intel company
General Description
The GD16556 and GD16557 constitute a
high performance multi-bitrate tran-
sponder chip set designed for Optical
Network applications. The devices are
available with either LVDS or LVPECL
low-speed I/Os.
The chip set is compatible with the line
rates:
SDH STM-1 / SONET OC3
u
SDH STM-4 / SONET OC12
u
SDH STM-16 / SONET OC48
u
Gigabit Ethernet
u
Switching between the bit rates is possi-
ble on-the-fly through select pins.
The chip set is designed for interconnect-
ing the high-speed line interface to stan-
dard CMOS ASICs or FPGAs. The
on-chip VCO and PLL blocks eliminate
external high-speed clock signals and
complicated timing relations.
Digital "Wrapping" Modes
GD16556 and GD16557 are capable of
transmitting and receiving data at in-
creased rates if overhead is needed for
16
STM-1 / OC3
STM-4 / OC12
STM-16 / OC48
GD16556
Gigabit
CDR &
Ethernet
DeMUX 1:16
Times:
1,
15/14,
16/15,
32/31
Line
Side
STM-1 / OC3
STM-4 / OC12
GD16557
STM-16 / OC48
Jitter
Gigabit
Cleaner &
Ethernet
MUX 16:1
Times:
1,
15/14,
16/15,
32/31
VCXO
system level service purposes. The de-
vices can operate with STM-1 (OC3),
STM-4 (OC12), STM-16 (OC48) and
Gigabit Ethernet line rates multiplied by a
fraction. Fractions available are 32/31,
16/15 and 15/14. Thus, for example, data
might be transmitted (or received) at a
rate of 32/31 times 2.488 Gbit/s with a
high- speed clock of 2.568 GHz. The
fractions are available through selection
of programmable dividers.
Signal Levels and Power Supply
Low speed interfaces are LVDS/LVPECL
compatible. The high-speed output from
the transmitter GD16557 is of CML-type
(open collector). Select pins are LVTTL
compatible.
Low power consumption is achieved by a
single +3.3 V power supply and by omit-
ting all circuitry, which can easily be im-
plemented in the low speed system
ASIC.
The devices are housed in 100 pin TQFP
EDQUAD thermal enhanced packages.
16
System
ASIC
Clock
Clock
VCXO
Clock
Clock
16
16
System
ASIC
Clock
Clock
Clock
Clock
STM-1/OC3
GD16557
STM-4/OC12
Jitter
STM-16/OC48
Cleaner &
Gigabit
MUX 16:1
Ethernet
System
Side
STM-1/OC3
STM-4/OC12
GD16556
STM-16/OC48
CDR &
Gigabit
DeMUX 1:16
Ethernet
2.5 Gbit/s
Transponder
Chip Set with
Digital "Wrapping"
GD16556/GD16557*
Preliminary
Features
General
SDH (SONET) STM-1(OC3) /
l
STM-4(OC12) / STM-16(OC48) / GE
compatible
True on-the-fly multi-bit rate operation
l
Bypass for non-compatible bit rates
l
Loop-back for system test mode
l
Overhead data rate capability
l
– 15/14 (7% overhead)
– 16/15 (6% overhead)
– 32/31 (3% overhead)
LVDS/LVPECL low-speed I/O
l
Single power supply: +3.3 V
l
100 pin TQFP EDQUAD packages
l
GD16556 (Receiver)
Clock and Data Recovery
l
1:16 Demultiplexer
l
Differential input with 5 mV
l
sensitivity
Loss of signal monitor
l
Bit consecutive monitor
l
Lock detect monitor
l
Power dissipation: 1.3 W (typ.)
l
GD16557 (Transmitter)
16:1 Multiplexer
l
Optional double PLL jitter-clean up
l
Counter or forward clocked
l
low-speed interface
PLL lock-detect
l
Power dissipation: 1.3 W (typ.)
l
Applications
Digital "Wrappers"
l
Optical Networking
l
Transponders
l
SDH/SONET FEC out-of-band
l
systems
Network interconnects
l
Gateways
l
Datacom
l
*: Patent pending
Data Sheet Rev.: 23
PP
Need help?
Do you have a question about the GIGA GD16556 and is the answer not in the manual?
Questions and answers