Automatic Tuning - JRC JRL-2000F Service Manual

Hf linear amplifier
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(3)SWR Detector Circuit
Vf and Vr detected by the output power detector circuit of CFG-111 are compared by
comparator IC15.
When the VSWR value which is a ratio of Vf to Vr, exceeds 3.5, No.4 pin of IC15
becomes Low level to inform CPU of the SWR alarm (A8).
On the other hand, Vf and Vr are applied to the SWR operating circuit made up of
IC14, IC17 and peripheral parts. The calculated SWR is indicated in the voltmeter on
the front panel.
The circuit made up of IC15, CD6, R54, R55 and C67 holds the peak of Vf.
Data selector IC of lC10 selects signals which are connected to the front panel meter.
Comparator IC16 which has an output terminal (No.8 pin) compares Vf with the refer-
ence voltage adjusted by the variable resistor RV1
.
If Vf exceeds the reference volt-
age, an ALC voltage is generated.
The ALC voltage moves the pointer of the voltmeter via diode CD5 and it is inversely
amplified to a negative voltage by IC17 operational amplyfier and then sent to the
exciter.
(4)Frequency Measurement Circuit
The RF signal from the exciter, which is detected by the CSC-433 antenna switch
circuit, is applied to J410, and is then amplified by transistor TR2.
The signal is wave-shaped to the rectangular wave by the IC23 two-stage buffer
amplifier.
After the divider of IC11 divides this signal ten times, it is applied to the timer IC of
IC4.
IC4 is controlled by CPU and measures frequency of the exciter output signal by
counting this signal.
2.7 Automatic Tuning
The CDJ-1143 control CPU of the JRL-2000F automatically tunes the antenna by
controlling relays of the CFG-111 matching circuit according to the program written to
ROMI
.
\
SET and TUNE operations will be described here.
When the SET switch is pressed, No.11 pin (SELBK) of the CDJ-1143 control J3
changes to Low level and requires power from the exciter.

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