Pioneer DEH-345RX1M/EW Service Manual page 62

DEH-345R,344R,343R
@ Pin Functions (UPD63702AGF)
Pin No. | Pin Name /O Function and Operation
1_|D.VDD Supplies current of positive voltage to the logic circuits
2_| RST System reset input pin
3 | AO Microcomputer interface
AO="L": STB active and set to address register
AO="H": STB active and set to parameter
4 | STB Signal to latch serial data within the LSI
5 | SCK Clock input pin to input and output serial data
6 |SO ie} Outputs serial data and status signal
7_[ SI Serial data input pin
8 | D.GND Logic circuit GND
9 | X.GND Crystal oscillation circuit GND
10_| XTAL Crystal oscillator connection pin
11 | XTAL Oo Crystal oscillator connection pin
12__| X.VDD Supplies current of positive voltage to the crystal oscillation circuit
13_ | DA.VDD Supplies current of positive voltage to the D/A converter
14 | R+ {eo} Right channel analog audio data output pin
15 | R- oO Right channel analog audio data output pin
16,17__| DA.GND D/A converter GND
18 | L- oO Left channel analog audio data output pin
19 | L+ oO Left channel analog audio data output pin
20_| DA.VDD Supplies current of positive voltage to the D/A converter
21_|D.VDD Supplies current of positive voltage to logic circuit
22 | FLAG oO Flag output pin to indicate that audio data currently being output consists of
noncorrectable data
23 | WOCK ie} Pin to output double the frequency of LRCK
24 | C16M fe] Pin to output the clock
25 | EMPH oO Output pin for the pre-emphasis data in the sub-O code
26 | DIN | Input pin for serial audio data
27_| DOUT ie} Output pin for the serial audio data
28 | SCKO ie} Output pin for the clock for the serial audio data
29 | LRCK oO Signals to distinguish the right and left channels of the audio data output
from DOUT. Frequency is 44.1kHz at 50% duty at normal regeneration
30_| TX ie] Output pin for the digital audio interface data
31 | CTLV | Oscillation control pin for high-frequency clock generation VCO used for the
digital PLL upon regeneration at fast speed of 2- or 4-fold
32__| POUT ie) Output point for phase comparison
33_ | D.GND GND for the logic circuit
34 | VCO | Input pin for the inverter
35 | VCO ie} Output pin for the inverter
36_ | D.VDD Supplies current of positive voltage to the logic circuit
37__ | PLCK oO Pin for monitoring the bit clock
38 | LOCK Oo Indicates "H" when the synchronized pattern detection signal matches the
frame counter output at the EFM recovery modulation, and "L" when they
don't match
39 | WFCK oO Minute-cycle signal for the bit clock, the signal indicates the cycle of 1 frame
(approx. 7.35kHz)
40 | RFCK oO Minute-cycle signal for the clock, the signal indicates cycle of 1 frame
(approx. 7.35kHz)
41_ | D.GND GND for the logic circuit
42,43 | TESTO,1 | Test pins
44,45 | TM2, TM4 | Pins for controlling regeneration at fast speed of 2- or 4-fold
46-49 | T4-T7 | Test pins
50,51 | C1D1, C1D2 ie} Output pin for indicating the C1 error correction results
52-54 | C2D1-C2D3 ie} Output pin for indicating the C2 error correction results
55 | D.VDD Supplies current of positive voltage to the logic circuit
56 | SFSY ie} Outputs 1 word of the subcode. Generally, 1 cycle is approx 136 micro seconds
57 | SBSY O The signal indicates the beginning of the subcode block. The SFSY signal is
output at high level every 98 times
58 | SBSO ie] Output pin for the subcode data
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