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PNX85500x
TS input
CI/CA
TS out/in for
PROCESSOR
PCMCIA
DVB-T/C
DVB
channel decoder
VIDEO
CVBS, Y/C,
DECODER
RGB
Low-IF
DIGITAL IF
MPEG/H.264
AUDIO DEMOD
SSIF, LR
AND DECODE
SPDIF
AUDIO IN
HDMI
HDMI
RECEIVER
SYSTEM
CONTROLLER
(8051)
2
I
C
GPIO
IR
Figure 7-9 PNX85500 functional diagram
Circuit Descriptions
MEMORY
CONTROLLER
MPEG
SYSTEM
PRIMARY
VIDEO
OUTPUT
AV-PIP
SUB-PICTURE
3D COMB
SECONDARY
VIDEO
OUTPUT
Motion-accurate
VIDEO
pixel processing
DECODER
SCALER,
DE-INTERLACE
AND NOISE
REDUCTION
AUDIO DSP
450 MHz
AV-DSP
560 MHz
DRAWING
MIPS32
ENGINE
24KEf CPU
DMA BLOCK
2
ADC
SPI
UART I
C
GPIO Flash
USB 2.0
x 8
back to
div. table
Q552.1L LA
LVDS for
flat panel display
LVDS
(single, dual or
quad channel)
VIDEO
analog CVBS
ENCODER
AUDIO DACS
analog audio
2
I
S
AUDIO OUT
SPDIF
SD
Ethernet
Memory
MAC
Card
7.
EN 53
18770_241_100201.eps
100219
2010-Dec-29
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