Chipset Overview - Supero SUPER P4STA User Manual

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Chipset Overview

Intel's 850 chipset is made up of three main components:
*82850 Memory Controller Hub (MCH) with Accelerated Hub Architecture
(AHA) bus,
*82801 BA I/O Controller Hub (ICH2) with AHA bus,
*82802 AB Firmware Hub (FWH).
Memory Controller Hub (MCH)
The MCH includes the host (CPU) interface, RDRAM interface, ICH interface
and 4xAGP interface for the 850 chipset.
management logic and supports dual channels for RDRAM. The AGP 2.0
interface supports 4x data transfers and operates at a peak bandwidth of
1056 GB. The MCH host interface bus runs at 100 MHz.
I/O Controller Hub (ICH2)
The ICH2 is the I/O Controller Hub subsystem on the P4STA, which inte-
grates many of the Input/Output functions of the 850 chipset, including a
two-channel ATA-33/66/100 Bus Master IDE controller. It also provides the
interface to the PCI Bus and communicates with the MCH over a dedicated
hub interface bus-the AHA. The P4STA has the more powerful ICH2, which
includes a dual channel IDE controller and two USB controllers that offer 24
Mbps of bandwidth across four ports.
AC'97 interface that supports full surround sound for the Dolby Digital Audio
used on DVDs.
Firmware Hub (FWH)
The FWH is a component that brings added security and manageability to
the PC platform infrastructure. This device includes an integrated Random
Number Generator (RNG) for stronger encryption, digital signing and secu-
rity protocols. The FWH stores the system BIOS and video BIOS to eliminate
a redundant nonvolatile memory component.
It contains advanced power
ICH2 also features an enhanced
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Chapter 1: Introduction