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Inova ICP-PIII User Manual

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ICP-PIII
High-Performance
CPU Boards
USER'S MANUAL
Publication Number: PD00581013.004 AB
MAN-ICP-PIII

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Summary of Contents for Inova ICP-PIII

  • Page 1 ICP-PIII High-Performance CPU Boards USER’S MANUAL Publication Number: PD00581013.004 AB MAN-ICP-PIII...
  • Page 2 The content of this user’s manual is furnished for informational use only, is subject to change without notice, and should not be constructed as a commitment by Inova Computers GmbH. Inova Computers GmbH assumes no responsibility or liability for any errors or inaccuracies that may appear in this user’s manual.

  • Page 3: Table Of Contents

    1.04 Graphics ....................1-3 1.1 Specifications ......1-4 1.2 Configuration ......1-6 Table 1.20 ‘Processor Overview ....................1-6 Figure 1.20 ICP-PIII Overview ..................... 1-7 1.3 Software ........ 1-8 1.31 Linux ......................1-8 1.32 VentureCom ..................... 1-8 1.33 Windows 2000 ..................1-8 1.34 Windows CE .....................
  • Page 4 Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard) ......3-5 Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A) ..... 3-6 Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B) ...... 3-7 Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C) .....
  • Page 5 Preface ICP-PIII 3.1 CompactPCI Backplane ..3-10 Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot ........ 3-11 3.2 Interfaces ......3-12 3.21 J7 & J12 Fast Ethernet ................3-12 Figure 3.21 RJ45 Pinout ......................3-12 Table 3.21 Ethernet Connector Signals ..................3-12 3.22 J17 VGA Interface ...................
  • Page 6 Table B1.7 Mouse Connector Signals..................B-7 B1.8 COM1 & COM 2 Interfaces ..............B-8 Figure B1.8 COM1 & COM2 Interface Pinout ................B-8 Table B1.8 COM1 & COM2 Connector Signals ................B-8 Page 0-4 ©2002 Inova Computers GmbH Doc. PD00581013.004...
  • Page 7 D1.2 IPB-RIO-HD-LPT-(FLEX) ................D-3 Figure D1.2 IPB-RIO-HD-LPT-(FLEX) .................... D-3 D1.3 IPB-RIO-C-SHORT ................... D-4 Figure D1.3 IPB-RIO-C-SHORT ....................D-4 Table D1.3 Rear I/O Type ‘C’ ..................... D-4 D1.4 IPB-RIO-C-80MM ..................D-5 Figure D1.4 IPB-RIO-C-80MM ....................D-5 Doc. PD00581013.004 ©2002 Inova Computers GmbH Page 0-5...

  • Page 8: Unpacking And Special Handling Instructions

    Company name, contact person, shipping address and invoice address í Product name and serial number í Failure or fault description í Clearly write the RMA number on the outside of the transportation carton. Page 0-6 ©2002 Inova Computers GmbH Doc. PD00581013.004...

  • Page 9: Revision History

    Preliminary, First Release; All pages revised 31/11/2000 PD00581013.002 Updated to include Radeon VE and Rear I/O options 15/08/2001 PD00581013.003 Final Version - Included Appendix A-D I/O Modules 21/09/2001 PD00581013.004 Specs. Updated & Rear I/O Table Corrected 15/02/2002 Doc. PD00581013.004 ©2002 Inova Computers GmbH Page 0-7...

  • Page 10: Three Year Limited Warranty

    Inova Computers (‘Inova’) grant the original purchaser of Inova products the following hardware warranty. No other warranties that may be granted or implied by anyone on behalf of Inova are valid unless the consumer has the expressed written consent of Inova.
  • Page 11 1.04 Graphics ....................1-3 1.1 Specifications ......1-4 1.2 Configuration ......1-6 Table 1.20 ‘Processor Overview ....................1-6 Figure 1.20 ICP-PIII Overview ..................... 1-7 1.3 Software ........ 1-8 1.31 Linux ......................1-8 1.32 VentureCom ..................... 1-8 1.33 Windows 2000 ..................1-8 1.34 Windows CE .....................

  • Page 12: Icp-Piii Cpu

    Fast Ethernet, FireWire and USB. To enable so much functionality to exist in such a small footprint, the ICP-PIII is able to host the I/O on either the front-panel or in the form of rear I/O or even both. Implementing the latest Intel chipsets and processors available for the embedded market the ICP-PIII is adequately equipped to provide support for all major operat- ing systems and off-the-shelf application software.

  • Page 13: Interfacing

    & hardware MPEG-2 support, enables screen resolutions up to 2048 x 1536 pixels to be driven. Dual video and TFT dual-scan/single-scan colour panels are supported with configurable colour depths. In addition, Inova’s ICP-PIII caters for the needs of the GigaST R, PanelLink™ and LVDS user.

  • Page 14: Graphics

    CRT / TFT resolutions up to 2048x1536 GigaST R / PanelLink™ or TFT Piggyback Dual display option or TFT will require dedicated front-panel. Recovery BIOS FLASH Recovery BIOS Watchdog Programmable up to 10 minutes; issues NMI or Reset Page 1-4 ©2002 Inova Computers GmbH Doc. PD00581013.004...
  • Page 15 *Note: Any CPU fitted with HD, FD or CD-ROM etc. has a max. operational temperature of 50 ≤ 700MHz. CPUs without HD or PC inter faces ar e single-slot (4TE) for ‘pr ocessor speeds Mobile processors are passively cooled - installation MUST have >0.3m/s air flow! Doc. PD00581013.004 ©2002 Inova Computers GmbH Page 1-5...

  • Page 16: Configuration

    ICP-PIII 1.2 Configuration Inova’s high-performance, high-density 3U PIII board supports functionality and connectivity on all three major serial networking levels like Fast Ethernet, FireWire and USB as well as most state-of- the-art fieldbus standards such as PROFIBUS, CAN, Interbus, and LON.
  • Page 17 In order to take full advantage of the rear I/O features, the CompactPCI back- plane needs to support them. Inova provides two standard versions; one has the J2 connector at the CPU location extended to the rear of the backplane while the other version has all slots fitted with the J2 connector on both the front and rear.

  • Page 18: Software

    Accelerated Graphics Port (AGP), multiple video cards and monitors, OpenGL 1.2, DirectX® 7.0 API, and Video Port Extensions. With Plug and Play automatic installation of new hardware is possible with only minimal configu- ration. More than 12,000 devices now support this functionality. Page 1-8 ©2002 Inova Computers GmbH Doc. PD00581013.004...

  • Page 19: Windows Ce

    (native processor speed) or hard real-time performance. In addition, advanced features are implemented such as modularity, hot updates, deadline-driven scheduling admission testing as well as a fast and pro- ductive cross-development. Doc. PD00581013.004 ©2002 Inova Computers GmbH Page 1-9...

  • Page 20: Hardware

    Disk-On-Chip™ FLASH (BIOS) This block diagram is applicable to all Inova’s PIII-based CPUs. Components and/or functionality may change without notice. An extra PCI load can be attached to the on-board 80-pin header. An open specification is available allowing developers to manufacture their own PCI device.

  • Page 21: Connector Location

    Table 1.43 Connector Description Connector Description J1, J2 CompactPCI Interface Connector J3, J4 SDRAM Piggyback Expansion Interface Connector for up 384MBytes PCI Expansion Slot 10BaseT/100BaseTx Fast Ethernet Interface Optional Independent 10BaseT/100BaseTx Fast Ethernet Interface Doc. PD00581013.004 ©2002 Inova Computers GmbH Page 1-11...

  • Page 22: Front-Panel Features

    GigaSTAR 9-Pin D-Sub on 4TE CPU Front-Panel or 8TE CPU Front-Panel The physical COM2 interface is missing on Inova’s IPB-FPE8 piggyback allowing a PCI piggyback device to be installed. If this piggyback is installed the hard-disk (IDE FLASH) must be installed as stand-alone Page 1-12 ©2002 Inova Computers GmbH...
  • Page 23 8TE front-panel is selected. Both COM ports are installed on Inova’s HD or IDE FLASH carrier board. A piggyback with COM1, mouse and keyboard is also available allowing the lower 9-pin D-Sub connector position to be used for a PCI- based piggyback.

  • Page 24: Interface Positions

    Figure 1.45 shows the typical positioning of the front panel extension modules for mouse, key- board, COM1, COM2, LPT1 and COM2/Fieldbus interfaces. Note A hard disk, if installed, will generally be fitted to the piggyback containing the mouse, keyboard, COM1 and COM2 interfaces. Page 1-14 ©2002 Inova Computers GmbH Doc. PD00581013.004...
  • Page 25 2.2 Memory Mapped Peripherals ..2-5 2.3 Interrupt Routing ....2-5 Table 2.30 PC-AT Interrupt Definitions ..................2-6 2.4 Inova PIII Device List ....2-7 Table 2.40 Legacy I/O Map (ISA Compatible) ................2-7 2.5 Interrupt Configuration .... 2-8 Table 2.50 CompactPCI Bus Interrupts ..................2-8 2.6 Timer / Counter .......

  • Page 26: Memory Map

    CGA Screen Memory B8000h MDA Screen Memory B0000h VGA Screen Memory A0000h Free User 640 kByte Memory Conventional Memory System Data 00000h The UMB reservation may be set up with the BIOS Page 2-2 ©2002 Inova Computers GmbH Doc. PD00581013.004...
  • Page 27 UMB Reservations for ISA Start Address Finish Address 0CC00h 0CFFFh 0D000h 0D3FFh 0D400h 0D7FFh 0D800h 0DBFFh 0DC00h 0DFFFh Table 2.01 Port Addressing Port Addressing Port Address COM1 3F8h COM2 2F8h LPT1 378h Doc. PD00581013.004 ©2002 Inova Computers GmbH Page 2-3...

  • Page 28: I/O Mapped Peripherals

    CompactPCI systems permit the full 16-bit addressing capability of the Intel 80x86 ‘processors, from 0h to 0FFFFh. All Inova CPU boards include peripheral devices requiring I/O address space on board and hence the BIOS automatically assigns the I/O address required by peripheral boards and PCI devices at boot time based on the requirements of each device.

  • Page 29: Memory Mapped Peripherals

    Intel 80x86 memory map from 0h to 0FFFFFFh. Inova’s CompactPCI systems allow the full 32-bit addressing capability of the Intel Pentium/Celeron range of ‘processors so that memory mapped peripheral devices may be mapped locally to the ‘processor board at any location in the memory map not being used by other devices (e.g.
  • Page 30 LPT1 IRQ8 Real-Time Clock IRQ9 Redirected IRQ2 IRQ10 IRQ11 Ethernet/FireWire IRQ12 Reserved IRQ13 Co-processor IRQ14 Hard Disk (IDE 0) IRQ15 IDE 1 Entries may be reserved for ISA devices with the BIOS Page 2-6 ©2002 Inova Computers GmbH Doc. PD00581013.004...

  • Page 31: Inova Piii Device List

    2.4 Inova PIII Device List Table 2.40 shows the available PCI devices both on-board and off-board (CompactPCI backplane). It should be noted that the interrupt routing assumes a standard Inova backplane configuration with a right-hand system slot. Table 2.40 Legacy I/O Map (ISA Compatible)

  • Page 32: Interrupt Configuration

    Table 2.50 CompactPCI Bus Interrupts CompactPCI CompactPCI Bus Interrupts Bus Interrupts INTA# INTB# INTC# INTD# INTP ( IRQ14 ) Serialized Interrupt INTS Refer to BIOS Documentation ENUM# ( IRQ5 ) Page 2-8 ©2002 Inova Computers GmbH Doc. PD00581013.004...

  • Page 33: Timer / Counter

    The BIOS featured in Inova’s CPUs programs the system timer tick for PC compatibility. The inter- rupt generated by the timer creates an interrupt request on IRQ0 of the programmable interrupt controller (PIC) which is serviced by the CPU as interrupt vector 08h.
  • Page 34 Configuration ICP-PIII This page has been left blank intentionally. Page 2-10 ©2002 Inova Computers GmbH Doc. PD00581013.004...
  • Page 35 Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard) ......3-5 Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A) ..... 3-6 Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B) ...... 3-7 Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C) .....
  • Page 36 3.29 J14 FLASH Interface ................3-19 3.30 J18 Floppy Disk Interface ................ 3-19 3.31 Connecting the PIII to the Inova IPB-FPE8 ..........3-20 Figure 3.31 CPU to IPB-FPE8 Connection .................. 3-20 3.32 Connecting the PIII to the Inova ICP-HD-1 ..........3-21 Figure 3.32 CPU to ICP-HD-1 Connection.................

  • Page 37: Compactpci J1/J2 Connector

    Figure 3.01 The 32-Bit CompactPCI Bus Interface Connector 3.02 ICP-PIII Connector J1 and J2 Inova’s ICP-PIII CPU board has been designed as a 32-bit system slot device able to operate in either +5V or +3.3V (I/O) systems. The CompactPCI backplane connector is keyed accordingly (yellow for +3.3V and blue for +5V.)
  • Page 38 Interfaces ICP-PIII Table 3.02 Inova’s ICP-PIII 32-Bit CompactPCI J1 Pin Assignment Pin Nr Row A Row B Row C Row D Row E REQ64# Pull- J1-25 ENUM# +3.3V Up V( I / O ) ACK64# Pull- J1-24 AD[1] V( I / O )
  • Page 39 ICP-PIII Interfaces Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard) Pin Nr Row A Row B Row C Row D Row E J2-22 J2-21 CLK6 J2-20 CLK5 J2-19 J2-18 J2-17 PRST# REQ6# GNT6# J2-16 (UBAT) J2-15 REQ5# GNT5#...
  • Page 40 Interfaces ICP-PIII Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A) Pin Nr Row A Row B Row C Row D Row E J2-22 J2-21 CLK6 ETH_TxF+ ETH_TxF- ETH_R45 J2-20 CLK5 COM 2- ETH_R78 J2-19 COM 2+...
  • Page 41 ICP-PIII Interfaces Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B) Pin Nr Row A Row B Row C Row D Row E J2-22 J2-21 CLK6 ETH_TxF+ ETH_TxF- ETH_R45 J2-20 CLK5 ETH_R78 J2-19 ETH_RxF+ ETH_RxF- J2-18...
  • Page 42 Interfaces ICP-PIII Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C) Pin Nr Row A Row B Row C Row D Row E J2-22 J2-21 CLK6 FW_TPA+ FW_TPA- HCS0# J2-20 CLK5 HADR0 HRST# J2-19 HADR1 FW_TPB+...
  • Page 43 ICP-PIII Interfaces Table 3.07 Inova’s ICP-PIII Rear I/O J2 (CPU) Integration REAR I/O Rear I/O OPTION STANDARD ETHERNET Both COM 1/2 Both (TTL) (RS485) USB 1/2 Both USB 2 FireWire 2 LPT 1 SPEAKER BATTERY EIDE Currently three forms of rear I/O are available and, depending on the version currently in use, decides which (if any) of the J2 signals are available to the rear J2 connector.

  • Page 44: Compactpci Backplane

    The System Slot is responsible for performing system initialization by managing each local board’s IDSEL signal. Physically, the System Slot may be located at either end of the backplane but Inova have placed theirs on the right to cater for physical expansion due to heat-sink, hard disk, extended function- ality etc.

  • Page 45: Interfaces

    ICP-PIII Interfaces Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot Z A B C D E F Z A B C D E F Z A B C D E F Z A B C D E F...

  • Page 46: J7 & J12 Fast Ethernet

    Users taking advantage of the CPU’s rear I/O options are advised not to use the front-panel interface if the rear interface is being used. Possible damage to the board could occur and data integrity cannot be assured. Page 3-12 ©2002 Inova Computers GmbH Doc. PD00581013.004...

  • Page 47: J17 Vga Interface

    PCI, PanelLink or GigaST R piggyback. The 15-pin high-density D-Sub connector forms the physical interface for the video on the ICP-PIII which is based on either the Silicon Motion Lynx3DM graphic accelerator equipped with 8MByte RAM or the Radeon VE controller with 16MByte RAM.
  • Page 48 60 to 80 60 to 80 60 to 80 1920x1200 60 to 85 60 to 85 60 to 85 1920x1440 60/75 60/75 60/75 2048x1536 Colour Depth Resolution 65, 000 16.7M 640x480 800x600 1024x768 1280x1024 Page 3-14 ©2002 Inova Computers GmbH Doc. PD00581013.004...

  • Page 49: J16 Panellink Interface

    J16 is available if requested at time of order and replaces the standard VGA connector on the front- panel. Figure 3.23 PanelLink Interface Connector Table 2.12 PanelLink Interface Pin No. Signal Tx2- Tx1- Tx0- TxC- DDC Data 6, 7, 8, 9 +5V (<100mA) Tx2+ Tx1+ Tx0+ TxC+ DDC Clock Doc. PD00581013.004 ©2002 Inova Computers GmbH Page 3-15...

  • Page 50: J16 Gigastar Interface

    2.24 J16 GigaSTAR Interface The standard 9-pin D-Sub connector is used for GigaSTAR video transmission. Figure 2.24 GigaSTAR D-Sub Interface Pinout Table 2.11 GigaSTAR Interface Pin No. Signal GigaSTAR Tx+ GigaSTAR Tx- Page 3-16 ©2002 Inova Computers GmbH Doc. PD00581013.004...

  • Page 51: J19 Usb Interface

    Interfaces 3.25 J19 USB Interface J19 is located as standard on the front panel Figure 3.25 USB Interface Pinout Table 3.25 USB Connector Signals Pin No. Signal USB P0- USB P0+ Housing Doc. PD00581013.004 ©2002 Inova Computers GmbH Page 3-17...

  • Page 52: J15 Firewire Interface

    Table 3.26 FireWire Connector Signals Pin No. Signal IEEE 1394 S +12V ( 1A Fuse) IEEE 1394 S GND IEEE 1294 S TPB- IEEE 1394 S TPB+ IEEE 1394 S TPA- IEEE 1394 S TPA+ Housing Page 3-18 ©2002 Inova Computers GmbH Doc. PD00581013.004...

  • Page 53: J20 Infrared (Irda) Interface

    3.29 J14 FLASH Interface J14 is proprietary and not documented here 3.30 J18 Floppy Disk Interface J18 is proprietary and not documented here but observes the standard slim-line floppy pin-out. Doc. PD00581013.004 ©2002 Inova Computers GmbH Page 3-19...

  • Page 54: Connecting The Piii To The Inova Ipb-Fpe8

    Interfaces ICP-PIII 3.31 Connecting the PIII to the Inova IPB-FPE8 Appendix A provides more information on the IPB-FPE8 and its derivatives. Figure 3.31 shows how the CPU connects to the piggyback by a length of flex-cable. Figure 3.31 CPU to IPB-FPE8 Connection...

  • Page 55: Connecting The Piii To The Inova Icp-Hd-1

    ICP-PIII Interfaces 3.32 Connecting the PIII to the Inova ICP-HD-1 Appendix B provides more information on the ICP-HD-1 and its derivatives. Figure 3.32 shows how the CPU connects to the piggyback by lengths of flex-cable. Figure 3.32 CPU to ICP-HD-1 Connection...

  • Page 56: Connecting The Piii To The Inova Ipb-Fpe12

    Interfaces ICP-PIII 3.33 Connecting the PIII to the Inova IPB-FPE12 Appendix C provides more information on the IPB-FPE12 and its derivatives. Figure 3.33 shows how the CPU connects to the piggyback by a length of flex-cable. The illustration also shows the IPB-FPE8 connection (Appendix A) Figure 3.33 CPU to IPB-FPE12 Connection...

  • Page 57: Connecting The Piii To The Inova Ipb-Fpe12

    ICP-PIII Interfaces 3.34 Connecting the PIII to the Inova IPB-FPE12 Appendix C provides more information on the IPB-FPE12 and its derivatives. Figure 3.34 shows how the CPU connects to the piggyback by a length of flex-cable. The illustration also shows the ICP-HD-1 connection (Appendix B) Figure 3.34 CPU to IPB-FPE12 Connection...

  • Page 58: Connecting The Piii To The Icp-Fd-1

    ICP-PIII 3.35 Connecting the PIII to the ICP-FD-1 Figure 3.35 shows how the CPU connects to the slim-line floppy disk unit. Figure 3.35 CPU to Slim-Line Floppy Disk Connection Floppy PENTIUM III Page 3-24 ©2002 Inova Computers GmbH Doc. PD00581013.004...
  • Page 59 Figure A1.7 Mouse Interface Pinout .................... A-6 Table A1.7 Mouse Connector Signals ..................A-6 A1.8 COM1 Interfaces ..................A-7 Figure A1.8 COM1 Interface Pinout .................... A-7 Table A1.8 COM1 Connector Signals ..................A-7 CPU Appendix-A ©2001 Inova Computers GmbH Page A-1...

  • Page 60: A1 Ipb-Fpe8 Cpu Extension

    - all of which are discussed in this section. A1.2 IPB-FPE8 & Front-panel (4HP or 8HP) The Inova IPB-FPE8 interface is a small piggyback either as stand-alone with its own 4HP front- panel or integrated with the CPU as in figure A1.2.

  • Page 61: A1.3 Stand-Alone Ipb-Fpe8

    Also, pin 1 has been highlighted by a red triangle. Note: Damage to the CPU board or the piggyback may result if the flex cable is positioned incorrectly. Inova will not accept responsibility for negligent actions! Figure A1.3 Stand-Alone Piggyback Interface IPB-FPE8 Pin 1...

  • Page 62: A1.4 Ipb-Fpe8Ms (Theme Variation

    Mouse, Keyboard and COM1 J18A, J18B Floppy Disk (either a standard slim-line floppy connector or flex cable) * If connectors 9a and 10a are configured as Master then 9b and 10b must be Slave. Page A-4 ©2001 Inova Computers GmbH CPU Appendix-A...

  • Page 63: A1.5 Ipb-Fpe8Ms Description

    As mentioned previously, the IPB-FPE8MS has a number of additional features compared to the standard IPB-FPE8 module. These extra features include HD and FD connection with both standard connectors and the Inova flex cables. This provides the user with system flexibility. Figure A1.5 Top & Bottom Views of the IPB-FPE8MS...

  • Page 64: A1.6 Keyboard Interface

    CPU front-panel or available as a separate 4HP unit. The piggyback located behind these interfaces connects to the CPU-mounted J11 connector. Figure A1.7 Mouse Interface Pinout Table A1.7 Mouse Connector Signals Pin No. Signal Pin No. Signal Data Page A-6 ©2001 Inova Computers GmbH CPU Appendix-A...

  • Page 65: A1.8 Com1 Interface

    UART’s RTS signal. Writing a hex value of 0B to this register allows data to be transmitted. Writing 1B to this register configures the device to receive data. CPU Appendix-A ©2001 Inova Computers GmbH Page A-7...
  • Page 66 IPB-FPE8 Appendix A This page has been left blank intentionally. Page A-8 ©2001 Inova Computers GmbH CPU Appendix-A...
  • Page 67 Table B1.7 Mouse Connector Signals ..................B-7 B1.8 COM1 & COM 2 Interfaces ..............B-8 Figure B1.8 COM1 & COM2 Interface Pinout ................B-8 Table B1.8 COM1 & COM2 Connector Signals ................B-8 CPU Appendix-B ©2001 Inova Computers GmbH Page B-1...

  • Page 68: B1 Icp-Hd Cpu Extension

    J11 and J13 connects to the interface boards discussed in this section. B1.2 ICP-HD-1 & Front-panel (4HP or 8HP) The Inova ICP-HD-1 interface is an IDE device carrier board available as a stand-alone device with its own 4HP front-panel or integrated with the CPU as in figure B1.2.

  • Page 69: B1.3 Ide Carrier Board Icp

    Also, pin 1 has been highlighted by a red triangle. Note: Damage to the CPU board or the piggyback may result if the flex cable is positioned incorrectly. Inova will not accept responsibility for negligent actions! Figure B1.3 IDE Carrier Board ICP-HD1...

  • Page 70: B1.4 Icp-Hde8Ms (Theme Variation

    Figure B1.4 IDE Carrier ICP-HDE8MS J10A J18A J13A The ICP-HDE8MS shown in figure B1.4 enables connection of floppy, a CD-ROM and other pe- ripherals. The connector names and descriptions are declared in table B1.4. Page B-4 ©2001 Inova Computers GmbH CPU Appendix-B...
  • Page 71 LPT1. Both the ICP-HD-1 and ICP- HDE8 possess COM2 which is accessed through J13 connected to the CPU board. If the Inova IPB-FPE12 piggy- back is used and connected to J13a then the COM2 on the IDE carriers ICP-HD-1 and ICP-HDE8MS will be disabled.

  • Page 72: B1.5 Icp-Hde8Ms Description

    As mentioned previously, the ICP-HDE8MS has a number of additional features compared to the standard ICP-HD-1 module. These extra features include HD and FD connection with both stand- ard connectors and the Inova flex cables. This provides the user with additional system flexibility. Figure B1.5 Top & Bottom Views of the ICP-HDE8MS...

  • Page 73: B1.6 Keyboard Interface

    CPU front-panel or available as a separate 4HP unit. The piggyback located behind these interfaces connects to the CPU-mounted J11 connector. Figure B1.7 Mouse Interface Pinout Table B1.7 Mouse Connector Signals Pin No. Signal Pin No. Signal Data CPU Appendix-B ©2001 Inova Computers GmbH Page B-7...

  • Page 74: B1.8 Com1 & Com 2 Interfaces

    UART’s RTS signal. Writing a hex value of 0B to this register allows data to be transmitted. Writing 1B to this register configures the device to receive data. Page B-8 ©2001 Inova Computers GmbH CPU Appendix-B...
  • Page 75 Table B1.3 IPM-ATA-CF Jumper Description ................. B-5 B1.4 IPM-ATA-PCMCIA ..................B-6 Figure B1.4 IPM-ATA-PCMCIA Board Layout ................B-6 Table B1.4 IPM-ATA-PCMCIA Jumper Description ................ B-6 B1.5 Device Compatibility ................B-7 Table B1.5 Compatibility List ...................... B-7 CPU Appendix-B ©2001 Inova Computers GmbH Page B-1...

  • Page 76: B1 Ipm-Ata Cpu Extension

    Appendix B B1 IPM-ATA CPU Extension Inova Plug-In Module (IPM-) offers the user the ability to exchange a hard-disk for example with- out having to remove the CPU from the CompactPCI enclosure and then dismantle it etc. Cur- rently, three units exist that provide industry with hard-disk, Compact FLASH, MicroDrive or ATA PCMCIA mass storage capability.

  • Page 77: B1.1 J1 Interfaces (Contd

    3. Y-Cable for bringing the power from the CompactPCI backplane and to this and another device 4. Standard IDE ribbon cable (30cm) 5. Inova rear I/O module (IPB-RIO-IDE-FD) with IDE and slim-line FD connections CPU Appendix-B ©2001 Inova Computers GmbH...

  • Page 78: B1.2 Ipm-Ata-Hd

    CPU board itself). A Master device must be present either in the form of a hard- disk, Compact FLASH, MicroDrive or CD-ROM etc. Slave only configurations and multi Master configurations are not supported and will not work! Page B-4 ©2001 Inova Computers GmbH CPU Appendix-B...

  • Page 79: B1.3 Ipm-Ata-Cf

    CPU board itself). A Master device must be present either in the form of an external hard-disk, Compact FLASH, MicroDrive or CD-ROM etc. Slave only configurations and multi Master configurations are not supported and will not work! CPU Appendix-B ©2001 Inova Computers GmbH Page B-5...

  • Page 80: B1.4 Ipm-Ata-Pcmcia

    (the primary is on the CPU board itself). A Master device must be present either in the form of an external hard-disk, PCMCIA device, Compact FLASH, MicroDrive or CD-ROM etc. Slave only con- figurations and multi Master configurations are not supported and will not work! Page B-6 ©2001 Inova Computers GmbH CPU Appendix-B...

  • Page 81: B1.5 Device Compatibility

    Master / Slave combinations will fail to be recognised by the BIOS. To help highlight the problem, Inova have provided the test report shown in Table B1.5 which should be regarded as a guide when choosing to pick-and-mix de- vices.
  • Page 82 IPM-ATA Appendix B This page has been left blank intentionally. Page B-8 ©2001 Inova Computers GmbH CPU Appendix-B...
  • Page 83 Figure C1.6 LPT1 Interface Pinout ....................C-5 Table C1.6 LPT1 Connector Signals .................... C-5 C1.5 COM2 Interface ..................C-6 Figure C1.5 COM2 Interface Pinout ................... C-6 Table C1.5 COM2 Connector Signals ..................C-6 CPU Appendix-C ©2001 Inova Computers GmbH Page C-1...

  • Page 84: C1 Ipb-Fpe12 Cpu Extension

    Appendix C C1 IPB-FPE12 CPU Extension The Inova IPB-FPE12 adds LPT and COM2 functionality to any Inova CPU. The piggyback is avail- able as a stand-alone device with its own 4HP front-panel or integrated within a 12HP K6 or PPC front-panel.

  • Page 85: C1.3 Lpt1 & Com2 Piggyback

    Also, pin 1 has been highlighted by a red triangle. Note: Damage to the CPU board or the piggyback may result if the flex cable is positioned incorrectly. Inova will not accept responsibility for negligent actions! Figure C1.3 LPT1 & COM2 Piggyback Board IPB-FPE12...
  • Page 86 Connector Description LPT1 & COM2 Note: Other Inova piggybacks (ICP-HD-1 & ICP- HDE8) provide J13a to “daisy-chain” the LPT1 / COM2 interfaces. If these connec- tors are used for the integration of the IPB-FPE12 then the COM2 port on these piggybacks is disabled.

  • Page 87: C1.4 Lpt1 Interface

    4HP unit. The piggyback located behind these interfaces connects to the CPU-mounted J13 connector. Figure C1.6 LPT1 Interface Pinout Table C1.6 LPT1 Connector Signals Pin No. Signal Pin No. Signal STROBE BUSY SLCT AUTOED ERROR INIT SLCTIN 18-25 CPU Appendix-C ©2001 Inova Computers GmbH Page C-5...

  • Page 88: C1.5 Com2 Interface

    UART’s RTS signal. Writing a hex value of 0B to this register allows data to be transmitted. Writing 1B to this register configures the device to receive data. Page C-6 ©2001 Inova Computers GmbH CPU Appendix-C...
  • Page 89 D1.2 IPB-RIO-HD-LPT-(FLEX) ................D-3 Figure D1.2 IPB-RIO-HD-LPT-(FLEX) .................... D-3 D1.3 IPB-RIO-C-SHORT ................... D-4 Figure D1.3 IPB-RIO-C-SHORT ....................D-4 Table D1.3 Rear I/O Type ‘C’ ..................... D-4 D1.4 IPB-RIO-C-80MM ..................D-5 Figure D1.4 IPB-RIO-C-80MM ....................D-5 CPU Appendix-D ©2001 Inova Computers GmbH Page D-1...

  • Page 90: D1 Ipb-Rio Cpu Extension

    CompactPCI connector on the rear of the Master Slot on the backplane. All standard Inova backplanes are equipped with this R2 connector so that even if the rear I/O functionality is not requested at time of order, it can be implemented at a later stage.

  • Page 91: D1.2 Ipb-Rio-Hd-Lpt-(Flex

    CompactPCI backplane and presents them in a form ready for device connection. This time, instead of a standard IDE header, the IDE device is connected using the familiar Inova flex cables. Also, a slim-line floppy disk may be attached using a suitable cable to the LPT connector (J13).

  • Page 92: D1.3 Ipb-Rio-C-Short

    Appendix D D1.3 IPB-RIO-C-SHORT All Inova -RIO(C) compatible CPUs can take advantage of this transition module as it allows the signals shown in table D1.3 to be recovered (used). Figure D1.3 illustrates this piggyback and points to the available interfaces.

  • Page 93: D1.4 Ipb-Rio-C-80Mm

    Naturally, not all enclosures are suitable for this type of connection and the following must be considered. Inova Desktop systems have an integrated fan - will the transition module interfere with it? 84HP Inova CoolBreeze systems are too short to accept an 80mm transition module.
  • Page 94 IPB-RIO Appendix D This page has been left blank intentionally. Page D-6 ©2001 Inova Computers GmbH CPU Appendix-D...

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