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Mechatronics MXS3FK-DSP Operational Manual

Spartan-3 dsp trainer
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OPERATIONAL MANUAL
MECHATRONICS TEST EQUIPMENT (I)PVT.LTD.
B-3,MAYUR COMPLEX, OPP. BHELKE NAGAR,
NEAR YASHAVANTRAO CHAVAN NATYAGRUH,
KOTHRUD, PUNE- 411038
PHONE :
FAX
:
EMAIL
:
URL
:
FOR
SPARTAN-3 DSP TRAINER
MODEL : MXS3FK-DSP
+91-20-25386926
+91-20-25386930
mtepl@vsnl.net
www.mte-india.com
Rev : 003

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  • Page 1 OPERATIONAL MANUAL SPARTAN-3 DSP TRAINER MODEL : MXS3FK-DSP Rev : 003 MECHATRONICS TEST EQUIPMENT (I)PVT.LTD. B-3,MAYUR COMPLEX, OPP. BHELKE NAGAR, NEAR YASHAVANTRAO CHAVAN NATYAGRUH, KOTHRUD, PUNE- 411038 PHONE : +91-20-25386926 +91-20-25386930 EMAIL mtepl@vsnl.net www.mte-india.com...

  • Page 2: Table Of Contents

    TABLE OF CONTENTS PREFACE .............................1 About This Manual ........................1 Manual Contents ............................1 CHAPTER 1..........................2 Introduction ..........................2 Features ..............................2 CHAPTER 2..........................5 ADC - DAC Interface .........................5 2.1 ANALOG INPUT..........................5 2.2 Analog Input Connector:........................6 2.3 ANALOG OUTPUT...........................8 2.4 Analog Output Connector:........................9 2.6 Stereo Jack Connector:........................9 2.7 Function Generator ........................10 2.8 Potentiometer Adjustments ......................10 2.9 Jumper Settings of ADC- DAC Interface..................11...
  • Page 3 9.3 ASCII CODE...........................33 CHAPTER 10..........................34 Switches And LEDs .........................34 10.1 DIP Switches ..........................34 10.2 Key Switches ..........................34 10.3 LEDS ............................35 CHAPTER 11..........................36 Connector Details ........................36 11.1 IO Connectors ..........................36 CHAPTER 12..........................38 Clock and Reset Sources ......................38 CHAPTER 13..........................39 SPARTAN-3 Configuration Details ..................39 13.1 Boundary Scan mode:........................39 13.2 Master Serial Mode ........................39 13.3 Jumper Setting ..........................39...
  • Page 4 LIST OF FIGURES Figure 1: Block Diagram........................3 Figure 2: FPGA – ADC DAC Interface ..................5 Figure 3: Input Channels of ADC ....................6 Figure 5: Reconstruction Filter ......................9 Figure 6: Stereo Jack ........................10 Figure 7: Frequency Range Set ....................10 Figure 8: USB Interface.......................14 Figure 9: FPGA –...
  • Page 5 LIST OF TABLES Table 1: Analog Inputs ........................6 Table 2: ADC Interface to SPARTAN 3 FPGA................8 Table 3: Control Inputs to ADC .....................8 Table 4: Analog Outputs .......................9 Table 5: DAC Interface to FPGA....................9 Table 6: Potentiometer adjustments ...................10 Table 7: Jumper Setting for ADC Input ..................11 Table 8: Jumper setting for Anti Aliasing Filter................11 Table 9: Jumper Setting for Analog Output.................11 Table 10: Jumper Setting for Reconstruction Filter..............11...

  • Page 6: Preface

    PREFACE About This Manual This manual gives operational details for all the interfaces. Manual Contents This manual contains following chapters: • Chapter 1, “ Introduction ” • Chapter 2, “ ADC And DAC Interface ” • Chapter 3, “ USB Interface ” •...

  • Page 7: Chapter 1

    CHAPTER 1 Introduction SPARTAN-3 based Universal DSP ProtoBoard (MXS3FK-004-DSP) provides easy to use development platform, useful to physically verify DSP algorithms or simple digital designs around SPARTAN -3 FPGA. Features Figure 1 shows the SPARTAN-3 ProtoBoard, which includes the following components and features: •...

  • Page 8: Figure 1: Block Diagram

    One Reconstruction filter at the output of Digital to Analog converter. Figure 1: Block Diagram • Seven Segment Display: Four-character, seven-segment LED display. • DIP Switches: 16 DIP switches. • LEDs: 38 onboard LEDS...
  • Page 9 16 output LEDs (OL 0 – OL 15). 16 input LEDs (IL 0 – IL 15). Done LED.(DONE) 3 Power ON LEDs (LED5V, LED3V3, LED2v5). 2 Relay LEDs (RNO, RNC). • Push Button Switches: 16 momentary-contact push button switches. • LCD interface: 16 character 2 row LCD.

  • Page 10: Chapter 2

    CHAPTER 2 ADC - DAC Interface SPARTAN-3 DSP ProtoBoard has a high speed, 12 bit ADC (AD 7891) and DAC (AD 7541), surface mounted on top side of the board. A detailed interface is as shown in Figure 2 Figure 2: FPGA – ADC DAC Interface 2.1 ANALOG INPUT Five analog input channels (In-Channel 1 to In-Channel 4 and In-Channel 5 for Thermister), as shown in Figure 3, are provided using ADC - AD7891, with following specifications...

  • Page 11: Analog Input Connector

    • In-Channel 1 and In-Channel 2 can take external analog inputs either from the PUT terminal or audio inputs from the stereo jacks provided. • In-Channel 3 takes an external analog input from the PUT terminal. Figure 3: Input Channels of ADC •...

  • Page 13: Analog Output

    Table 2: ADC Interface to SPARTAN 3 FPGA Data Bits FPGA pin "AD0_F" "AD1_F"" "AD2_F"" "AD3_F"" "AD4_F"" "AD5_F"" "AD6_F"" "AD7_F"" "AD8_F"" "AD9_F"" "AD10_F"" "AD11_F"" Table 3: Control Inputs to ADC Control Inputs FPGA PIN "MODE" "EOC_F" "\CONVST\" "\CS\" "\RD\" "\WR\" 2.3 ANALOG OUTPUT Four analog output channels are provided on-board DAC –...

  • Page 14: Analog Output Connector

    Figure 5: Reconstruction Filter 2.4 Analog Output Connector: • Vout1 to Vout4: Four PUTs are provided to provide ANALOG OUTPUTS Table 4: Analog Outputs Vout1 Vout2 Vout3 Vout4 Vout1 Vout2 Vout3 Vout4 Table 5: DAC Interface to FPGA Data Bits FPGA PIN "DAC0_F"...

  • Page 15: Function Generator

    Figure 6: Stereo Jack 2.7 Function Generator Function Generator - IC8038 is used on board to generate sine, square, triangular waves in the frequency range of 60 Hz to 200 KHz. Output of function generator can be used as analog input to ADC for performing different DSP applications Function Generator outputs are available as Sine, Square and Triangular wave at three test points –...

  • Page 16: Jumper Settings Of Adc- Dac Interface

    Frequency Adjustment Square Wave Amplitude Adjustment Triangular Wave Amplitude Adjustment Sine Wave Amplitude Adjustment Offset adjustment of Sine wave Offset adjustment of Triangular wave Time constant(R) adjustment of anti-Aliasing Filter Time constant(R) adjustment of Reconstruction Filter DAC-1 range adjustment DAC-2 range adjustment PR10 DAC-3 range adjustment PR11...
  • Page 17 DAC OUT with Reconstruction Filter DAC OUT without Reconstruction Filter...

  • Page 18: Chapter 3

    CHAPTER 3 USB Interface SPARTAN-3 Protoboard has a USB interface using device FT245BM from FTDI. It offers data transfer rates up to 8 Million bits (1 Megabyte) per second. To send data from the FPGA to the host computer, write the byte-wide data into the module when TXE# is low.

  • Page 19: Data Bus Connection

    Figure 8: USB Interface 3.1 Data Bus Connection 8 bit bidirectional data bus for data transfer from / to FPGA and USB interface. Table 11: Data Bus Interface to SPATAN -3 FPGA FPGA Pin Data Bit "USB_D0_F" "USB_D1_F" "USB_D2_F" "USB_D3_F" "USB_D4_F"...

  • Page 20: Ftdi Driver Installation

    • RD #: Enables reading of data byte from USB controller on data line interface when low. • WR : Writes data byte from D0-D7 into the transmit FIFO of USB. • TXE #: Data write enable. • RXF #: Data read enable. Table 12: Control Lines Interface to SPARTAN-3 FPGA Control Bit FPGA Pin...
  • Page 21 • When USB device unplugged the Device Manager will remove USB Serial Converter controller from its USB Serial Bus Controller list as shown below...

  • Page 22: Chapter 4

    CHAPTER 4 Serial Interface The SPARTAN -3 DSP Protoboard supports RS-232 serial interface. The details of interface are described below. 4.1 RS- 232 Interface The RS-232 transmit and receive signals appear on the female DB9 connector, indicated as in Figure 9. The connector is a DCE-style port and connects to the DB9 DTE-style serial port connector available on most personal computers and workstations.
  • Page 23 For more details on RS232 UART application please refer the following application note AN2141 from Maxim.

  • Page 24: Chapter 5

    CHAPTER 5 PS/2 Mouse/Keyboard Interface SPARTAN -3 Proto board includes a separate PS/2 port for keyboard/mouse interface using a standard 6 pin PS/2 connector as shown in figure 10. Figure 10: PS/2 Connector Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a host device, the SPARTAN -3 FPGA in this case.

  • Page 25: Ps/2 Keyboard

    Clock to data hold time 5µs 25µs Figure 11: PS/2 Timing Diagram 5.1 PS/2 KEYBOARD The keyboard uses open-collector drivers so that either the keyboard or the host can drive the two-wire bus. If the host never sends data to the keyboard, then the host can use input pins. A PS/2-style keyboard uses scan codes to communicate key press data.

  • Page 26: Control Signal Connection

    Figure 12: PS/2 Keyboard with scan codes Some keys, called extended keys, send an “E0” ahead of the scan code and furthermore, they may send more than one scan code. When an extended key is released, an “E0 F0” key up code is sent, followed by the scan code.
  • Page 27 "PS2_CLOCK_F" "PS2_DATA_F"...

  • Page 28: Chapter 6

    CHAPTER 6 VGA Interface The SPARTAN-3 proto board includes a VGA display port and DB15 connector, indicated as in Figure 13. This port connects directly to most PC monitors or flat-panel LCD displays using a standard monitor cable. VGA stands for Video Graphics Array, sometimes referred to as Video Graphics Adapter. It is a video card, which is an interface between a computer and its corresponding monitor.

  • Page 29: Vga Display Theory

    As shown in Figure 13, the SPARTAN-3 FPGA controls 9 VGA signals: three for Red, three for Green, three for Blue, Horizontal Sync, and Vertical Sync, all available on the VGA connector. The FPGA pins that drive the VGA port appear in Table 19. Table 19: VGA Interface to SPARTAN-3 FPGA Control Bit FPGA Pin...

  • Page 30: Figure 14: Crt Display Timing

    Figure 14: CRT Display Timing The size of the beams, the frequency at which the beam traces across the display and the modulation frequency of electron beam. Determine the display resolution. Modern VGA displays support multiple display resolutions, and the VGA controller dictates the resolution by producing timing signals to control the raster patterns.

  • Page 31: Vga Signal Timing

    6.2 VGA signal TIMING The signal timings in Table 20 are derived for a 640-pixel by 480-row display using a 25 MHz pixel clock and 60 Hz ±1 refresh. Figure 15 shows the relation between each of the timing symbols. Figure 15: VGA Timing The timing for the sync pulse width (TPW) and front and back porch intervals (TFP and TBP) are based on observations from various VGA displays.

  • Page 32: Chapter 7

    CHAPTER 7 Seven Segment LED Display The SPARTAN-3 protoboard has a four-character, seven segment LED display controlled by FPGA user-I/O pins. Each digit shares eight common control signals to light individual LED segments. Each individual character has a separate cathode control input. To light an individual signal, drive the individual segment control signal High along with the associated cathode control signal for the individual character.

  • Page 33: Table 21: Seven Segment Display Interface To Spartan-3 Fpga

    • Common Anode Display: In this type of display all the anode terminals of LEDs are tied together and the cathode terminals decide the status of the LED either ON or OFF. • To turn ON the LED i.e. segment value of driven segment should be 0 and 1 for turn OFF. Interface details for the seven segment display with SPARTAN-3 display is as follows Table 21: Seven Segment Display Interface to SPARTAN-3 FPGA Control Bit...

  • Page 34: Chapter 8

    CHAPTER 8 Stepper Motor And Relay Interface 8.1 Stepper Motor Interface The stepper motor provided onboard interface with the following specification- • Stepper Motor-SMO-02 Input Voltage – 12 VDC Step Angle – 1.8 Steps/Revolution – 200 Figure 17: Stepper Motor Interface Stepper Motor Connector Details By giving control signals to these pins the Speed and Direction of Rotation of Stepper Motor can be controlled...

  • Page 35: Figure 18: Relay Interface

    Figure 18: Relay Interface Table 23: Stepper Motor and Relay Interface to FPGA Function FPGA Pin Number A1_COIL " _F" A2_COIL " _F" B1_COIL " _F" B2_COIL " _F" RELAY0 " _F"...

  • Page 36: Chapter 9

    CHAPTER 9 LCD Interface SPARTAN-3 proto board includes a LCD Module, which is a dot matrix liquid crystal display that displays alphanumeric, Kana (Japanese) characters and symbols. Built in controller provides connectivity between LCD and FPGA. This LCD has a built in Dot Matrix controller, with font 5x7 or 5x10 dots, display data RAM for 80 characters ( 80 x 8 bit) and a character generator ROM which provides 160 characters with 5x7 font and 32 characters with font of 5x10.

  • Page 37: Data Lines Connection

    9.1 Data Lines Connection LCD has 8 bit bidirectional data bus interface to FPGA. When Enable signal is at low level, these data bus remains in high impedance state. Interface details of the data lines with SPARTAN-3 FPGA are as in Table 24 Table 24: Data Line Interface to SPARTAN-3 FPGA Data Bit FPGA Pin...

  • Page 38: Ascii Code

    9.3 ASCII CODE The ASCII code for 5x 7 LCD Display is given in Figure 20 Figure 20: ASCII Code for 5 x 7 LCD display...

  • Page 39: Chapter 10

    CHAPTER 10 Switches And LEDs 10.1 DIP Switches The SPARTAN -3 proto board has 16 DIP switches. The switches connect to an associated FPGA pin, as shown in Table 26 A 4.7KΩ series resistor provides nominal input protection. Table 26: DIP switch Interface to SPARTAN-3 FPGA Control Bit FPGA Pin "IL0_F"...

  • Page 40: Leds

    10.3 LEDS The SPARTAN-3 proto board has 16 multicoloured LEDs located above the key switches, indicated in Figure 1. The LEDs are labelled LED15 through LED0.Table 28 shows the FPGA connections to the LEDs. A series current limiting resistor of 270Ω is associated with every LED. To light an individual LED, drive the associated FPGA control signal High Table 28: LED Interface to SPARTAN-3 FPGA Control Bit...

  • Page 41: Chapter 11

    CHAPTER 11 Connector Details SPARTAN-3 Proto Board has provision for 4 connectors. 11.1 IO Connectors • I/O’s from FPGA are provided on four connectors. Each connector is having 3.3V, Ground and free IOs. For XC3S400 (PQ208) IOs are provided on four connectors as follows, •...

  • Page 42: Figure 21: Positional Details Of On Board Connectors

    Figure 21: Positional Details of On Board Connectors...

  • Page 43: Chapter 12

    CHAPTER 12 Clock and Reset Sources The SPARTAN-3 Proto board has a dedicated 4 MHz oscillator source (OSC1) and an optional socket for another clock oscillator source (OSC2). This dedicated clock source can be used to derive other frequencies using DCM (digital clock mangers) available in SPARTAN-3 FPGA.

  • Page 44: Chapter 13

    CHAPTER 13 SPARTAN-3 Configuration Details SPARTAN-3 Proto board supports two configuration modes as stated below • Boundary Scan mode • Master Serial Mode 13.1 Boundary Scan mode: In boundary scan mode of configuration the SPARTAN-3 FPGA is directly configured via a JTAG port using the dedicated configuration pins TCK, TMS, TDI and TDO.

  • Page 45: Jtag Header

    Table 33: Configuration Selection JUMPER SETTING JP17 Configuration of PROM + FPGA Configuration of FPGA • JTAG Chain Selection Jumper: JP17 jumper is used to select the JTAG chain for configuration. When jumper is connected between 2-3, then PROM and FPGA both get added in the JTAG Chain where as connecting jumper between 1-2 brings only FPGA in Chain.

  • Page 46: Figure 23: Jtag Connector Details

    Figure 23: JTAG Connector Details...

  • Page 47: Chapter 14

    CHAPTER 14 Power Supplies SPARTAN-3 Proto board is provided with a regulated power supply of + 5V DC output. This supply is used to generate the required on board supply voltages. Output of the regulated power supply is given to power connector present on board. The power LED (Red LED) lights up when power is properly applied to the board.

  • Page 48: Consolidated Ucf For The Complete Board

    APPENDIX A Consolidated UCF For The Complete Board Clock And Reset Reset "RESET" loc= P78; Clock "CLOCK" loc= P76; "CLOCK1" loc= P77; Test LEDs "OL0_F" loc= P161; "OL1_F" loc= P172; "OL2_F" loc= P156; "OL3_F" loc= P171; "OL4_F" loc= P155; "OL5_F" loc= P169;...
  • Page 49 "TXE#_F" loc= P119; "WR#_F" loc= P117; "RD#_F" loc= P116; "RXF#_F" loc= P120; LCD Interface Data Lines "DL0_F" loc= P33; "DL1_F" loc= P31; "DL2_F" loc= P29; "DL3_F" loc= P28; "DL4_F" loc= P27; "DL5_F" loc= P26; "DL6_F" loc= P24; "DL7_F" loc= P22; Control Lines "RS_F"...
  • Page 50 "PS2_CLOCK_F" loc= P194; "PS2_DATA_F" loc= P191; Keys "KEY0_F" loc= P143; "KEY1_F" loc= P144; "KEY2_F" loc= P146; "KEY3_F" loc= P147; Input Switches "IL0_F" loc= P141; "IL1_F" loc= P140; "IL2_F" loc= P139; "IL3_F" loc= P138; "IL4_F" loc= P137; "IL5_F" loc= P135; "IL6_F" loc= P133;...
  • Page 52 FREE IOs "IO1_F" loc= P21; "IO2_F" loc= P20; "IO3_F" loc= P19; "IO4_F" loc= P18; "IO5_F" loc= P16; "IO6_F" loc= P15; "IO7_F" loc= P13; "IO8_F" loc= P12; "IO9_F" loc= P11; "IO10_F" loc= P10; "IO11_F" loc= ADC Interface Data Lines "AD0_F" loc= P45;...
  • Page 53 " " loc= DAC1_F " " loc= 100; DAC2_F " " loc= DAC3_F " " loc= DAC4_F " " loc= DAC5_F " " loc= DAC6_F " " loc= DAC7_F " " loc= DAC8_F " " loc= DAC9_F 102; " " loc= 101;...

  • Page 54: Operating Instructions To Start A New Design

    APPENDIX B Operating Instructions To Start A New Design B.1 Starting The ISE Software: • Start ISE from the Start menu by selecting Start ->  P rograms ->  X ilinx ISE Project Navigator. B.2 Design Flow • DESIGN ENTRY •...

  • Page 55: Design Description

    Sample Design of Half Adder is used to explain the Design Flow. B.3 Design Description Carry Half Adder B.4 Truth Table of Half adder: - Output Inputs Carry B.5 VHDL Code for Half adder library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;...

  • Page 56: Steps To Implement The Half Adder In The Fpga Using Xilinx Ise(8.1I)

    B.6 Steps to implement the Half adder in the FPGA using Xilinx ISE(8.1i) Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start Step 1 : Programs Xilinx ISE (8.1i). SOURCE WINDOW WORK SPACE TRANSCRIPT PROCESS WINDOW...
  • Page 57 Step 2 Create a new project In the window go to FILE New project. Specify the project name and location and say NEXT Select Device. Use the pull-down arrow to select the Value for each Property Name. Click in the field to access the pull-down list. Say FINISH.
  • Page 58 Step 3: Creating a new VHD file Click on the symbol of FPGA device and then right click Click on new source VHDL module and give the File name VHDL MODULE Then say Next Define ports.In this case • a and b are the input ports defined as in •...
  • Page 59 Step 4: Writing the Behavioural VHDL Code in VHDL Editor Sample code is given below for this experiment. Step 5 Check Syntax Run the Check syntax Process window synthesize check syntax >, and remove errors if present.
  • Page 60 Step 6 Creating a test bench file Verify the operation of your design before you implement it as hardware. Simulation can be done using ISE simulator. For this click on the symbol of FPGA device and then right click Click on new source Test Bench Waveform and give the name Select entity Finish.
  • Page 61 Step 7: Simulate the code Simulation Tools ISE tool supports the following simulation tools: • HDL Bencher is an automated test bench creation tool. It is fully integrated with Project Navigator. • ModelSim from Model Technology, Inc., is integrated in Project Navigator to simulate the design at all steps (Functional and Timing).
  • Page 62 Verify your design in wave window by seeing behaviour of output signal with respect to input signal. Close the ISE simulator window SIMULATED OUTPUT...
  • Page 63 Step 8: Synthesize the design using XST. Translate your design into gates and optimize it for the target architecture. This is the synthesis phase. Again for synthesizing your design, from the source window select, synthesis/Implementation from the drop-down menu. SYNTHESIS Highlight file in the Sources in Project window.
  • Page 64 SYNTHESIS COMPLETED SUCCESSFULLY Step 9: Create Constraints File(UCF) Click on the symbol of FPGA device and then right click Click on new source Implementation Constraints File and give the name Select entity Finish. Click on User Constraint and in that Double Click on Assign Package Pins option in Process window.
  • Page 65 ASSIGNMENT Step 10: Implementing a Design Once synthesis is complete, you can place and route your design to fit into a Xilinx device, and you can also get some post place-and-route timing information about the design. The implementation stage consists of taking the synthesized netlist through translation, mapping, and place and route.
  • Page 66 IMPLEMENTATION DONE Step 11: Generating Programming File Right-click on Generate Programming File, choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream Step 12 Downloading in Boundary Scan Mode. Note : Xilinx provides 2-tools for downloading purpose, viz. •...
  • Page 67 BOUNDARY SCAN MODE...
  • Page 68 Procedure for downloading using iMPACT • Boundary Scan Mode 1. Right click on “Configure Device (iMPACT)” -> and Say RUN or Double click on “Configure Device (iMPACT)”. 2. Right click in workspace and say Initialize chain .The device is seen. 3.
  • Page 69 Right click on “Generate PROM,ACE or JTAG file” -> and Say RUN or Double click on “Generate PROM,ACE or JTAG file” Specify the PROM file name and location where it is to be generated.
  • Page 70 Specify the desired parameters of the PROM on board and say ADD then FINISH...
  • Page 71 Say Generate File from the Process Window. PROGRAMMING THE PROM Note: Check the Jumper setting on the board. Refer the Chapter jumper Setting Similar to Step 12.Initialize chain through iMPACT. PROM and FPGA devices on board are seen .Assign the generated mcs file and bit file as desired. Right click the PROM symbol and say PROGRAM.
  • Page 72 Now, whenever the board is powered on in master serial mode, FPGA is configured through PROM automatically...

  • Page 73: Component Diagram Details

    APPENDIX C Component Diagram Details Above figure represents component diagram for SPARTAN-3 Development board.

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