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Vmetro Power MIDAS M5210-EFF User Manual

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Summary of Contents for Vmetro Power MIDAS M5210-EFF

  • Page 1 (217) 352-9330 | Click HERE Find the Curtiss-Wright / VMETRO PowerMIDAS MDR M5210-EFF at our website:...
  • Page 2 User Guide Power MIDAS M5000 Series Single Board Computer...
  • Page 3 Any Software and Firmware code provided by VMETRO described herein is proprietary to VMETRO or its licensors. The use of this Software and Firmware is governed by a licensing agreement included on the media on which the Software and Firmware was supplied. Use of the Software or Firmware assumes that the user has agreed to the terms of the licensing agreement.
  • Page 4 The warranty provided herein for electronic equipment products is the user's sole and exclusive remedy. In no event shall VMETRO, or its distributors and agents, be liable for direct, indirect, special, incidental, or consequential damages (including but not limited to lost...
  • Page 5 Fax: (607) 272 5498 Contact: Luca Ravera info@vmetro.com Phone: +39 11 9661319 Fax: +39 11 9662368 Asia Pacific info@vsystems.it VMETRO Pte Ltd 175A Bencoolen Street #06-09 Burlington Square Singapore 189650 Phone: +65 6238 6010 Fax: +65 6238 6020 info@vmetro.com.sg www.vmetro.com...
  • Page 6 Preface Introduction The VMETRO MIDAS M5000 series is a single-board computer (SBC) built in a 6U VMEbus form factor based on the AMCC PPC440GX PowerPC processor. This document describes the M5000 hardware. The chapters are summarized below: • Product Overview: provides a brief description of the M5000.
  • Page 7 1 073 741 824 bytes Quality Assurance VMETRO is dedicated to supplying our customers with products and services of the highest quality. We therefore, continually review and assess our products and services with the aim to improve the processes involved in the development of our world-class products.

  • Page 8: Table Of Contents

    Contents Product Overview ........1 1.1 Main features: .
  • Page 9 RJ45 Ethernet Connector......... . . 24 Processor Subsystem .
  • Page 10 IDSEL Assignment ..........43 5.3 Tundra Universe IID PCI-to-VME Bridge .
  • Page 11 APPENDIXES..........71 PLD Registers .
  • Page 12 Figures FIGURE 1-1 Component Overview ..........2 FIGURE 1-2 Processor Subsystem .
  • Page 13 M5000 Series: User Guide Issued June 20, 2007 5:23...
  • Page 14 Tables TABLE 2-1.Default Jumper and Switch settings ........13 TABLE 2-2.PCI-X to PCI-X Bridges SW2, SW9, SW8 settings .
  • Page 15 TABLE B-2. VME Slave image 0 - setup ......... . 82 TABLE B-3.VME Slave image 1 - setup .

  • Page 16: Product Overview

    Product Overview The M5000 series is part of the next generation of boards in the MIDAS family. As for the previous generations, the M5000 series focuses on high-performance data buffering and flexible data flows between I/O ports. I/Os are provided through front panel connectors and P2 and P0 backplane connectors.

  • Page 17: Main Features

    Product Overview 1.1 Main features: • A PowerPC processor subsystem (440GX from IBM) with up to 256MiB local DDR-SDRAM memory, 32MiB of FLASH memory, four Ethernet ports (two 10/100/1000Mbps and two 10/ 100Mbps) and two serial ports. • Two standard PPMC sites located on separate PCI segments (64-bit, 33/66MHz PCI, 66/100/ 133MHz PCI-X).

  • Page 18: Main Components

    Main Components 1.2 Main Components Processor Subsystem The processor subsystem is built around the AMCC 440GX integrated processor, the QLOGIC ISP2312 dual Fibre Channel I/O Controller and the PCI6540 PCI-X to PCI-X bridge. The Processor Subsystem is located on the Primary PCI segment (PCI-X). The processor subsystem block diagram is shown in figure Figure 1-2: FIGURE 1-2 Processor...

  • Page 19: Pmc Subsystem

    Product Overview PCI6540 PCIX-to-PCIX Bridge The PCI6540 provides a 64-bit PCI-X to PCI-X bridge designed for high performance, high availability applications, in PCI-X to PCI-X conversion, bus expansions, frequency conversions from faster PCI-X to slower PCI-X or from slower PCI-X to faster PCI-X bus, address remapping, high availability and universal system-to-system bridging.

  • Page 20: Extension Subsystem

    Both PMC sites support either 3.3V or 5V signaling on VIO. The choice is determined by mounting options (resistors and voltage key/pin) and can only be modified by VMETRO. The default setting when shipped is 3.3V. The voltage key must always be mounted in the correct position to avoid severe hardware damage.

  • Page 21: Miscellaneous Functions

    Product Overview UNIV UNIV PCI/PCI X 6540 (33 133MHz, 64bit) (33MHz, 64bit, 5V) PCI-X to PCI-X Bridge MEZZ MEZZ VME Interface The Tundra Universe IID PCI-to-VME Bridge is a PCI only component which provides VME accesses. Hardware configuration of the Universe IID is done entirely using micro switches. RACE++ Interface The Mercury PXB++ PCI-to-RACE++ Bridge is a PCI only component which provides RACE++ accesses.
  • Page 22 It is possible to connect to only the segments that are appropriate for a specific software tool. An adapter board is needed to connect to the correct taps of the chain, and to provide connectors that are compatible with the tools connector. For more information please contact VMETRO. Temperature Sensors Temperature sensors are very useful when monitoring applications during extreme conditions.
  • Page 23 Product Overview M5000 Series: User Guide Issued June 20, 2007...

  • Page 24: Installation And Hardware Description

    Installation and Hardware description Issued June 20, 2007 M5000 Series: User Guide...

  • Page 25: Before You Begin

    Note – You should also inspect the board to verify that no mechanical damage has occurred. Please report any discrepancies or damage to your distributor or to VMETRO immediately. M5000 Series: User Guide...

  • Page 26: Installing Pmc Modules

    Installing PMC Modules 2.2 Installing PMC Modules The M5000 is shipped with two PMC filler panels mounted in the front panel. They act as EMC shielding in unused PMC positions. Before installing a PMC module, the filler panel(s) must be removed.

  • Page 27: Switches And Jumper Settings

    Installation and Hardware description 2.3 Switches and Jumper Settings FIGURE 2-1 Jumper Settings PMC Monarch SW10 Selection Processor SW11 PCI to VME Bridge Subsystem PCI to VME Configuration settings bridge settings PCI to VME Settings PCI-X to PCI-X Bridge #3 RACEway to PCI-X Capability VME bridge...

  • Page 28: Default Jumper And Switch Settings

    Switches and Jumper Settings Default Jumper and Switch Settings The factory settings of the jumpers and switches are shown in Table 2-1: Default Jumper and Switch settings TABLE 2-1. Jumper/switch Position Description Inserted on left side on R PCI to RACEway Bridge Reset Configuration models.

  • Page 29: Table 2-2.Pci-X To Pci-X Bridges Sw2, Sw9, Sw8 Settings

    Installation and Hardware description Each switch is has the settings described in Table 2-2. PCI-X to PCI-X Bridges SW2, SW9, SW8 settings TABLE 2-2. Switch Function Port Priority Boot The switch is connected to the P_BOOT pin on the bridge. Non-Transparent Mode: the primary/secondary port has boot priority when the switch is ON/ Transparent Mode: Not Used.

  • Page 30: Table 2-3.Pci-To-Vme Bridge Sw11 Settings

    Switches and Jumper Settings PCI-to-VME Bridge The PCI-to-VME bridge is configured using the switches SW5, SW3 and SW11. PCI-to-VME bridge SW11 settings TABLE 2-3. Switch Function SYSFAIL Assertion SYSFAIL is not asserted when the switch is ON. SYSFAIL is asserted asserted when the switch is OFF VME64 AutoId AutoId is enabled when the switch is ON AutoId is disabled when the switch is OFF...

  • Page 31: Table 2-6.Raceway-To-Pci Bridge Sw7 Settings

    Installation and Hardware description PCI to RACEway Bridge The PCI to RACEway bridge is configured using switch SW7. RACEway-to-PCI bridge SW7 settings TABLE 2-6. Switch Function Operating Mode The bridge is configured in bridge mode/endpoint mode when the switch is ON/OFF. This switch is connected to the pin RES_PROM_P on the bridge.

  • Page 32: Jumper Settings

    Switches and Jumper Settings PCI-X Capability Selection for PMC Slots The PCI-X Capability Selection is performed using the switches SW1 and SW4. • Switch 1 configures PMC#2 bus • Switch 4 configures PMC#1 bus PCI-X Capability Selection SW1(PMC#2) and SW4(PMC#1) settings TABLE 2-9.

  • Page 33: Installing The M5000 Into The Vme Chassis

    Warning! The M5000 hardware requires forced air-cooling for reliable operation. Commercial and Rugged Level 1 boards require 300lfm, Rugged Level 3 requires 600lfm. For Rugged Level 2 contact VMETRO.. Operation on extender boards is not recommended. Typical values for power consumption are shown in Table 2-10. In Idle Mode, no processors are booting, and no data is transferred.

  • Page 34: Table 2-10.M5000 Power Consumption

    Installing the M5000 into the VME Chassis Although the M5000 board may increase the system power consumption by driving the VME bus, the additional power is not included in the numbers below, since the additional power is dissipated outside the board. Furthermore, the VME traffic pattern, and the M5000's share of the VME bus is highly application dependent.

  • Page 35: Environmental Specifications

    Installation and Hardware description 2.5 Environmental Specifications VMETRO offers ruggedized versions of selected models of the PowerMIDAS M5000s that are characterized for extended temperature range, shock, vibration, altitude and humidity. These boards are equipped with extra and/or special hardware to improve tolerance against shock and vibration.

  • Page 36: Front Panel Connectors

    Front Panel Connectors 2.6 Front Panel Connectors Figure 2-2 shows the front panel connectors on the M5000. FIGURE 2-2 Front Panel connections PMC #2 PMC #1 Serial Ethernet Duplex Link 10/100 Power Fail Fibre Channel Ethernet Port Serial Port Ports PMC # 2 Site PMC # 1 Site Various configurations of the IO connectors are possible depending on the model of M5000 you...

  • Page 37: Fibre Channel Port Leds

    Installation and Hardware description Fibre Channel Port LEDS Fibre Channel Port LEDS TABLE 2-12. Amber LED Green LED Power On On Steady On Steady Loss of Sync Flash at half-second interavls Signal Acquired On Steady Online On Steady System Error (8002h) Flash at half-second intervals Flash at half-second intervals RS232 Connector and cables...

  • Page 38: Figure 2-4 Rs232 Pinout

    Front Panel Connectors FIGURE 2-4 RS232 pinout M5x10-RS232/RS422 Board Female Pin 2 RS232_Rx Pin 2 RxD1 Port#1 Pin 1 RS232_Tx Pin 3 TxD1 RS-232 Pin 7 Pin 5 Female Pin 5 RS422_Rx+ Pin 6 RS422_Rx- RS422_Tx+ Pin 3 Pin 7 Pin 4 RS422_Tx- Pin 6...

  • Page 39: Rj45 Ethernet Connector

    Installation and Hardware description RJ45 Ethernet Connector The M5000 board has an RJ45 type connector for connecting to Ethernet. FIGURE 2-5 Ethernet connector Pin 1 Pin 8 Pin 1: TxD+ Pin 2: TxD- Pin 3: RxD+ Pin 6: RxD- To connect to ethernet, cables with RJ45 connectors must be used. Cat. 5 cables are recommended. M5000 Series: User Guide Issued June 20, 2007...

  • Page 40: Processor Subsystem

    Processor Subsystem Issued June 20, 2007 M5000 Series: User Guide...

  • Page 41: Introduction

    Processor Subsystem 3.1 Introduction FIGURE 3-1 Processor Subsystem Block Diagram SRAM SRAM QLOGIC PCI- X (64 - bit / 133MHz) PCI/PCI -X 6540 ISP2312 (33- 133MHz, 64bit) 2Gbits/s FC 2Gbits/s FC PCI - X to PCI - X Bridge Dual FC Host Adapter SPROM FLASH SPROM...

  • Page 42: Amcc 440Gx Powerpc Embedded Processor

    AMCC 440GX PowerPC Embedded Processor 3.2 AMCC 440GX PowerPC Embedded Processor Designed specifically to address high-end embedded applications, the PowerPC 440GX (PPC440GX) provides a high-performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation. This chip contains a high-performance RISC processor core, DDR SDRAM controller, PCI-X bus interface, Ethernet interface, controls for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O.

  • Page 43: Figure 3-2 Leds On The Mdc-Rj45 I/O Spacer

    Processor Subsystem Link Configuration The four Ethernet links are configured the following way: • The first two MAC interfaces are always configured as SMII (Serial Media Independent Interface). The media interfaces are always configured in the 10/100-TX mode • The third and fourth MAC interfaces are always configured as RGMII (Reduced Gigabit Media Independent Interface).

  • Page 44: Flash

    AMCC 440GX PowerPC Embedded Processor Ethernet LEDs on the MDC-RJ45 I/O Spacer TABLE 3-2. EMAC # LED 1 LED2 Status EMAC 1 Green Yellow (steady) 100 Mbit/s Link Green Yellow (flashing) 100 Mbit/s Activity (RX/TX) Green Green (steady) Duplex Link Green Green (flashing) Collision...

  • Page 45: Serial Prom Devices

    A third serial EEPROM is used to store the MFS (Midas File System). Monitor and BSP boot behavior depending on parameter values held in the MFS. Use of SPROM Devices should be under VMETRO guidance, some functions are already available in the BSP software.

  • Page 46: Qlogic Isp2312 Dual Fibre Channel Controller

    QLOGIC ISP2312 Dual Fibre Channel Controller 3.3 QLOGIC ISP2312 Dual Fibre Channel Controller The ISP2312 is a highly integrated single-chip, dual-channel, bus master, Fibre Channel processor that targets storage, clustering, and networking applications. This chip connects a conventional PCI or PCI-X bus to one or two 1.062 or 2.125 Gbps Fibre Channel ports connected to fabric, single arbitrated loop or point-to-point topologies.

  • Page 47: Pci-X To Pci-X Bridges

    Processor Subsystem 3.4 PCI-X to PCI-X Bridges The PLX6540 64-bit PCI-X to PCI-X bridge is designed for high performance, high availability applications, in PCI-X to PCI conversion, bus expansions, frequency conversions from faster PCI- X to slower PCI-X or from slower PCI-X to faster PCI-X bus, address remapping, high availability hot swap and universal system-to-system bridging.

  • Page 48: Secondary Interface

    PCI-X to PCI-X Bridges Secondary Interface The secondary interface of the PCI6540 is connected to the first PMC site (PMC#1) and the primary interface of another PCI6540 bridge. Issued June 20, 2007 M5000 Series: User Guide...
  • Page 49 Processor Subsystem M5000 Series: User Guide Issued June 20, 2007...

  • Page 50: Pmc Subsystem

    PMC Subsystem Issued June 20, 2007 M5000 Series: User Guide...

  • Page 51: Introduction

    PMC Subsystem 4.1 Introduction The PMC subsystem is composed of two 3.3V signalling PMC sites and is located on two PCI(-X) segments called the Secondary and Tertiary PCI Segments. The connection between the two PCI(- X) segments is provided by a PCI-X to PCI-X bridge. FIGURE 4-1 Subsystem Block Diagram...

  • Page 52: Secondary And Tertiary Pci Segments

    Secondary and Tertiary PCI Segments 4.2 Secondary and Tertiary PCI Segments PCI Mode and Speed Configuration The PCIXCAP and M66EN pins of a PMC module determine which clock speed and protocol (PCI vs. PCI-X) can be used on the segment. There are five detectable modes of operation: 33/66MHz PCI and 66/100/133MHz PCI-X.

  • Page 53: Processor Pmc Support

    PMC Subsystem • AD[20] is used for the PCI6540 P2P Primary Side IDSEL (PCI6540 closer to the Extension Subsystem) Processor PMC Support The Processor PMC standard adds several extensions to the PMC standard: • Support for a second PCI device: Support for a second device requires an additional REQ/ GNT pair and an additional IDSEL signal.

  • Page 54: Pci6540 Pcix-To-Pcix Bridge

    PCI6540 PCIX-to-PCIX Bridge 4.3 PCI6540 PCIX-to-PCIX Bridge This Bridge has been discussed in “PCI-X to PCI-X Bridges” on page 32. What follows are details appropriate for this particular bridge. Power-up / Reset Configuration Options PCI-X Capability Both primary and secondary interfaces can be run in PCI or PCI-X modes. See “PCI-X Capability Selection for PMC Slots”...

  • Page 55: Pmc To Vme Connections

    PMC Subsystem 4.4 PMC to VME connections PMC#1-P4 to VME-P2 In addition to the standard PCI(-X) bus, the PMC#1 site includes a connection between its P4 connector and the VME-P2 connector. This connection follows the ANSI/VITA 35-2000 standard (PMC-P4 pin out mapping to VME P0 and VME64x-P2). As for the PMC#1-P4 to VME-P2 connection, signals are routed as differential pairs.

  • Page 56: Extension Subsystem

    Extension Subsystem Issued June 20, 2007 M5000 Series: User Guide...

  • Page 57: Introduction

    Extension Subsystem 5.1 Introduction The Extension Subsystem is composed of VME, RACEway and mezzanine connections. All the devices are located on a private 64-bit, 33MHz, 5V signaling, PCI only segment. This PCI segment is called the Quaternary PCI Segment. A PCI6540 universal PCI-X to PCI-X bridge connects the Quaternary PCI Segment with the Tertiary PCI Segment.

  • Page 58: Quaternary Pci Segment

    Quaternary PCI Segment 5.2 Quaternary PCI Segment The Quaternary PCI Segment is a 64-bit/33MHz PCI bus. Devices Three major devices are located on the Quaternary PCI Segment: • Tundra Universe IID PCI-to-VME bridge. • Mercury PXB++ PCI-to-RACE++ bridge. • PCI6540 PCI-X to PCI-X bridge. Arbitration The built in arbiter of the PCI6540 bridge is used to arbitrate this segment.

  • Page 59: Tundra Universe Iid Pci-To-Vme Bridge

    Extension Subsystem 5.3 Tundra Universe IID PCI-to-VME Bridge The Tundra Universe II is the industry's leading high performance PCI-to-VMEbus interconnect. Universe II is fully compliant with the VME64 bus standard, and tailored for the next-generation of advanced PCI processors and peripherals. With a zero-wait state implementation, multi-beat transactions, and support for bus-parking, Universe II provides high performance on the PCI bus.

  • Page 60: Mercury Pxb++ Pci-To-Race++ Bridge

    Mercury PXB++ PCI-to-RACE++ Bridge 5.4 Mercury PXB++ PCI-to-RACE++ Bridge The PXB++ implements the functions required to bridge the PCI local bus with the RACEway Interlink crossbar fabric. The PXB++ performs all necessary address translation and routing functions to support high speed transfers between the local PCI bus and either native RACEway interfaces or remote PCI buses which also use PXB++ interfaces.

  • Page 61: Mezzanine Connector

    Extension Subsystem 5.5 Mezzanine Connector The mezzanine connector extends the Quaternary PCI Segment to a MEZZ-x500F type mezzanine which contains 3 PMC slots. M5000 Series: User Guide Issued June 20, 2007...

  • Page 62: Pci6540 Pci-X To Pci-X Bridge

    PCI6540 PCI-X to PCI-X Bridge 5.6 PCI6540 PCI-X to PCI-X Bridge More information about the PCI-X to PCI-X Bridge processor has been discussed in “PCI-X to PCI-X Bridges” on page 32. Power-up / Reset Configuration Options PCI-X Capability • Primary port: XCAP signal is setup at boot-up by the configuration of PCIXCAP, M66EN signals and configuration switches.
  • Page 63 Extension Subsystem M5000 Series: User Guide Issued June 20, 2007...

  • Page 64: Mezzanine Pmc Carrier

    Mezzanine PMC Carrier Precautions in Handling and Storage Static electricity can cause permanent damage. Prevent electrostatic damage by taking proper precautions. • Make sure your body is grounded when coming into contact with the board by wearing an anti-static wrist strap. •...

  • Page 65: Mezzanine Pmc Carrier Description

    Note – The Mezzanine PMC Carrier provides three 5v PMC sites. The two PMC sites on the M52xx are 3.3v If 3.3v PMC sites are required on the PMC Carrier please contact VMETRO. These additional PMC sites share a single PCI segment, which is bridged to the Quarternary PCI bus via a transparent P2P bridge.

  • Page 66: Board Layout

    Board Layout 6.2 Board Layout FIGURE 6-2 Board Layout PMC #3 PMC #3 connectors PMC #4 PMC #4 connectors Secondary MEZZ Bridge PMC #5 (P2P) PMC #5 connectors Issued June 20, 2007 M5000 Series: User Guide...

  • Page 67: Installing Pmc Modules Onto The Pmc Carrier

    Mezzanine PMC Carrier 6.3 Installing PMC Modules onto the PMC Carrier The M5000 is shipped with two PMC filler panels mounted in the front panel. They act as EMC shielding in unused PMC positions. Before installing a PMC module, the filler panel(s) must be removed.

  • Page 68: Figure 6-3 Mounting Screws For The Pmc Carrier

    Installing PMC Modules onto the PMC Carrier FIGURE 6-3 Mounting screws for the Item 800 PMC Carrier Item 800 Item 800 PMC #2 Item 800 PMC #1 Item 807 Item 807 Item 807 PMC #3 Item 800 PMC #4 Item 807 PMC #5 Item 800 Item 800...

  • Page 69: Pmc Carrier Daisy-Chain

    Mezzanine PMC Carrier FIGURE 6-4 Mounting the PMC modules PMC Module PMC #3 PMC #4 PMC Module PMC #5 PMC Module Step 3: Reassemble the unit Fasten the PMC Carrier board to the M52xx using screws as shown in Figure 6-3 PMC Carrier Daisy-Chain The P1 connector of the PMC Carrier board provides a daisy-chain bypass for the signals BG[3:0]* and IACKIO*.

  • Page 70: Functional Description

    Functional Description 6.4 Functional Description System Overview The Mezzanine PMC Carrier has 3 PMC slots which adds an extra PCI bus to bridge the two existing busses on the M52xx board. There are two bridges 64bit wide and operate at 33Mhz. These bridges provide a connection from the M52xx bus to the PMC Carrier bus.

  • Page 71: Interrupt Routing

    Mezzanine PMC Carrier Interrupt routing The PMC Carrier board has four interrupts from each of the three PMCs. These are routed (multiplexed) to the M52xx board via an interrupt routing PLD (Programmable Logic Device). The PMC Carrier board will distribute these interrupts to the base board interrupt destinations according to the routing tables in “Interrupt Routing”...

  • Page 72: Debug Functions

    A status register where the value of the interrupt signals from the PMC slots are available. Both functions are accessed through the use of the GPIO pins on one of the P2P bridges. Contact VMETRO for more details. Issued June 20, 2007...

  • Page 73: Vme Connectors On Mezz-X500

    Mezzanine PMC Carrier 6.5 VME Connectors on MEZZ-x500 VME P1 Connector on MEZZ-x500F VME P1 Connector TABLE 6-4. pin# row Z row A row B row C row D BG0IN* 1) BG0OUT* 1) BG1IN* 1) BG1OUT* 1) BG2IN* 1) BG2OUT* 1) BG3IN* 1) BG3OUT* 1) IACKIN* 1)

  • Page 74: Vme P2 Connector On Mezz-X500F

    VME Connectors on MEZZ-x500 VME P2 Connector on MEZZ-x500F VME P2 Connector TABLE 6-5. pin# row Z row A row B row C row D Jn4(4)-2 Jn4(5)-2 Jn4(5)-1 Jn4(4)-1 Jn4(5)-4 Jn4(5)-3 Jn4(4)-3 Jn4(4)-5 Jn4(5)-6 Jn4(5)-5 Jn4(4)-4 Jn4(5)-8 Jn4(5)-7 Jn4(4)-6 Jn4(4)-8 Jn4(5)-10 Jn4(5)-9 Jn4(4)-7...

  • Page 75: Pmc Connector Pinouts On Pmc Carrier (Mezz-X500F)

    Mezzanine PMC Carrier 6.6 PMC Connector Pinouts on PMC Carrier (MEZZ-x500F) PMC Connector Pinouts - Jn1, Jn2 and Jn3 for all PMC slots on MEZZ-x500F The pinouts for PMC connectors Jn1, Jn2 and Jn3 on the MEZZ-x500F (all three PMC slots) are the same as for the PMC connectors Jn1, Jn2 and Jn3 on the M52xx board.

  • Page 76: Pmc Connector Pinouts - Jn4 For Pmc Slot 4 On Mezz-X500F

    PMC Connector Pinouts on PMC Carrier (MEZZ-x500F) PMC Connector Pinouts - Jn4 for PMC slot 4 on MEZZ-x500F Jn4 64 Bit PCI Pinouts for PMC connector Jn4, PMC slot 4 on MEZZ-x500F TABLE 6-6. Pin# Signal Name Signal Name Pin# P2-D1 P2-Z1 P2-D2...

  • Page 77: Pmc Connector Pinouts - Jn4 For Pmc Slot 5 On Mezz-X500F

    Mezzanine PMC Carrier PMC Connector Pinouts - Jn4 for PMC slot 5 on MEZZ-x500F Jn4 64 Bit PCI Pinouts for PMC connector Jn4, PMC slot 5 on MEZZ-x500F TABLE 6-7. Pin# Signal Name Signal Name Pin# P2-C1 P2-A1 P2-C2 P2-A2 P2-C3 P2-A3 P2-C4...

  • Page 78: Miscellaneous Functions

    Miscellaneous Functions Issued June 20, 2007 M5000 Series: User Guide...

  • Page 79: Jtag Chain

    Each segment is used for a specific set of similar devices, and can be accessed separately from the remaining parts of the JTAG chain. This allows tools that only support certain devices to be used by only accessing the segment with supported devices. For more information please contact VMETRO. M5000 Series: User Guide Issued June 20, 2007...

  • Page 80: Reset Network

    Reset Network 7.2 Reset Network The board reset network is centralized around the reset PLD. Output reset signals are routed first to the reset PLD before being propagated to the other board components. The primary sources of reset are the power-up reset controller and reset button. Other sources are various software resets from the processor, PCI-X to PCI-X bridges, VME reset, RACEway reset and PMC modules etc.

  • Page 81: Interrupt Routing

    Miscellaneous Functions 7.3 Interrupt Routing In order to support a flexible interrupt routing mechanism, all interrupt source and destination signals are routed to a PLD which provides the actual routing between sources and destinations: FIGURE 7-1 Interrupt Routing PCIX-to-PCIX PCIX-to-PCIX Dual FC Dual FC Bridge...
  • Page 82 Interrupt Routing Interrupt routing for PPMC#1 Source PPMC2 MEZZ PXB++ Universe PPC Bridge 1 Bridge 2 Bridge 3 A,B,C,D A,B,C,D A,B,C,D I0,I1 Destination I0,I1 Interrupt routing for Universe II Source PPMC1 PPMC2 MEZZ PXB++ Bridge 1 Bridge 2 Bridge 3 A,B,C,D A,B,C,D A,B,C,D A,B,C,D Destination Issued June 20, 2007...

  • Page 83: Temperature Sensors

    The PowerPC processor communicates with the sensors via its second I2C bus. The type of component used is Maxim MAX1731. Contact VMETRO for more information. M5000 Series: User Guide...

  • Page 84: Power Supplies

    Power Supplies 7.4 Power Supplies The main sources of power are 5V and ±12V supplied by the VME backplane. The 5V power source is used to generate the required component voltages, ±12V is routed directly to the PMC sites. Issued June 20, 2007 M5000 Series: User Guide...
  • Page 85 Miscellaneous Functions M5000 Series: User Guide Issued June 20, 2007...

  • Page 86: Appendixes

    APPENDIXES Issued June 20, 2007 M5000 Series: User Guide...
  • Page 87 M5000 Series: User Guide Issued June 20, 2007...

  • Page 88: Pld Registers

    PLD Registers Issued June 20, 2007 M5000 Series: User Guide...

  • Page 89: Miscellaneous Pld Registers

    PLD Registers A-1 Miscellaneous PLD Registers The PLD registers can be accessed by the processor in following address range: PLD Registers TABLE A-1. Mnemonic Register Address Access Size PPC_BOOT PowerPC Boot Options 0x00 4 bits RST_SERIAL Reset and Serial Line Management 0x01 6 bits MISC...
  • Page 90 Miscellaneous PLD Registers PPC_BOOT PPC_BOOT_SPROM_WE# PowerPC Boot SPROM devices are write-protected (1) or enabled (0) (Read-Only) PPC_SPROM_WE# PowerPC MFS SPROM device is write-protected (1) or enabled (0) (Read-Only) PPC_FLASH_MON_WE# PowerPC FLASH device (Monitor part) is write-protected (1) or enabled (0) (Read-Only) PPC_FLASH_WE# PowerPC FLASH device is write-protected (1) or enabled (0) (Read-Only)

  • Page 91: Table A-2.Clock Speed Display

    PLD Registers PCI_CFG PMC2_PCIX PMC#2 PCI(-X) Bus Mode (Read-Only): set to 1 if PCI-X mode detected on PCI(-X) bus where PMC site #2 is located, 0 otherwise PMC1_PCIX PMC#1 PCI(-X) Bus Mode (Read-Only): set to 1 if PCI-X mode detected on PCI(-X) bus where PMC site #1 is located, 0 otherwise PMC2_CLK1 PMC#2 PCI(-X) Bus Clock Speed Bit 1 (Read-Only): set to 1 if clock speed...

  • Page 92: Interrupt Registers

    Miscellaneous PLD Registers INTERRUPT Registers Address is offset from PLD base Address. Interrupt Registers TABLE A-3. Address Register[7-4] Register[3-0] 0x04 Ethernet 0x05 P2P1_P P2P2_P 0x06 P2P3_P P2P1_S 0x07 P2P2_S P2P3_S 0x08 FC_A FC_B 0x09 PMC1_A PMC1_B 0x0A PMC1_C PMC1_D 0x0B PMC2_A PMC2_B 0x0C...
  • Page 93 PLD Registers M5000 Series: User Guide Issued June 20, 2007...

  • Page 94: Universe Iid Configuration Examples

    Universe IID Configuration Examples Issued June 20, 2007 M5000 Series: User Guide...

  • Page 95: General Information

    Universe IID Configuration Examples B-1 General Information Note – The 'Universe IID' PCI-VME Bridge, performs byte swapping of the data lanes on all transactions between VMEbus and PCI bus. This is also the case for accesses to the internal registers. The internal register bank is located on the 'PCI side' of the byte swapping.

  • Page 96: Vmebus Slave Images

    VMEbus Slave Images B-2 VMEbus Slave Images PCI Master Enable In addition to the configuration registers for the VMEbus slave images, one control register bit is essential for mapping VMEbus cycles to PCI bus cycles through the Universe IID. The PCI master enable ('BM') bit located in the PCI_CSR register space (offset: 0x004).

  • Page 97: Table B-1.Vme_Rai Setup

    Universe IID Configuration Examples VMEbus Register Access Image In this configuration example, the VMEbus Register Access Image is set up by use of the DIP switch and jumpers. VME_RAI Setup TABLE B-1. Action: Result: SW3-3 ON VME_RAI is enabled. SW3-1 ON, SW3-2 OFF VME_RAI is mapped in A24 address space.

  • Page 98: Table B-3.Vme Slave Image 1 - Setup

    VMEbus Slave Images VMEbus Slave Image 1 The VMEbus Slave Image 1 is set up to map A24 accesses, in the address range 0x100000- 0x3FFFFF, from VMEbus to I/O Cycles on the PCI bus, with PCI addresses starting from 0x02100000. VME Slave image 1 - setup TABLE B-3.

  • Page 99: Table B-5.Initialization Sequence For Vmebus Slave Image Config. Example

    Universe IID Configuration Examples Initialization Sequence By performing the list of cycles shown in the table below, the mapping for this configuration example is achieved. Initialization sequence for VMEbus slave image config. example. TABLE B-5. Write from VME PCI Data 1) Result: D:0x0000.0000 to A:0x000F04 0x0000.0000...

  • Page 100: Pci Slave Images

    PCI Slave Images B-3 PCI Slave Images The VME_RAI, described in the 'VMEbus Slave Images' section, is also utilized to set up PCI slave images in the examples below. PCI Target Enable - Memory & I/O Space In addition to the configuration registers for the PCI slave images, two control register bits are essential for mapping PCI bus cycles to VMEbus cycles through the Universe II.

  • Page 101: Table B-6.Pci Slave Image 0 Setup

    Universe IID Configuration Examples PCI Slave Image 0 In this configuration example, the PCI Slave Image 0 is set up to map PCI I/O Space transactions, in the address range 0x0-0xFFF, to A24, D16 VMEbus cycles in the address range 0x1000-0x1FFF. PCI slave image 0 setup.

  • Page 102: Table B-8. Pci Slave Image 2 Setup

    PCI Slave Images PCI Slave Image 2 PCI Slave Image 2 is set up to map PCI Memory Space transactions, in the address range 0x4000.0000-0x5FFF.FFFF to A32, D64 VMEbus cycles, in the address range 0x0000.0000- 0x1FFF.FFFF. PCI slave image 2 setup TABLE B-8.
  • Page 103 Universe IID Configuration Examples M5000 Series: User Guide Issued June 20, 2007...

  • Page 104: Vme64 Configuration Rom

    VME64 Configuration ROM A VME64 Configuration SPROM is included in the board design. This SPROM is accessible from the processor via a set of I/O pins on the third PCIX-to-PCIX bridge. The general content layout is described in the ANSI/VITA 1.1.1997 specification (page 53).

  • Page 105: Table C-1.Vme64 Configuration Rom

    0xFF Not to be used 'C'. Used to identify valid CR. 'R'. Used to identify valid CR. 24 bit IEEE Assigned Manufacturers ID. 0x006046 = VMETRO Board ID 31-24 Board ID 23-16 Board ID 15-8 M5000 Series: User Guide Issued June 20, 2007...

  • Page 106: Table C-2.Cr Entry: Board Id Offset: 0X00033-0X0003F

    VME64 configuration ROM TABLE C-1. Board ID 7-0 Revision ID 31-24 Revision ID23-16 Revision ID 15-8 Revision ID 7-0 Pointer to null terminated ASCII string. Revision ID (VMETRO Assigned) 0x000000 = No string 5F-7B Reserved for future use 0x00 Not used...

  • Page 107: Table C-4.Cr Entry: Revision Id Offset: 0X00043-0X0004F

    VME64 Configuration ROM Assigned Board ID Values TABLE C-3. Field Bit(s) Values 31-24 0x02=PowerMIDAS Product Family VME-P0 Connector: 0 = Not Mounted Family Specific Number 1 = Mounted PCI-to-RACEway Bridge: 0 = Not Mounted 1 = Mounted 21:18 Base Board Front Panel Configuration: 0 = RS-232 1 = RS-232 / Ethernet 2 = RS-232 / Ethernet / 1x Fibre Channel...

  • Page 108: Table C-5.Revision Id Description

    Revision ID Description TABLE C-5. Field Bits Description Family Specific Number 31-16 Reserved PCB Revision 15:12 PCB Revision number. (Start at 0xA and wrap from 0xF to 0x0) Reserved 11:8 '0000' ECO Level ECO Level indicator. (Start at 0x00 and go from 0x09 to 0x0A) Issued June 20, 2007 M5000 Series: User Guide...
  • Page 109 VME64 Configuration ROM M5000 Series: User Guide Issued June 20, 2007...

  • Page 110: Vme Connector Pinout

    VME Connector Pinout Issued June 20, 2007 M5000 Series: User Guide...

  • Page 111: General Description

    VME Connector Pinout D-1 General Description The abbreviation "NC" means Not Connected. The description "Jn4-1", Jn4-2", etc. used in the pinout table for P2 connector means the pins 1, 2, etc. on connector Jn4 on PMC slot 2. M5000 Series: User Guide Issued June 20, 2007...

  • Page 112: Vme P0 Connector For All Models

    VME P0 Connector for all models D-2 VME P0 Connector for all models Defined in DY4 StarLink PMC manual Pinout is compatable with DY4 Starlink PMC Module and Rear Transition Module. P0 pinout for all models TABLE D-1. PMC#2-P4 Pin VME-P0 Pin Signal Description Link A Pair 3 Rx+...

  • Page 113: Table D-1.P0 Pinout For All Models

    VME Connector Pinout P0 pinout for all models TABLE D-1. Link C Pair 3 Rx- Link C Pair 3 Tx- Link C Pair 2 Rx+ Link C Pair 2 Tx+ Link C Pair 2 Rx- Link C Pair 2 Tx- Link C Pair 1 Rx+ Link C Pair 1 Tx+ Link C Pair 1 Rx-...

  • Page 114: Vme P1 Connector For All Models

    VME P1 Connector for all models D-3 VME P1 Connector for all models VME P1 Connector TABLE D-2. pin# row Z row A row B row C row D D[0] BBSY* D[8] +5V1) D[1] BCLR* D[9] GND1) D[2] ACFAIL* D[10] D[3] BG0IN* D[11]...

  • Page 115: Vme P2 Connector For Non-R Model

    VME Connector Pinout D-4 VME P2 Connector for non-R model P2 pinout for non-R model TABLE D-3. pin# row Z row A row B row C row D Jn4-2 Jn4-1 Jn4-3 Jn4-5 Jn4-4 A[24] Jn4-6 Jn4-8 A[25] Jn4-7 A[26] Jn4-9 Jn4-11 A[27] Jn4-10...

  • Page 116: Vme P2 Connector For -R Models

    VME P2 Connector for -R models D-5 VME P2 Connector for -R models P2 pinout for -R model TABLE D-4. pin# row Z row A row B row C row D XCLKI XRESETIO* pIO09 XSYNCI* pIO08 A[24] A[25] pIO07 pIO06 A[26] A[27] pIO11...
  • Page 117 VME Connector Pinout M5000 Series: User Guide Issued June 20, 2007...

  • Page 118: Pmc Connector Pinout

    PMC Connector Pinout Issued June 20, 2007 M5000 Series: User Guide...

  • Page 119: General Description

    PMC Connector Pinout E-1 General Description “NC” means Not Connected. “PU” and “PD” mean that the connector pin is connected to +5V via a pull up resistor or to ground (GND) via a pull down resistor respectively. Connections to the VME P2 connector are denoted as P2-[row][pin]. Example: P2-D1 means connection to pin 1 in row D of the VME P2 connector.

  • Page 120: Pmc Connector Pinout - Jn1 For Both Pmc Slots On All Models

    PMC Connector Pinout - Jn1 for both PMC slots on all Models E-2 PMC Connector Pinout - Jn1 for both PMC slots on all Models Jn1 64 Bit PCI Pinout for PMC connector Jn1 (both slots/all models) TABLE E-1. Pin# Signal Name Pin# Signal Name...

  • Page 121: Pmc Connector Pinout - Jn2 For Both Pmc Slots On All Models

    PMC Connector Pinout E-3 PMC Connector Pinout - Jn2 for both PMC slots on all Models Jn2 64 Bit PCI Pinout for PMC connector Jn2 (both slots/all models) TABLE E-2. Pin# Signal Name Pin# Signal Name +12V PD (TRST#) PD (TMS) NC (TDO) PD (TDI) NC (PCI-RSVD)

  • Page 122: Pmc Connector Pinout - Jn3 For Both Pmc Slots On All Models

    PMC Connector Pinout - Jn3 for both PMC Slots on all Models E-4 PMC Connector Pinout - Jn3 for both PMC Slots on all Models Jn3 64 Bit PCI Pinout for PMC connector Jn3 (both slots/all models) TABLE E-3. Pin# Signal Name Pin# Signal Name...

  • Page 123: Pmc Connector Pinout - Jn4 For Pmc #1 & Pmc #2

    PMC Connector Pinout E-5 PMC Connector Pinout - Jn4 for PMC #1 & PMC #2 Jn4 64 Bit PCI PMC#1-to-VME P2 column only valid for non-Raceway models, PMC#2-to-VME P0 column only valid for P models. Pinout for PMC connector Jn4, PMC slot 1 & 2 TABLE E-4.
  • Page 124 PMC Connector Pinout - Jn4 for PMC #1 & PMC #2 (Continued)Pinout for PMC connector Jn4, PMC slot 1 & 2 TABLE E-4. BTX0+ Link B Pair 0 Transmit data + CRX3- Link C Pair 3 Receive data - CTX3- Link C Pair 3 Transmit data - CRX3+ Link C Pair 3 Receive data +...
  • Page 125 PMC Connector Pinout M5000 Series: User Guide Issued June 20, 2007...

  • Page 126: Mtbf Values

    MTBF Values The Mean Time Between Failures (MTBF) values given here are calculated estimations representing the inherent reliability of the M5000 series SBCs. The prediction is done according to the Inherent Model in PRISM v1.5 (System reliability assessment tool). PRISM contains experience data and methods for predicting component reliability.

  • Page 127: Table F-1.Mtbf Values (Hours)

    MTBF Values MTBF Values (Hours) TABLE F-1. Model GB (25ºC) (35ºC) (40ºC) (50ºC) (50ºC) (75ºC) M5210RP-EFF 1 259 400 635 280 399 230 195 230 116 280 48 307 M5210-JEJ 1 021 000 551 000 361 000 173 000 112 000 46 000 M5210-GEG 1 106 000...
  • Page 128 Ordering Information Models AMCC 440GX 133 MHz High Speed RJ45 RJ45 Optical PowerPC PCI-X PMC Streaming 10/100 Optical 2Gb/s Gigabit Gigabit Processor Positions Memory Ethernet Fibre Channel Ethernet Ethernet 256MiB M5210-EF0 256MiB M5210-JEJ 256MiB M5210-JFJ 256MiB M5210-JFF 256MiB M5210-GEG 256MiB M5210-GFG 256MiB M5210-GFF...
  • Page 129 Information about 3rd party drivers and HW that is used. • North and South America Telephone Support (281) 584-0728 (281) 584-9034 Website http://www.vmetro.com/support Europe and the rest of the world Telephone Support +47 23 17 28 00 +47 23 17 28 01 Website http://www.vmetro.com/support...
  • Page 130 References The Fibre Channel Industry Association (FCIA) http://www.fibrechannel.org American National Standards Institute http://www.ansi.org Component Manufacturers Available Vendor Component documentation Tundra Universe II (VME-PCI Bridge) User Manual http://www.tundra.com Manual Addendum Device Errata Application Notes AMCC 440GX Processor Processor http://www.amcc.com/ Developers Manual Application Notes and more PLX Technology...
  • Page 131 M5000 Series: User Guide Issued June 20, 2007...

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