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Alinx ZYNQ UltraScale+ ACU5EV Manual

Fpga development board
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ZYNQ UltraScale+
FPGA Development Board
ACU5EV
System on Module

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Summary of Contents for Alinx ZYNQ UltraScale+ ACU5EV

  • Page 1 ZYNQ UltraScale+ FPGA Development Board ACU5EV System on Module...

  • Page 2: Version Record

    ZYNQ Ultrascale + FPGA Board ACU5EV User Manual Version Record Version Date Release By Description Rev 1.1 2021-04-24 Rachel Zhou First Release Amazon Store: https://www.amazon.com/alinx 2 / 34...

  • Page 3: Table Of Contents

    Part 5: eMMC Flash.................... 18 Part 6: Clock configuration.................20 Part 7: LED......................23 Part 8: Power Supply..................24 Part 9: ACU5EV Core Board Size Dimension..........26 Part 10: Board to Board Connectors pin assignment........27 Amazon Store: https://www.amazon.com/alinx 3 / 34...

  • Page 4: Part 1: Acu5Ev Core Board Introduction

    PL side (HP I/O: 96, HD I/O: 84). The wiring between the XCZU5EV chip and the interface has been processed with equal length and differential, and the core board size is only 3.15*2.36 (inch), which is very suitable for secondary development. Amazon Store: https://www.amazon.com/alinx 4 / 34...
  • Page 5 ZYNQ Ultrascale + FPGA Board ACU5EV User Manual Figure 1-1: ACU5EV Core Board (Front View) Amazon Store: https://www.amazon.com/alinx 5 / 34...

  • Page 6: Part 2: Zynq Chip

    Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end contains a wealth of programmable logic units, DSP and internal RAM. . Figure 2-1 detailed the Overall Block Diagram of the ZU5EV Chip. Figure 2-1: Overall Block Diagram of the ZYNQ ZU5EV Chip Amazon Store: https://www.amazon.com/alinx 6 / 34...
  • Page 7 The main parameters of the PL logic part are as follows:  Logic Cells: 256.2K  Flip-flops: 234.24K  Look-up-tables (LUTs): 117.12K  Block RAM: 5.1Mb  Clock Management Units (CMTs): 4 Amazon Store: https://www.amazon.com/alinx 7 / 34...
  • Page 8 ZYNQ Ultrascale + FPGA Board ACU5EV User Manual  DSP Slices: 1248  Video Codec Unit (VCU): 1  PCIE3.0: 2  GTH 12.5Gb/s Transceiver: 4 XCZU5EV-2SFVC784I chip speed grade is -2, industrial grade, package is SFVC784 Amazon Store: https://www.amazon.com/alinx 8 / 34...

  • Page 9: Part 3: Ddr4 Dram

    PCB design to ensure high-speed and stable operation of DDR4. The hardware connection of DDR4 SDRAM on the PS Side is shown in Figure 3-1: Amazon Store: https://www.amazon.com/alinx 9 / 34...
  • Page 10 ZYNQ Ultrascale + FPGA Board ACU5EV User Manual Figure 3-1: DDR3 DRAM schematic diagram The hardware connection of DDR4 SDRAM on the Pl Side is shown in Figure 3-2: Figure 3-2: DDR3 DRAM schematic diagram Amazon Store: https://www.amazon.com/alinx 10 / 34...
  • Page 11 AH19 PS_DDR4_DQ7 PS_DDR_DQ7_504 AG19 PS_DDR4_DQ8 PS_DDR_DQ8_504 AF22 PS_DDR4_DQ9 PS_DDR_DQ9_504 AH22 PS_DDR4_DQ10 PS_DDR_DQ10_504 AE22 PS_DDR4_DQ11 PS_DDR_DQ11_504 AD22 PS_DDR4_DQ12 PS_DDR_DQ12_504 AH23 PS_DDR4_DQ13 PS_DDR_DQ13_504 AH24 PS_DDR4_DQ14 PS_DDR_DQ14_504 AE24 PS_DDR4_DQ15 PS_DDR_DQ15_504 AG24 PS_DDR4_DQ16 PS_DDR_DQ16_504 AC26 PS_DDR4_DQ17 PS_DDR_DQ17_504 AD26 Amazon Store: https://www.amazon.com/alinx 11 / 34...
  • Page 12 PS_DDR4_DQ37 PS_DDR_DQ37_504 PS_DDR4_DQ38 PS_DDR_DQ38_504 PS_DDR4_DQ39 PS_DDR_DQ39_504 PS_DDR4_DQ40 PS_DDR_DQ40_504 PS_DDR4_DQ41 PS_DDR_DQ41_504 PS_DDR4_DQ42 PS_DDR_DQ42_504 PS_DDR4_DQ43 PS_DDR_DQ43_504 PS_DDR4_DQ44 PS_DDR_DQ44_504 PS_DDR4_DQ45 PS_DDR_DQ45_504 PS_DDR4_DQ46 PS_DDR_DQ46_504 PS_DDR4_DQ47 PS_DDR_DQ47_504 PS_DDR4_DQ48 PS_DDR_DQ48_504 PS_DDR4_DQ49 PS_DDR_DQ49_504 PS_DDR4_DQ50 PS_DDR_DQ50_504 PS_DDR4_DQ51 PS_DDR_DQ51_504 PS_DDR4_DQ52 PS_DDR_DQ52_504 PS_DDR4_DQ53 PS_DDR_DQ53_504 Amazon Store: https://www.amazon.com/alinx 12 / 34...
  • Page 13 PS_DDR4_A6 PS_DDR_A6_504 PS_DDR4_A7 PS_DDR_A7_504 AA23 PS_DDR4_A8 PS_DDR_A8_504 AA22 PS_DDR4_A9 PS_DDR_A9_504 AB23 PS_DDR4_A10 PS_DDR_A10_504 AA25 PS_DDR4_A11 PS_DDR_A11_504 AA26 PS_DDR4_A12 PS_DDR_A12_504 AB25 PS_DDR4_A13 PS_DDR_A13_504 AB26 PS_DDR4_WE_B PS_DDR_A14_504 AB24 PS_DDR4_CAS_B PS_DDR_A15_504 AC24 PS_DDR4_RAS_B PS_DDR_A16_504 AC23 PS_DDR4_ACT_B PS_DDR_ACT_N_504 Amazon Store: https://www.amazon.com/alinx 13 / 34...
  • Page 14 PL_DDR4_DQ0 IO_L24N_T3U_N11_64 PL_DDR4_DQ1 IO_L24P_T3U_N10_64 PL_DDR4_DQ2 IO_L23N_T3U_N9_64 PL_DDR4_DQ3 IO_L23P_T3U_N8_64 PL_DDR4_DQ4 IO_L21N_T3L_N5_AD8N_64 PL_DDR4_DQ5 IO_L21P_T3L_N4_AD8P_64 PL_DDR4_DQ6 IO_L20N_T3L_N3_AD1N_64 PL_DDR4_DQ7 IO_L20P_T3L_N2_AD1P_64 PL_DDR4_DQ8 IO_L18N_T2U_N11_AD2N_64 PL_DDR4_DQ9 IO_L18P_T2U_N10_AD2P_64 PL_DDR4_DQ10 IO_L17N_T2U_N9_AD10N_64 PL_DDR4_DQ11 IO_L17P_T2U_N8_AD10P_64 PL_DDR4_DQ12 IO_L15N_T2L_N5_AD11N_64 PL_DDR4_DQ13 IO_L15P_T2L_N4_AD11P_64 PL_DDR4_DQ14 IO_L14N_T2L_N3_GC_64 PL_DDR4_DQ15 IO_L14P_T2L_N2_GC_64 PL_DDR4_DM0 IO_L19P_T3L_N0_DBC_AD9P_64 Amazon Store: https://www.amazon.com/alinx 14 / 34...
  • Page 15 PL_DDR4_A10 IO_L4N_T0U_N7_DBC_AD7N_64 PL_DDR4_A11 IO_L7N_T1L_N1_QBC_AD13N_64 PL_DDR4_A12 IO_L6N_T0U_N11_AD6N_64 PL_DDR4_A13 IO_L1N_T0L_N1_DBC_64 PL_DDR4_BA0 IO_T1U_N12_64 PL_DDR4_BA1 IO_L5N_T0U_N9_AD14N_64 PL_DDR4_RAS_B IO_T2U_N12_64 PL_DDR4_CAS_B IO_L5P_T0U_N8_AD14P_64 PL_DDR4_WE_B IO_L11N_T1U_N9_GC_64 PL_DDR4_ACT_B IO_L13N_T2L_N1_GC_QBC_64 PL_DDR4_CS_B IO_L6P_T0U_N10_AD6P_64 PL_DDR4_BG0 IO_L2N_T0L_N3_64 PL_DDR4_RST IO_L7P_T1L_N0_QBC_AD13P_64 PL_DDR4_CLK_N IO_L10N_T1U_N7_QBC_AD4N_64 PL_DDR4_CLK_P IO_L10P_T1U_N6_QBC_AD4P_64 PL_DDR4_CKE IO_T3U_N12_64 PL_DDR4_OTD IO_L19N_T3L_N1_DBC_AD9N_64 Amazon Store: https://www.amazon.com/alinx 15 / 34...

  • Page 16: Part 4: Qspi Flash

    ZYNQ chip. In the system design, the GPIO port functions of these PS ports need to be configured as the QSPI FLASH interface. Figure 4-1 shows the QSPI Flash in the schematic. Figure 4-1: QSPI Flash in the schematic Amazon Store: https://www.amazon.com/alinx 16 / 34...
  • Page 17 ZYNQ Ultrascale + FPGA Board ACU5EV User Manual Configure chip pin assignments: Signal Name Pin Name Pin Number MIO0_QSPI0_SCLK PS_MIO0_500 AG15 MIO1_QSPI0_IO1 PS_MIO1_500 AG16 MIO2_QSPI0_IO2 PS_MIO2_500 AF15 MIO3_QSPI0_IO3 PS_MIO3_500 AH15 MIO4_QSPI0_IO0 PS_MIO4_500 AH16 MIO5_QSPI0_SS_B PS_MIO5_500 AD16 Amazon Store: https://www.amazon.com/alinx 17 / 34...

  • Page 18: Part 5: Emmc Flash

    PS part of the ZYNQ UltraScale+. In the system design, it is necessary to configure the GPIO port function of the PS side as an EMMC interface. Figure 5-1 shows the part of eMMC Flash in the schematic diagram. Figure 5-1: QSPI Flash in the schematic Amazon Store: https://www.amazon.com/alinx 18 / 34...
  • Page 19 Pin Number MMC_DAT0 PS_MIO13_500 AH18 MMC_DAT1 PS_MIO14_500 AG18 MMC_DAT2 PS_MIO15_500 AE18 MMC_DAT3 PS_MIO16_500 AF18 MMC_DAT4 PS_MIO17_500 AC18 MMC_DAT5 PS_MIO18_500 AC19 MMC_DAT6 PS_MIO19_500 AE19 MMC_DAT7 PS_MIO20_500 AD19 MMC_CMD PS_MIO21_500 AC21 MMC_CCLK PS_MIO22_500 AB20 MMC_RSTN PS_MIO23_500 AB18 Amazon Store: https://www.amazon.com/alinx 19 / 34...

  • Page 20: Part 6: Clock Configuration

    PS system. The crystal is connected to the PS_PADI_503 and PS_PADO_503 pins of BANK503 of the ZYNQ chip. The schematic diagram is shown in Figure 6-2: Figure 6-2: Passive Crystal Oscillator for RTC Amazon Store: https://www.amazon.com/alinx 20 / 34...
  • Page 21 (MRCC) of PL BANK64. This global clock can be used to drive the DDR4 controller and user logic circuits in the FPGA. The schematic diagram of this clock source is shown in Figure 6-4 Amazon Store: https://www.amazon.com/alinx 21 / 34...
  • Page 22 ZYNQ Ultrascale + FPGA Board ACU5EV User Manual Figure 6-4: PL system clock source Clock pin assignment: Signal Name PL_CLK0_P PL_CLK0_N Amazon Store: https://www.amazon.com/alinx 22 / 34...

  • Page 23: Part 7: Led

    FPGA configuration program, the configuration LED light will light up. The LED Schematic in the Core Board is shown in Figure 7-1: Figure 7-1: LED Schematic in the Core Board Amazon Store: https://www.amazon.com/alinx 23 / 34...

  • Page 24: Part 8: Power Supply

    The core board uses a PMIC chip TPS6508641 to generate all the power required by the XCZU5EV chip. For the TPS6508641 power supply design, please refer to the power supply chip manual. The design block diagram is as follows: Amazon Store: https://www.amazon.com/alinx 24 / 34...
  • Page 25 In addition, the VCCIO power supply of BANK65 and BANK66 of XCZU5EV chip is provided by the carrier board, which is convenient for users to modify, but the maximum power supply cannot exceed 1.8V. Amazon Store: https://www.amazon.com/alinx 25 / 34...

  • Page 26: Part 9: Acu5Ev Core Board Size Dimension

    ZYNQ Ultrascale + FPGA Board ACU5EV User Manual Part 9: ACU5EV Core Board Size Dimension Figure 9-1: ACU5EV Core Board Size Dimension Amazon Store: https://www.amazon.com/alinx 26 / 34...

  • Page 27: Part 10: Board To Board Connectors Pin Assignment

    Pin assignment of board to board connector J29 J29 Pin Signal Name Pin Number J29 Pin Signal Name Pin Number B65_L2_N B65_L22_P B65_L2_P B65_L22_N B65_L4_N B65_L20_P B65_L4_P B65_L20_N B65_L1_N B65_L6_N B65_L1_P B65_L6_P B65_L7_P B65_L17_P B65_L7_N B65_L17_N Amazon Store: https://www.amazon.com/alinx 27 / 34...
  • Page 28 B65_L5_P B65_L18_N B65_L11_N B65_L8_P B65_L11_P B65_L8_N B65_L10_N B65_L24_N B65_L10_P B65_L24_P B66_L3_P B65_L12_P B66_L3_N B65_L12_N B66_L1_P B65_L13_N B66_L1_N B65_L13_P B66_L6_P B65_L21_P B66_L6_N B65_L21_N B66_L16_P B65_L23_P B66_L16_N B65_L23_N B66_L15_P B66_L5_N B66_L15_N B66_L5_P B66_L4_P B66_L2_P B66_L4_N B66_L2_N Amazon Store: https://www.amazon.com/alinx 28 / 34...
  • Page 29 Signal Name Pin Number B66_L14_P FPGA_TDI B66_L14_N FPGA_TCK B66_L22_P FPGA_TDO B66_L22_N FPGA_TMS B66_L19_N B66_L21_N B66_L19_P B66_L21_P B66_L24_P B66_L17_P B66_L24_N B66_L17_N B66_L23_N B25_L9_P B66_L23_P B25_L9_N B25_L5_N B25_L10_P B25_L5_P B25_L10_N B66_L18_N B25_L12_P B66_L18_P B25_L12_N B25_L4_N B25_L11_P Amazon Store: https://www.amazon.com/alinx 29 / 34...
  • Page 30 B26_L9_N B26_L2_N B26_L9_P B26_L2_P B26_L5_N B26_L4_N B26_L5_P B26_L4_P B26_L1_P B26_L12_P B26_L1_N B26_L12_N 505_CLK2_P 505_CLK1_P 505_CLK2_P 505_CLK1_P 505_CLK0_P 505_CLK3_P 505_CLK0_N 505_CLK3_N 505_TX3_P 505_TX1_P 505_TX3_N 505_TX1_N 505_RX3_P 505_TX0_P 505_RX3_N 505_TX0_N 505_TX2_P 505_RX1_P 505_TX2_N 505_RX1_N 505_RX2_P 505_RX0_P Amazon Store: https://www.amazon.com/alinx 30 / 34...
  • Page 31 AG14 B24_L12_N AA12 B24_L2_N AH14 B24_L3_P AG13 B24_L3_N AH13 B44_L12_N B44_L9_P AA11 B44_L12_P AB10 B44_L9_N AA10 B44_L10_N B44_L3_P AH12 B44_L10_P B44_L3_N AH11 B24_L11_N B44_L1_N AH10 B24_L11_P B44_L1_P AG10 B24_L9_N B24_L4_P AE13 B24_L9_P B24_L4_N AF13 Amazon Store: https://www.amazon.com/alinx 31 / 34...
  • Page 32 224_RX2_N 224_TX2_N 224_RX1_P 224_TX1_P 224_RX1_N 224_TX1_N 224_RX0_P 224_TX0_P 224_RX0_N 224_TX0_N Pin assignment of board to board connector J32 J32 Pin Signal Name Pin Number J32 Pin Signal Name Pin Number PS_MIO35 PS_MIO30 PS_MIO29 PS_MIO31 Amazon Store: https://www.amazon.com/alinx 32 / 34...
  • Page 33 PS_MIO57 PS_MIO36 PS_MIO54 PS_MIO37 PS_MIO27 PS_MIO28 PS_MIO77 PS_MIO59 PS_MIO76 PS_MIO60 PS_MIO61 PS_MIO39 PS_MIO62 PS_MIO38 PS_MIO63 PS_MIO65 PS_MIO40 PS_MIO66 PS_MIO44 PS_MIO67 PS_MIO45 PS_MIO68 PS_MIO47 PS_MIO64 PS_MIO48 PS_MIO69 PS_MIO41 PS_MIO74 PS_MIO32 PS_MIO73 PS_MIO46 PS_MIO72 PS_MIO50 PS_MIO71 Amazon Store: https://www.amazon.com/alinx 33 / 34...
  • Page 34 ZYNQ Ultrascale + FPGA Board ACU5EV User Manual PS_MIO49 PS_MIO75 PS_MIO34 PS_MIO70 PS_MIO26 PS_MIO43 PS_MIO24 AB19 PS_MIO51 PS_MIO25 AB21 PS_MIO42 PS_MIO33 VCCO_65 VCCO_66 VCCO_65 VCCO_66 VCCO_65 VCCO_66 +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V +12V Amazon Store: https://www.amazon.com/alinx 34 / 34...

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