Per Vices Noctar User Manual

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P E R V I C E S C O R P O R AT I O N

N O C TA R U S E R M A N U A L

Table of Contents

Summary of Contents for Per Vices Noctar

Page 1 P E R V I C E S C O R P O R AT I O N N O C TA R U S E R M A N U A L...
Page 3: Table Of Contents
Contents Change Log Preface Obligatory Warnings Speciﬁcations Installation Troubleshooting Command Line Utilities Graphical Utilities Usage Notes System Overview Noctar GPIO...
Page 4 4 per vices corporation On Latency and Performance FPGA Implementation FPGA Simulation and Test bench FPGA Programming Driver Implementation Appendix I: Mechanical Drawings Appendix I: Pin Descriptions Appendix II: GPIO Address Offsets Epilogue...
Page 5: Change Log
Change Log 2012-12-12: Rev A: Initial Release 2013-01-04: Rev B: Cleaning up some sections, ﬁxing typos, im- proving readability, note on input GPIO. 2013-01-23: Rev C: Adding section on testing ADC outputs. Adding IQ matching section. More cleanup and readability. 2013-02-03: Rev D: Adding additional notes on how decimation and interpolation works.
Page 7: Preface
Faced with a number of conﬂicting requirements, we have en- devoured to satisfy the broadest use cases possible, while trying to reduce the complexity necessary to operate Noctar. Our goal is to help you best utilize the ﬂexibility afforded by SDR technology.
Page 8 8 per vices corporation Our hope is that you will ﬁnd Noctar to be a useful and de- pendable companion in your engineering, development, and research efforts. We welcome your feedback; please feel free to contact us at: solutions@pervices.com A note on Langford...
Page 9: Obligatory Warnings
Per Vices neither assumes or authorizes any person to assume for it any other liability. Your use of this device is at your own risk. Per Vices shall not be liable for you for any damages, direct or indirect, incurred or arising from the use of this product.
Page 10 10 per vices corporation If you have any problems, please contact: solutions@pervices.com Speciﬁcations Every effort has been made to test and measure the validity of this equipment. However, we cannot guarantee the accuracy of speciﬁca- tions, and they may change at any time.
Page 11 11 ATTENTION RF TRANSMITTER This device is capable of RF transmission on bands or frequencies subject to regulatory oversight. Operators are responsible to ensure use of this device meets local regulatory and legal standards, as they may apply to you and the band of interest.
Page 13: Specifications
Down/Up Conversion, superhet ar- digital conversion, it is capable of processing up to signal bandwidths chitectures can be implemented using up to 200MHz from 100kHz to 4GHz. Noctar is compatible with Digital Down/Up Conversion on the FPGA. GnuRadio, and includes open source drivers.
Page 14 We test all devices on a 64 bit Arch Linux system running GnuRadio and the 3.4 kernel. We do not support the Linux 2.6 kernel. We have also successfully used Noctar on 64 bit Ubuntu systems. Some users have reported problems compiling our drivers on VM’s or 32 bit machines, especially those using Ubuntu, so we rec-...
Page 15 15 Speciﬁcation units Table 2: Observed Performance. Temperature These speciﬁcations reference Card Operating Temperature observations taken during in- Analogue ternal use and development. RF Tuning (ADF4351) 4400 Please note the Dynamic Range Dyn. Range (RX,TX) section for more information.
Page 16 16 per vices corporation Speciﬁcation units 2GHz Input RF Input Power Analysis Bandwidth Rx Chain SFDR 63.5 71.6 Input Rx Sensitivity -73.6 Input P1dB Tx Chain Power Gain SFDR Table 3: These speciﬁcations are intended to serve as a very...
Page 17: Installation
Reverse these steps for removal. Driver and Utility Installation The installation procedure is relatively straightforward; 1. Obtain a copy of the Noctar drivers. You can download them from the Per Vices site, or use the ones that may have been shipped with your device.
Page 18 18 per vices corporation Auto loading Initialization Routines You will have to initialize the device (by running langford_init) every time you restart your computer! You can make this easier by copying this ﬁle to your init scripts. Ubuntu Installation Ubuntu is not presently supported. Nevertheless, if you’re new to Ubuntu, here’s a step-by-step guide on getting yourself set up.
Page 19 The "langford" group is generally created when compiling the kernel modules, and ensures that your user will have all the permissions required to modify and use the noctar driver. This group is created to ensure that only authorized users (that is, users within the group) are able to conﬁgure or transmit on the radio device.
Page 20 An important note is that, prior to run- ning or using Noctar, we need to initialize it. Therefore: 1. Initialize noctar by running langford_init as root. Type the follow- ing into a terminal to create the charactor device in /dev/langford...
Page 21 21 (a) To generate the ﬂow graph, either press the ’F5’ key, or use ’Run > Generate’ from the top drop down menu. (b) To execute the ﬂow graph, either press the ’F6’ key, or use ’Run > Execute’ from the top drop down menu.
Page 22 1. To adjust the radio front end, we’ll use the noctar IO utility. We shall open this utility, in a separate terminal, while the ﬁrst wa- terfall plot is running.
Page 23 RF Gain: 255 ii. VGA Gain (I): 63 iii. VGA Gain (Q): 63 (c) Now, we’ll hit "Apply" in the Noctar IO panel to actually write those settings to the device. 4. Having updated the radio parameters, click on "Autoscale" again to rescale the waterfall plot.
Page 24 24 per vices corporation GnuRadio The easiest way to start using Noctar requires you to have a com- plete GnuRadio installation. GnuRadio may be including in your distributions package manager. If you want to use the utilities, en- sure that you pay special attention to satisfying all necessary (and optional) dependencies.
Page 25: Troubleshooting
Troubleshooting First, ensure that you’ve initialized the driver; # langford_init It may be necessary to rebuild the langford drivers after updating or upgrading your kernel. If you encounter runtime errors indicating the ﬁle doesn’t exist, ie; failed to open ’/dev/langford’: No such ﬁle or directory Runtime Error: can’t open ﬁle Then you may have to initialize the character device, using the lang- ford_init script;...
Page 26 If you’re unable to see anything on the waterfall plot, or if your out- put is saturated, you may need to adjust the radio gain. You may do this using the command line, or through the Noctar IO panel. More information on this utility is available in the Graphical Utilities chapter on page 29.
Page 27: Command Line Utilities
Command Line Utilities This section discusses the utilities available to read and write data from Noctar, how to use the control utility, and an illustration of the python IO application. Command Line Utilities Multiple command line utilities are used to control the functionality of the Noctar device.
Page 28 28 per vices corporation synthesizer), abstract the bit banging, and automatically conﬁg- ure on board chips. These utilities are also useful for debugging the calculation of values for the serial interface peripherals. For example, to debug the frequency synthesizer, you can use lang- ford_adf4350_util to write the register values in 32 bit hex values directly as a program argument.
Page 29: Graphical Utilities
When playing with the FM Rx Demo, you may want to also launch the Noctar IO panel in order to adjust the gain settings. Remember to correctly set the decimation and frequency in the NoctarIO panel settings prior to applying any settings - otherwise the ﬂow chart will...
Page 30 30 per vices corporation Figure 2: Screen capture of Noctar GUI controlling the re- ception of a simple GNU Radio Companion ﬂow chart. Figure 3: Screen capture us- ing GnuRadio Companion, and Noctar IO panel to view waterfall plot.
Page 31: Usage Notes
Usage Notes Receive Chain • This device is capable of very high gain - you might ﬁnd yourself saturating or overload the receiver. This can be easily solved by turning down the gain. The RF Front End has about 40dB dynamic range at the RF Attenuators.
Page 32 32 per vices corporation – When you want to turn off this feature to the default 2Vp-p, pass in -1 as the last parameter; langford_adc_util /dev/langford A IntRef -1 – There is a catch; you may have to remove RC10. It was origi-...
Page 33 33 Symbol Access Value Description Table 4: Test pattern register 1 7 to 3 not used 00000 (address 0x0014) bit descrip- 2 to 1 TESTPAT_SEL[2:0] digital test pattern select tion. From the ADC1210S series datasheet (NXP Semiconductors midscale / TI).
Page 34 34 per vices corporation Figure 4: These test points (found about the top left corner of the shield that is immedi- ately to the left of the DAC) directly access the second DAC channel while in baseband mode. - dropping a byte (8 bits) irrevocably corrupts data. If you ﬁnd yourself encountering this problem, increase the decimation to 2 or higher will avoid this problem.
Page 35 35 • To calculate Receive sample rate, after decimation, use the fol- sample,adc lowing formula; f , where F 125MSPS. rx,SR ADC,SR To illustrate, if you seek to reduce the sample rate by a factor of 8, three bits of decimation would be set (n...
Page 36 36 per vices corporation up some resources. This is easy to do while maintaining system (software, driver & RTL) integrity. Look for the null sink or the null source commented out near the FIFO and DSP chains. Simply replace the FIFO and DSP chain with the null source/sink.
Page 37: System Overview
System Overview Overview Noctar has independent RX and TX chains. Within each chain, there are two branches, a High branch, supporting RF frequencies (generally about 150-4000MHz), and a Low branch, supporting base band applications (usually from several hundred kHz through to 110MHz).
Page 39: Noctar Gpio
Noctar GPIO Noctar has ten user assignable IO pins. These pins, accessible The inputs are directly coupled through an IO header protruding from the bracket, allows you to to the FPGA - if you’re not care- build programs capable of communicating with outside equipment.
Page 40 - maybe you aren’t using the outputs, and really want to convert some of the IO inputs into outputs. With Noctar, this is easy! There are two parts to this - adding the pins to the FPGA, and including them in the driver.
Page 41 41 14. If this is a pin internal to the FPGA, then continue and make any other changes to the FPGA design as necessary. The remain- ing steps except for the last are not necessary. If this pin is to be accessed outside the FPGA, follow the remaining steps.
Page 43 On Latency and Performance If you’re reading this section it’s because you’re likely pushing boundries, or trying to accomplish something very neat. The de- fault ﬁrmware uses very conservative settings, so we encourage you to tweak the settings to signiﬁcantly improve your particular applica- tion We really want to encourage you to get the most out of our hardware, so...
Page 44 44 per vices corporation IQ Matching If you’re looking at this section, it’s likely because you’re looking at trying to get the most performance out of the board. You might even be asking yourself - why did you guys use two discrete ADCs? The answer comes down to cost - we’re trying to pack in a lot of per-...
Page 45 Quartus project ﬁle, along with the top level verilog including the Quartus Megafunctions, and the Altera PCIe hard IP. This is the DSP directory - it contains all the Per Vices IP necessary to implement the decimation, interpolation, ﬁltering, and digital down/up conversion. This directory includes a complete testbenches simulating the entire dsp chain using iVerilog.
Page 46 This includes automatic equalization and preemphasis. This module controls this functionality. A diagram detailing the FPGA system is shown in Figure 7. GPIO ADC clock domain Figure 7: Noctar FPGA sys- langford_qsys DcFifo64 TopRx oPCIeTx wRxDmaData...
Page 47 47 DSP - Digital Signal Processing System We use several DSP cores to deliver you the magic of SDR. Each DSP core occupies its own subdirectory in the dsp directory, with multiple DSP cores being integrated into the rx and tx DSP chains. The rx DSP chain is called TopRx and the tx DSP chain is called TopTx.
Page 48 48 per vices corporation This module allows for optional decimation by 2. This allows for lower digital transfer rates and narrower signal bandwidths while avoiding problems relating to aliasing. Tx DSP Chain -TopTx The Tx chain, shown in Figure 9, comprises of the following modules:...
Page 49 FPGA Simulation and Test bench Verifying DSP Cores Each DSP core can be tested separately or together. Two types of types of tests are done on each DSP core, each with their own pur- pose: 1. Simulation Quick results for ease of veriﬁcation Used to check functional accuracy of each core 2.
Page 50 50 per vices corporation All necessary ﬁles will be generated and the simulation will run. 4. After the simulation is complete, gtkwave will launch with the simulation results. You can view these results and compare them against your expectations. 5. If you wish, you can modify the test bench by editing the tb_iverilog.v ﬁle.
Page 51 51 6. Open the tb_altera.qpf project ﬁle located in the tb_altera directory of the DSP core of your choice. For example: dsp/HPF/tb_altera/tb_altera.qpf 7. In Quartus, click Processing > Start Compilation. This will gener- ate the design ﬁle. All timing and Once this is complete, you will get a message informing you of such.
Page 53 FPGA Programming We’ve made it easy to program the Noctar FPGA. You’re going to re- quire two things - a USB Blaster cable, which costs money, and a copy of the Quartus II software, which is gratis on the Altera website http://www.altera.com...
Page 54 54 per vices corporation (a) When the programming is complete, the Quartus program will indicate as such. 12. Turn off your computer. Note that you should do a cold shut down to ensure the device enumerates properly - a reboot doesn’t always do it.
Page 55 This document outlines the considerations taken into the design and implementation of the driver for the Noctar device. The goal is to allow you to easily add features, modify, or debug, the Noctar driver. The ﬁles required to compile the driver are located in the git://langford_driver directory.
Page 56 To illustrate, to a user mode program, a ﬁle write is used to transmit data toward the SDR and out into the real world. However, for Noctar , bus writes Noctar is a SDR device with an...
Page 57 During removal; 1. driver_remove This function is executed when a the Noctar device is removed or if the driver is unloaded. This function undoes all the tasks performed in driver_probe.
Page 58 58 per vices corporation IO Flow When the driver has completely loaded, it goes away into the back- ground, waiting for the character device ﬁle to be opened. When the device is opened, the driver sets up the computer for DMA transfers.
Page 59 59 Receive Data (High Frequency Branch) Rx data are provided in IQ pairs. Each IQ pair is 32 bits, with the I and Q components represented by two 16 bit signed integers. Specif- ically, the format for RX (reading from the /dev/langford device) on the high frequency RX stage is represented in Table 5.
Page 60 60 per vices corporation Transmission Data (High Frequency Branch) TX data are provided in IQ pairs. Each IQ pair is 16 bits. I is repre- sented as a 8 bit signed integer. Following I is Q also represented as a 8 bit singed integer.
Page 61 Appendix I: Mechanical Drawings...
Page 63 For the engineers, masochistic, or curious, this section exhaustively lists all the options you can change with langford. Consider this the hardware API that allows you to manipulate the data that Noctar collects If you’re not sure how these param-...
Page 64 64 per vices corporation N61LE, N62LE 0,1 Latch Enable pin of serial interface for RX and TX frequency synthesizer respectively. N61MUXOUT, N62MUXOUT 0,1 Multiplexor output pin of serial interface for RX and TX fre- quency synthesizer respectively. N61LD, N62LD 0,1 Lock detect pin of serial interface for RX and TX frequency syn-...
Page 65 65 N7SDO 0,1 Serial data from the serial interface for the the differential ADC VGA. DACIQSel 0,1 IQ framing pin for the DAC. Used for single port mode. DACReset 0,1 Reset pin for the DAC. Used also to enable pin mode.
Page 66 66 per vices corporation ADCASDIO, ADCBSDIO 0,1 Enable LVDS outputs for the ADC. By default, the data format is CMOS. Used also as the data pin to/from the ADC’s serial interface. ADCAnCS, ADCBnCS 0,1 Enable pin mode for the ADC. Used also as the chip select pin for the ADC’s serial interface.
Page 67 Peripherals > Microcontroller Peripherals in the Component Library. Currently, there are 6 32 bit registers. This following subsections summarizes the assignment of GPIO pins in the Noctar system. Assignment Table 9: PIO0 - Output - Ad-...
Page 68 68 per vices corporation Assignment Table 10: PIO1 - Output - Ad- N61CE dress offset: 0x00008100 - Physi- N61DATA cal output pins. N61CLK N61LE N62CE N62DATA N62CLK N62LE N3ENB N3HILO NASRxA NASTxA N7CLK N7CS N7SDI DACIQSel DACReset DACCSB DACSDIO DACSClk...
Page 69 69 Assignment Table 12: PIO3 - Output - Ad- RXPhase 31:0 dress offset: 0x00008300 - Phase increment for rx NCO Assignment Table 13: PIO4 - Output - Ad- TXPhase 31:0 dress offset: 0x00008400 - Phase increment for tx NCO...
Page 71 Epilogue «Take chances! Make mistakes ! Get messy!» Per Vices believes in the value of mistakes as research experience. We Ms. Frizzle encourage, whenever possible, that you try and limit your mistakes to the (mostly) reversible kind. However, we also appreciate those times when you...