1. Manuals
  2. Brands
  3. Lime Microsystems Manuals
  4. Computer Hardware
  5. LMS8001
  6. Reference manual

Lime Microsystems LMS8001 Reference Manual

Hide thumbs Also See for LMS8001:
Table of Contents

Advertisement

Quick Links

Download this manual
Lime Microsystems Limited
Surrey Technology Centre
Occam Road
The Surrey Research Park
Guildford, Surrey GU2 7YG
United Kingdom
Tel:
+44 (0) 1483 685 063
e-mail:
enquiries@limemicro.com
Chip version:
Chip revision:
Document version:
Document revision:
LMS8001
Reference Manual
LMS8001A, LMS8001B
1
1.0
0

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the LMS8001 and is the answer not in the manual?

Questions and answers

Related Manuals for Lime Microsystems LMS8001

Summary of Contents for Lime Microsystems LMS8001

  • Page 1 Lime Microsystems Limited Surrey Technology Centre Occam Road The Surrey Research Park Guildford, Surrey GU2 7YG United Kingdom Tel: +44 (0) 1483 685 063 e-mail: enquiries@limemicro.com LMS8001 Reference Manual Chip version: LMS8001A, LMS8001B Chip revision: Document version: Document revision:...

  • Page 3: Table Of Contents

    Contents Overview .......................... 1 Digital Logic Block Diagram ..................2 SPI interface ....................... 3 GPIO .......................... 4 Biasing & LDOs ......................6 Temperature Sensor ....................... 7 Channel and PLL profiles ....................8 MUXSEL Macro ......................9 Channel Control Logic ....................11 RF Channel Control Logic –...
  • Page 4 Register bank BiasLDOConfig (0x0010 – 0x001F) ..........34 Register bank Channel_x ..................38 Register bank HLMIXx ................... 44 Register bank PLL_CONFIGURATION (0x4000 – 0x401F) ........ 47 Register bank PLL_PROFILE_n ................51 LMS8001 Package Drawing ..................56 LMS8001 Pinout ......................57...

  • Page 5: Overview

    Overview LMS8001 (Figure 1.1) contains four RF channels, integrated PLL with programmable LO distribution, and auxiliary circuits, such as biasing block, integrated LDOs and a temperature sensor. Figure 1.1: LMS8001 Block Diagram...

  • Page 6: Digital Logic Block Diagram

    Digital Logic Block Diagram Digital logic implemented in LMS8001 is shown in Figure 2.1. It consists of SPI interface for communication, register banks, programmable GPIO, control logic for RF channels and PLL. There are four sets (profiles) per RF channel and eight sets (profiles) of PLL control signal values.

  • Page 7: Spi Interface

    Figure 2.1: LMS8001 Digital Block Diagram 2.1 SPI interface The functionality of LMS8001 is fully controlled by a set of internal registers which can be accessed through a serial SPI port interface. Both write and read operations are supported. The serial SPI port can be configured to run in 3 or 4 wire mode with the following pins used: ...

  • Page 8: Gpio

    0x001F 2.2 GPIO LMS8001 has flexible GPIO with nine individually programmable pins, whose structure is shown in Figure 2.5. GPIO pins can be used in several ways, from basic input/output to advanced control of RF channels and PLL. GPIO pin n direction is controlled by...
  • Page 9 GPIO_PE[n] bit of GPIOConfig_PE register. Output driver strength is controlled by GPIO_DS[n] bit of GPIOConfig_DS register. GPIO pin n state can be read from GPIO_IN[n] bit of GPIOInData register. When used as output, GPIO pin n can be configured to output the value of GPIO_OUT_SPIO[n], or the value of internal signals PLL_LOCK, VTUNE_LOW, VTUNE_HIGH or FAST_LOCK_ACT.

  • Page 10: Biasing & Ldos

    Biasing & LDOs LMS8001 biasing block, shown in Figure 3.1, generates all reference currents and voltages required for chip operation. External 10 kΩ resistor is used for calibration. Integrated LDOs allow operation from single supply voltage, and are fully programmable. LDOs can be individually controlled, allowing elaborate power management schemes.

  • Page 11: Temperature Sensor

    Temperature Sensor Integrated temperature sensor can be used for temperature compensation of RF channels. To use the temperature sensor, bias should be enabled by setting TEMP_SENS_EN=1 and clock by setting TEMP_SENS_CLKEN=1 in register TEMP_SENS. Temperature conversion is started by writing 1 to TEMP_START_CONV bit, which is cleared when the conversion is complete.

  • Page 12: Channel And Pll Profiles

    Channel and PLL profiles Channel and PLL control signals are grouped in signal groups, which are multiplexed simultaneously. Each signal group has four sets of values per channel, and eight sets of values for PLL. Collection of signal groups forms a profile. Group multiplexer control signals are generated by MUXSEL macros, controlled by registers listed in table below.

  • Page 13: Muxsel Macro

    MUXSEL Macro RF channel and PLL profiles are selected by multiplexer control signals. Each bit of multiplexer control signals is generated by MUXSEL macro, shown in Figure 6.1. Control signal can be generated from GPIO inputs (INTERNAL=0) or from internal register (INTERNAL=1).
  • Page 14 Address Register Name (Reset Value) Default Bitfield Name Mode Description Invert the SELn signal of Group control signals. 0 – No inversion, Group_SELn_INVERT 1 – Signal is inverted. GPIO mask for SELn signal of Group control signals 000000000 Group_SELn_MASK<8:0> multiplexer.

  • Page 15: Channel Control Logic

    Channel Control Logic There are two options of LMS8001. The difference is in the architecture of the RF channels. Option LMS8001A contains RF channels with LNA, two mixers and power amplifier (Figure 7.1), whereas LMS8001B channel is comprised of high-linearity mixer (HLMIX) only (Figure 7.3).

  • Page 16: High-Linearity Mixer (Hlmix) Control Logic - Lms8001B

    possible configurations. Signal group multiplexer control signals are generated by MUXSEL macro, allowing the control via GPIO pins, SPI registers, or combination of them. Figure 7.2: RF Channel control signal multiplexing Registers relevant to RF Channel configuration are grouped into register banks Channel_x (x=A,B,C,D).
  • Page 17 Figure 7.4: HLMIX control signal multiplexing Registers relevant to HLMIX configuration are grouped into register banks HLMIXx (x=A,B,C,D).

  • Page 18: Hfpll

    It is fully self-contained synthesizer and requires no external parts to cover the full specified frequency range of the device using convenient reference frequency values between 10 and 50 MHz. Besides, LMS8001 IC can use external LO signal from the dedicated input pins.

  • Page 19: Reference

    Block diagram of the complete frequency synthesizer of the LMS8001 IC is shown in the Figure 8.1. Three main sub-parts are indicated: reference clock buffer, HFPLL core and LO distribution network. Details about mentioned sub-parts and its containing circuits will be given in the following sections.

  • Page 20: Hfpll Core

    8.4 HFPLL CORE The HFPLL core block diagram is shown in Figure 8.4. It is classic type-II, fourth-order PLL core which uses fractional-N technique with 3 order noise shaping to synthesize and fine adjust the LO frequency value. HFPLL core can also be operated in integer-N mode, which gives the best phase noise performance at the expense of reduced frequency resolution of the synthesizer.

  • Page 21: Loop Filter

    HFPLL core has achieved phase-locked condition. PLL_LOCK high logic value means that HFPLL has achieved phase-locked state. LMS8001 HFPLL core also contains two comparators which can be used to detect if the VTUNE control voltage is inside the recommended limits. All-zero output of the VTUNE monitoring circuits means that VCO VTUNE voltage is properly centered.
  • Page 22 Usually, open-loop methods are more complex but lead to the faster calibration times. LMS8001 provides to the user several options to perform the coarse frequency tuning of the VCO inside the HFPLL_CORE block. Before performing any kind of VCO frequency calibration, the user should carefully program the static registers inside the PLL_CONFIGURATION register bank and PLL_PROFILE_n he/she intends to use.
  • Page 23 Automatic Mode In this mode, internal digital state-machine is enabled and runs the coarse-frequency tuning algorithm based on the binary-search process. The whole process is initiated by setting the sticky-bit FCAL_START to the logic-high value. State-machine clears FCAL_START bit when the VCO frequency calibration is completed. During the VCO calibration, HFPLL feedback loop is broken.
  • Page 24 the final cap bank configuration should be very close to the targeted HFPLL frequency. Binary search, by default, starts from the MSB bit of the cap bank configuration code, VCO_FREQ<7:0>, and determines the final result bit by bit down to LSB. Calibration time per bit of the cap bank code mainly depends on the CTUNE_RES<1:0>...
  • Page 25     AUTO VTUNE WAIT FREQ Basic steps for configuring the LMS8001 IC when running the automatic VCO frequency calibration are presented in Figure 8.7. Figure 8.7: Automatic VCO Frequency Calibration Manual Mode manual calibration mode internal state-machine disabled (PLL_CALIBRATION_EN=0b1, PLL_CALIBRATION_MODE=0b1).
  • Page 26 Logic high value of FREQ_LOW output means that the VCO oscillation frequency is below the targeted value. Using the described circuits and functionality, the user of LMS8001 IC is free to develop custom algorithm for VCO coarse-frequency tuning in the open-loop PLL configuration.
  • Page 27 Figure 8.8: Manual Open-Loop VCO Frequency Calibration Algorithm Example Closed-loop manual VCO calibration In this type of VCO calibration process, PLL core loop is closed. In the case of LMS8001 IC, the HFPLL core loop will be closed when all the blocks inside the loop are powered up, CTUNE_EN and LPFSW_n bits are set to 0b0, and PLL_RSTN is equal to 0b1.

  • Page 28: Ff-Div

    0b01. Optimum VCO capacitor bank code can be taken to be the average of these two values. More complicated algorithms are also possible including the process of selecting the right VCO core. Table 1: VTUNE Comparator Truth Table VTUNE_HIGH VTUNE_LOW STATUS OK, VTUNE is in the recommended range.

  • Page 29: Lo Distribution Network

    Figure 8.10: Feed-Forward Divider Block Diagram 8.5 LO Distribution Network LO Distribution network of the LMS8001 IC is presented in Figure 8.11. It provides four LO outputs for four different RF channels integrated on-chip. Figure 8.11: LO Distribution...

  • Page 30: External Lo

    8.7 HFPLL Configuration 8.7.1 Digital Control Logic Top level structure of the digital control logic implemented in LMS8001 for configuration and control of HFPLL frequency synthesizer is shown in Figure 8.12. There are eight sets (profiles) of PLL control signal values. Profile can be selected with GPIO pins, SPI register value, or a combination, depending on how MUXSEL macro is programmed.
  • Page 31 PLL_FLOCK_INTERNAL=1, when the bit PLL_FLOCK_INTVAL directly controls the fast lock multiplexer. Figure 8.13: Fast lock control logic Figure 8.14: Fast lock timing diagram Table 2: LMS8001 Memory Space for HFPLL Configuration Register Bank Start Address End Address PLL_CONFIGURATION 0x4000...

  • Page 32: Hfpll Fast-Lock Mode

    8.7.2 HFPLL Fast-Lock Mode Overview The LMS8001 IC provides to the user the option to optimize its system and achieve faster frequency settling times. There are eight different PLL_PROFILE registers in the memory space of the device that store sets of the HFPLL programming information. Only one PLL_PROFILE is active at the time and its settings are multiplexed to the HFPLL control inputs.

  • Page 33: Hfpll Frequency Calculation

    8.7.3 HFPLL Frequency Calculation The LC-VCO inside the HFPLL of LMS8001 IC covers frequency range from 4.8 up to 9.6 GHz. Lower frequency bands are synthesized using feed-forward divider stages. Output of the VCO drives the feedback divider or it can be first scaled down in frequency two times as illustrated in Figure 8.10.
  • Page 34   Round   FRAC   PDIV      Frequency step size of the complete LMS8001 frequency synthesizer is given with: PDIV     STEP      DIST  ...

  • Page 35: Register Banks

    Register banks LMS8001 address space is divided into register banks, listed in Table 1. Table 3: LMS8001 Memory Map Register Bank Start Address End Address Comment ChipConfig 0x0000 0x000F BiasLDOConfig 0x0010 0x001F Channel_A 0x1000 0x101F Relevant only for LMS8001A Channel_B...

  • Page 36: Register Bank Chipconfig (0X0000 - 0X001F)

    9.1 Register bank ChipConfig (0x0000 – 0x001F) Register bank ChipConfig contains registers related to chip configuration. 0x0000 SPIConfig (0x001F) Default Bitfield Name Mode Description Driver strength of SPI_SDIO pad. 0 – Driver strength is 4mA (default) SPI_SDIO_DS 1 – Driver strength is 8mA Driver strength of SPI_SDO pad.
  • Page 37 0x0005 GPIOOUT_SEL0 (0x0000) Default Bitfield Name Mode Description GPIO1 source select 000 – from SPI 001 – PLL_LOCK 010 – VTUNE_LOW GPIO1_SEL<2:0> 011 – VTUNE_HIGH 100 – Fast lock active others – reserved GPIO0 source select 000 – from SPI 001 –...

  • Page 38: Register Bank Biasldoconfig (0X0010 - 0X001F)

    0x000A GPIOConfig_DS (0x0000) Default Bitfield Name Mode Description GPIO drive strength 0 – Driver strength is 4mA (default) 000000000 GPIO_DS<8:0> 1 – Driver strength is 8mA 0x000B GPIOConfig_IO (0x03FF) Default Bitfield Name Mode Description GPIO input/output control 0 – Pin is output 111111111 GPIO_InO<8:0>...
  • Page 39 0x0010 BiasConfig (0x1400) Default Bitfield Name Mode Description Enable signal for central bias block 0 – Sub blocks may be selectively powered down PD_BIAS (default) 1 – Powers down all BIAS blocks 0x0011 LOBUFA_LDO_Config (0x0065) Default Bitfield Name Mode Description Enables the load dependent bias to optimize the load EN_LOADIMP_LDO_LOBU regulation...
  • Page 40 0x0014 LOBUFD_LDO_Config (0x0065) Default Bitfield Name Mode Description Enables the load dependent bias to optimize the load regulation EN_LOADIMP_LDO_LOBU 0 – Constant bias (default) 1 – Load dependant bias Short the noise filter resistor to speed up the settling time 0 –...
  • Page 41 0x0017 HFLNAC_LDO_Config (0x0065) Default Bitfield Name Mode Description Controls the output voltage of the LO buffer LDO by setting the resistive voltage divider ratio. 01100101 RDIV_HFLNAC<7:0> Vout = 860 mV + 3.92 mV * RDIV Default : 01100101 (101) Vout = 1.25 V 0x0018 HFLNAD_LDO_Config (0x0065) Default...

  • Page 42: Register Bank Channel_X

    0x001C PLL_CP_LDO_Config (0x0065) Default Bitfield Name Mode Description Enables the load dependent bias to optimize the load regulation EN_LOADIMP_LDO_PLL_ 0 – Constant bias (default) 1 – Load dependant bias Short the noise filter resistor to speed up the settling time 0 –...
  • Page 43 +0x01 CHx_HFPAD_ICT (0x0210) Default Bitfield Name Mode Description Double the linearization bias current 0 – Ilin * 1 (default) CHx_PA_ILIN2X 1 – Ilin * 2 Controls the bias current of linearization section of HFPAD 10000 CHx_PA_ICT_LIN<4:0> I = Inom * CHx_PA_ICT_LIN/16 Default : 16 Controls the bias current of main gm section of HFPAD 10000...
  • Page 44 +0x06 CHx_PD2 (0x00BF) Default Bitfield Name Mode Description Controls the switch in series with 50 Ω resistor to ground at HFPAD input. CHx_PA_R50_EN2 0 – Switch is open 1 – Switch is closed Controls the HFPAD bypass switches. 0 – HFPAD in not bypassed CHx_PA_BYPASS2 1 –...
  • Page 45 +0x08 CHx_LNA_CTRL0 (0x8428) Default Bitfield Name Mode Description Controls the LNA gain 1000 CHx_LNA_GCTRL0<3:0> Gain = Gain_max – CHx_LNA_GCTRL * (approx.) 0.5 dB +0x09 CHx_LNA_CTRL1 (0x8428) Default Bitfield Name Mode Description Controls the bias current of linearization section of LNA 15:11 10000 CHx_LNA_ICT_LIN1<4:0>...
  • Page 46 +0x0D CHx_PA_CTRL1 (0x0000) Default Bitfield Name Mode Description Controls the gain of HFPAD linearizing section 0000 CHx_PA_LIN_LOSS1<3:0> Pout = Pout_max – Loss CHx_PA_MAIN_LOSS1<3: Controls the gain of HFPAD main section 0000 Pout = Pout_max – Loss 0> +0x0E CHx_PA_CTRL2 (0x0000) Default Bitfield Name Mode...
  • Page 47 +0x13 CHx_LNA_SEL1 (0x0800) Default Bitfield Name Mode Description CHx LNA control signals multiplexer SEL0 signal is generated CHx_LNA_SEL1_INTERNA 0 – from GPIO & CHx_LNA_SEL0_MASK, 1 – from CHx_LNA_INT_SEL<0> Invert the SEL1 signal of CHx LNA control signals. 0 – No inversion, CHx_LNA_SEL1_INVERT 1 –...

  • Page 48: Register Bank Hlmixx

    +0x1E CHx_LNA_CTRL_RB Default Bitfield Name Mode Description CHx_LNA_ICT_LIN_RB<4: 15:11 Readback the actual controlling value 0> CHx_LNA_ICT_MAIN_RB< 10:6 Readback the actual controlling value 4:0> CHx_LNA_CGSCTRL_RB< Readback the actual controlling value 1:0> CHx_LNA_GCTRL_RB<3:0 Readback the actual controlling value > +0x1F CHx_PA_CTRL_RB Default Bitfield Name Mode Description...
  • Page 49 +0x1 HLMIXx_CONFIG1 (0x2043) Default Bitfield Name Mode Description HLMIXx LO bias voltage. HLMIXx_VGCAS<6:5> = 00 – Rb = 20 kΩ HLMIXx_VGCAS<6:5> = 01, 10 – Rb = 15 kΩ 13:7 1000000 HLMIXx_VGCAS1<6:0> HLMIXx_VGCAS<6:5> = 11 – Rb = 10 kΩ Ib = Inom * HLMIXx_VGCAS<4:0>/16 Vb = VDD –...
  • Page 50 +0x6 HLMIXx_LOSS2 (0x0000) Default Bitfield Name Mode Description Pout = Pout_max – Loss 0000 HLMIXx_MIXLOSS2<3:0> Reserved +0x7 HLMIXx_LOSS3 (0x0000) Default Bitfield Name Mode Description Pout = Pout_max – Loss 0000 HLMIXx_MIXLOSS3<3:0> Reserved +0x8 HLMIXx_CONF_SEL0 (0x0800) Default Bitfield Name Mode Description HLMIXx bias control signals multiplexer SEL0 signal is HLMIXx_CONF_SEL0_INT generated...

  • Page 51: Register Bank Pll_Configuration (0X4000 - 0X401F)

    +0xC HLMIXx_INT_SEL (0x0000) Default Bitfield Name Mode Description HLMIXx_LOSS_INT_SEL< Internal value of HLMIXx loss control signals multiplexer 1:0> selection signals. HLMIXx_CONF_INT_SEL< Internal value of HLMIXx control signals multiplexer selection 1:0> signals. +0xE HLMIXx_CONFIG_RB Default Bitfield Name Mode Description 13:7 HLMIXx_VGCAS_RB<6:0> Readback the actual controlling value HLMIXx_ICT_BIAS_RB<4: Readback the actual controlling value...
  • Page 52 +0x4001 PLL_CFG_XBUF (0x0000) Default Bitfield Name Mode Description Enables XBUF 0 – Powered down (default) PLL_XBUF_EN 1 – Enabled +0x4002 PLL_CAL_AUTO0 (0x0000) Default Bitfield Name Mode Description Starts the automatic VCO frequency calibration algorithm FCAL_START (sticky-bit). Writing 1 starts the calibration, automatically cleared when calibration is finished.
  • Page 53 +0x4005 PLL_CAL_AUTO3 (0xFA05) Default Bitfield Name Mode Description High-frequency cap-bank configuration used during VCO VCO_SEL_FREQ_MAX<7: 15:8 11111010 auto-select process 0> Default: 11111010 (250) Low-frequency cap-bank configuration used during VCO VCO_SEL_FREQ_MIN<7:0 00000101 auto-select process > Default: 00000101 (5) +0x4006 PLL_CAL_MAN (0x8080) Default Bitfield Name Mode...
  • Page 54 +0x4009 PLL_CFG_SEL1 (0x0800) Default Bitfield Name Mode Description Invert the SEL1 signal of PLL profile multiplexer. 0 – No inversion, PLL_CFG_SEL1_INVERT 1 – Signal is inverted. PLL_CFG_SEL1_MASK<8: 000000000 GPIO mask for SEL1 signal of PLL profile multiplexer. 0> +0x400A PLL_CFG_SEL2 (0x0800) Default Bitfield Name Mode...

  • Page 55: Register Bank Pll_Profile_N

    +0x400E PLL_LODIST_CFG1 (0x0210) Default Bitfield Name Mode Description Controls the input bias current value for LO Distribution PLL_LODIST_ICT_BUF<4: 10000 Network output buffers. 0> Ibias = Inom * PLL_LODIST_ICT_BUF / 16 +0x400F PLL_LODIST_CFG2 (0x00AA) Default Bitfield Name Mode Description Controls the current drive-strength of the LO Distribution PLL_ICT_OUT3<1:0>...
  • Page 56 +0x0 PLL_ENABLE_n (0x0000) Default Bitfield Name Mode Description PLL_LODIST_EN_BIAS_n Enable for LO distribution bias. Enable for IQ generator in LO distribution. PLL_LODIST_EN_DIV2IQ_ 0 – Clock is not divided by 2 1 – Clock is divided by 2, I and Q are generated PLL_EN_VTUNE_COMP_n Enable for tuning voltage comparator in PLL.
  • Page 57 +0x3 PLL_CP_CFG0_n (0x0100) Default Bitfield Name Mode Description Flip for PFD inputs 0 – Normal operation, FLIP_n 1 – Inputs are interchanged 13:12 DEL_n<1:0> Reset path delay Charge pump pulse current 11:6 000100 PULSE_n<5:0> I = 25 µA * PULSE<5:0> Charge pump offset (bleeding) current 000000 OFS_n<5:0>...
  • Page 58 +0x8 PLL_SDM_CFG_n (0x00D8) Default Bitfield Name Mode Description INTMOD_EN_n Integer mode enable Enable dithering in SDM 0 – Disabled DITHER_EN_n 1 – Enabled Selects between the feedback divider output and FREF for SEL_SDMCLK_n 0 – CLK CLK_DIV 1 – CLK CLK_REF Reverses the SDM clock 0 –...
  • Page 59 +0xB PLL_LODIST_CFG_n (0x0000) Default Bitfield Name Mode Description LO distribution channel A frequency, sign and phase control. FSP_OUT<2> - Frequency division control 0 – LO is divided by 2, 1 – LO is not divided. PLL_LODIST_FSP_OUT0_ FSP_OUT<1> - LO sign 0 –...

  • Page 60: Lms8001 Package Drawing

    LMS8001 Package Drawing...

  • Page 61: Lms8001 Pinout

    LMS8001 Pinout...
  • Page 62 Name Description Ground. Connect paddle to good ground with as many as possible vias to ensure proper RF grounding. Not connected EXTLO_P External LO + VDD18_BIAS 1.8 V supply voltage for bias. HFINA_N Channel A RF input - HFINA_HLMIX_P HFINA_P Channel A RF input + HFINA_HLMIX_N Normal bonding: Supply voltage for Channel A LNA.
  • Page 63 Name Description Normal bonding: Supply voltage for Channel D LNA. VDD_HFIND HLMIX bonding: Output of 120 mA LDO. HFIND_P Channel D RF input + HFIND_HLMIX_N HFIND_N Channel D RF input - HFIND_HLMIX_P VDD18_VCO 1.8 V supply for VCO. VDD18_PLL 1.8 V supply for three on-chip PLL LDOs. VDD12_PLL_CP 1.2 V supply for PLL charge pump.

This manual is also suitable for:

Lms8001aLms8001b

Table of Contents