AKM AK4633 Manual

16-bit mono codec with alc & mic/spk-amp

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ASAHI KASEI

The AK4633 is a 16-bit mono CODEC with Microphone-Amplifier and Speaker-Amplifier. Input circuits

include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit. Output circuits include a

Speaker-Amplifier and Mono Line Output. The AK4633 suits a moving picture of Digital Still Camera and

etc. This speaker-Amplifier supports a Piezo Speaker. The AK4633 is housed in a space-saving 24-pin

QFN package.

10. Master / Slave Mode

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16-Bit ∆Σ Mono CODEC with ALC & MIC/SPK-AMP

1. 16-Bit Delta-Sigma Mono CODEC

2. Recording Function

• 1ch Mono Input

• 1

MIC Amplifier: 0dB, 6dB, 10dB, 14dB, 17dB, 20dB, 26dB or 32dB

• 2

Amplifier with ALC: +36dB ∼ -54dB, 0.375dB Step, Mute

• ADC Performance (MIC-Amp= +20dB): S/(N+D): 84dB, DR, S/N: 85dB

• Wind Noise Reduction

• Notch Filter

3. Playback Function

• Digital ALC (Automatic Level Control): +36dB ∼ -54dB, 0.375dB Step, Mute

• Mono Line Output Performance: S/(N+D): 85dB, S/N: 93dB

• Mono Speaker-Amp

- Speaker-Amp Performance: S/(N+D): 60dB (150mW@ 8Ω)

- BTL Output

- Output Power: 400mW @ 8Ω

• Beep Input

4. Power Management

5. Flexible PLL Mode:

• Frequencies:

11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin)

1fs (FCK pin)

16fs, 32fs or 64fs (BICK pin)

6. EXT Mode:

• Frequencies: 256fs, 512fs or 1024fs (MCKI pin)

7. Sampling Rate:

• PLL Slave Mode (FCK pin) : 7.35kHz

• PLL Slave Mode (BICK pin) : 7.35kHz

• PLL Slave Mode (MCKI pin):

8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz

• PLL Master Mode:

8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz

• EXT Slave Mode/EXT Master Mode:

7.35kHz

48kHz (256fs), 7.35kHz

8. Output Master Clock Frequency: 256fs

9. Serial µP Interface: 3-wire

GENERAL DESCRIPTION

FEATURE

Output Noise Level: -87dBV

~ 48

kHz

48kHz

26kHz (512fs), 7.35kHz

- 1 -

[AK4633]

AK4633

13kHz (1024fs)

2006/04

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Summary of Contents for AKM AK4633

Page 1 Microphone-Amplifier and an ALC (Automatic Level Control) circuit. Output circuits include a Speaker-Amplifier and Mono Line Output. The AK4633 suits a moving picture of Digital Still Camera and etc. This speaker-Amplifier supports a Piezo Speaker. The AK4633 is housed in a space-saving 24-pin QFN package.
Page 2: Power Supply
2 Band PMAO AOUT SDTO (ALC) Line Out SDTI PMDAC MCKO PMPLL PMSPK MCKI Speaker VCOC Control Register CCLK PMBP CDTI BEEP/MICN SVDD SVSS Figure 1. AK4633 Block Diagram MS0447-E-03 2006/04 - 2 - Downloaded from Elcodis.com electronic components distributor...
Page 3: Top View
ASAHI KASEI [AK4633] Ordering Guide −40 ∼ +85°C AK4633VN 24pin QFN (0.5mm pitch) AKD4633 Evaluation board for AK4633 Pin Layout SVSS BICK SVDD AK4633VN AOUT SDTO BEEP/MICN Top View SDTI CDTI MIC/MICP CCLK MS0447-E-03 2006/04 - 3 - Downloaded from Elcodis.com...
Page 4 ASAHI KASEI [AK4633] Interchange with AK4631 1. Function Function AK4631 AK4633 2.6V ∼ 3.6V 2.2V ∼ 3.6V AVDD 2.6V ∼ 3.6V 1.6V ∼ 3.6V DVDD 2.6V ∼ 5.25V 2.2V ∼ 4.0V SVDD MIC Input Single-end Single-end / differential MIC Power Output Voltage 0.75 x AVDD...
Page 5 OVOL7 OVOL6 OVOL5 OVOL4 OVOL3 OVOL2 OVOL1 OVOL0 ALC2 Mode Control RFS5 RFS4 RFS3 RFS2 RFS1 RFS0 (2) AK4633 Addr Register Name Power Management 1 PMVCM PMBP PMSPK PMAO PMDAC PMADC PMPFIL Power Management 2 MCKO PMPLL Signal Select 1...
Page 6 ASAHI KASEI [AK4633] 3. Register Setting (1) When PLL reference clock is input from FCK or BICK pin, the setting of FS3-0 bits is changed as shown in the following table. Sampling Frequency Mode FS3 bit FS2 bit FS1 bit...
Page 7: Pin / Function
This pin should be connected to AVSS with one resistor and capacitor in series. Power-Down Mode Pin “H”: Power up, “L”: Power down reset and initialize the control register. AK4633 should always be reset upon power-up. Chip Select Pin CCLK...
Page 8 Note 3. AVSS, DVSS and SVSS must be connected to the same analog ground plane. Note 4. In case that PCB wiring density is 100%. This power is the AK4633 internal dissipation that does not include power of externally connected speaker.
Page 9: Recommended Operating Conditions
AVDD or SVDD is powered up. When the power supplies except DVDD are partially powered OFF, the AK4633 must be reset by bringing PDN pin “L” after these power supplies are powered ON again. If AVDD is powered off when DVDD is powered up, the PMADC bit should be set to “0” before AVDD is powered off.
Page 10 ASAHI KASEI [AK4633] ANALOG CHRACTERISTICS (Ta=25°C; AVDD, DVDD, SVDD=3.3V; AVSS=DVSS=SVSS=0V; fs=8kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 3.4kHz; EXT Slave Mode; unless otherwise specified) Parameter Units MIC Amplifier : MDIF bit = “0”; (Single-ended input) Input Resistance kΩ...
Page 11 PMVCM = PMPLL = MCKO = PMAO = PMBP = PMMP = M/S =“1”. In this case, the output current of MPI pin is 0mA. When the AK4633 is EXT mode (PMPLL = MCKO = M/S = “0”), “AVDD+DVDD” is typically 6mA@fs=8kHz, 9mA@fs=48kHz.
Page 12 ASAHI KASEI [AK4633] FILTER CHRACTERISTICS (Ta = 25°C; AVDD =2.2 ∼ 3.6V, DVDD =1.6 ∼ 3.6V, SVDD =2.2 ∼ 4.0V; fs=8kHz) Parameter Symbol Units ADC Digital Filter (Decimation LPF): ±0.16dB Passband (Note 19) −0.66dB −1.1dB −6.9dB Stopband (Note 19) ±0.1...
Page 13 ASAHI KASEI [AK4633] SWITING CHARACTERISTICS (Ta = 25°C; AVDD =2.2 ∼ 3.6V, DVDD =1.6 ∼ 3.6V, SVDD =2.2 ∼ 4.0V; C =20pF) Parameter Symbol Units PLL Master Mode (PLL Reference Clock = MCKI pin) (Figure 2) MCKI Input: Frequency fCLK 11.2896...
Page 14 ASAHI KASEI [AK4633] Parameter Symbol Units PLL Slave Mode (PLL Reference Clock: FCK pin) (Figure 6,Figure 7) FCK: Frequency fFCK 7.35 DSP Mode: Pulse Width High tFCKH tBCK-60 1/fFCK-tBCK Except DSP Mode: Duty Cycle duty BICK: Period tBCK 1/64fFCK 1/16fFCK...
Page 15 ASAHI KASEI [AK4633] Parameter Symbol Units EXT Slave Mode (Figure 11) MCKI Frequency: 256fs fCLK 1.8816 2.048 12.288 512fs fCLK 3.7632 4.096 13.312 1024fs fCLK 7.5264 8.192 13.312 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK FCK Frequency (MCKI = 256fs) fFCK 7.35...
Page 16 ASAHI KASEI [AK4633] Parameter Symbol Units EXT Master Mode (Figure 2) MCKI Frequency: 256fs fCLK 1.8816 2.048 12.288 512fs fCLK 3.7632 4.096 13.312 1024fs fCLK 7.5264 8.192 13.312 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK FCK Frequency (MCKI = 256fs) fFCK 7.35...
Page 17 1059 1/fs ADRST bit = “1” tPDV 1/fs Note 25. The AK4633 can be reset by the PDN pin = “L”. Note 26. This is the count of FCK “↑“ from the PMADC = “1”. MS0447-E-03 2006/04 - 17 - Downloaded from Elcodis.com...
Page 18 ASAHI KASEI [AK4633] Timing Diagram 1/fCLK MCKI tCLKH tCLKL 1/fFCK 50%DVDD dFCK dFCK 1/fMCK MCKO 50%DVDD tMCKOH tMCKOL dMCK = tMCKOL x fMCK x 100% Figure 2. Clock Timing (PLL/EXT Master mode) (MCKO isn’t available at EXT Master Mode) 50%DVDD...
Page 19 ASAHI KASEI [AK4633] 50%DVDD tBCK tDBF dBCK BICK 50%DVDD (BCKP = "1") BICK 50%DVDD (BCKP = "0") tBSD SDTO 50%DVDD tSDH tSDS SDTI Figure 4. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “1”) 50%DVDD tBFCK dBCK...
Page 20 ASAHI KASEI [AK4633] 1/fFCK tFCKH tBFCK tBCK BICK (BCKP = "0") tBCKH tBCKL BICK (BCKP = "1") Figure 6. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 0) 1/fFCK tFCKH...
Page 21 ASAHI KASEI [AK4633] 1/fCLK MCKI tCLKH tCLKL 1/fFCK tFCKH tFCKL tBCK BICK tBCKH tBCKL 1/fMCK 50%DVDD MCKO tMCKOH tMCKOL dMCK = tMCKOL x fMCK x 100% Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode)
Page 22 ASAHI KASEI [AK4633] tFCKH tFCKB BICK (BCKP = "0") BICK (BCKP = "1") tBSD SDTO 50%DVDD tSDH tSDS SDTI Figure 9. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0) tFCKH tFCKB BICK (BCKP = "1") BICK (BCKP = "0")
Page 23 ASAHI KASEI [AK4633] 1/fCLK MCKI tCLKH tCLKL 1/fFCK tFCKH tFCKL tBCK BICK tBCKH tBCKL Figure 11. Clock Timing (EXT Slave mode) tBFCK tFCKB BICK tFSD tBSD SDTO 50%DVDD tSDS tSDH SDTI Figure 12. Audio Interface Timing (PLL, EXT Slave mode & Except DSP mode)
Page 24 ASAHI KASEI [AK4633] tCSS tCCKL tCCKH CCLK tCCK tCDS tCDH CDTI Figure 13. WRITE Command Input Timing tCSW tCSH CCLK CDTI Figure 14. WRITE Data Input Timing MS0447-E-03 2006/04 - 24 - Downloaded from Elcodis.com electronic components distributor...
Page 25 ASAHI KASEI [AK4633] CCLK tCCZ tDCD CDTI DVDD Figure 15 . Read Data Output Timing PMADC tPDV SDTO 50%DVDD Figure 16. Power Down & Reset Timing 1 Figure 17. Power Down & Reset Timing 2 MS0447-E-03 2006/04 - 25 - Downloaded from Elcodis.com...
Page 26: Operation Overview
ASAHI KASEI [AK4633] OPERATION OVERVIEW System Clock There are the following four clock modes to interface with external devices (Table 1 and Table 2). Mode PMPLL bit M/S bit PLL3-0 bit Figure PLL Master Mode Table 4 Figure 18 PLL Slave Mode 1...
Page 27 AK4633 goes master mode by changing M/S bit = “1”. When the AK4633 is used by master mode, FCK and BICK pins are a floating state until M/S bit becomes “1”. FCK and BICK pins of the AK4633 should be pulled-down or pulled-up by about 100kΩ resistor externally to avoid the floating state.
Page 28 ASAHI KASEI [AK4633] When PLL2 bit is “0”(PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3-2 bits (Table 6). FS3 bit FS2 bit Sampling Frequency Mode FS1 bit FS0 bit Range 7.35kHz ≤ fs ≤ 12kHz Don’t care...
Page 29 ASAHI KASEI [AK4633] PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) When an external clock (11.2896MHz, 12MHz , 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and FCK clocks are generated by an internal PLL circuit. The MCKO output frequency is fixed to 256fs, the output is enabled by MCKO bit.
Page 30 A reference clock of PLL is selected among the input clocks to MCKI, BICK or FCK pin. The required clock to the AK4633 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. When BICK input frequency is 16fs, the audio interface format supports only Mode 0(DSP Mode).
Page 31 EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0” and M/S bit is “0”, the AK4633 becomes EXT slave mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 512fs or 1024fs), BICK (≥32fs) and FCK (fs).
Page 32 MCKI should always be present whenever the ADC or DAC or Programmable Filter is in operation (PMADC bit = “1” or PMDAC bit = “1” or PMPFIL bit = “1”). If MCKI is not provided, the AK4633 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally.
Page 33 MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. FCK and BICK are output from AK4633 in master mode, but must be input to AK4633 in slave mode. In Mode 1-3, the SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge.
Page 34 ASAHI KASEI [AK4633] BICK(32fs) SDTO(o) SDTI(I) 15 14 Don’t Care BICK(64fs) SDTO(o) SDTI(i) Don’t Care Don’t Care 15 14 15:MSB, 0:LSB Data 1/fs Figure 24. Mode 2 Timing BICK(32fs) SDTO(o) SDTI(i) BICK(64fs) SDTO(o) Don’t Care Don’t Care SDTI(i) 15:MSB, 0:LSB...
Page 35 ASAHI KASEI [AK4633] BICK(16fs) SDTO(o) SDTI(i) BICK(32fs) SDTO(o) SDTI(i) Don’t Care Don’t Care 1/fs 1/fs 15:MSB, 0:LSB Figure 26. Mode 0 Timing (BCKP = “0”, MSBS = “0”) BICK(16fs) SDTO(o) SDTI(i) BICK(32fs) SDTO(o) SDTI(i) Don’t Care Don’t Care 1/fs 1/fs 15:MSB, 0:LSB Figure 27.
Page 36 ASAHI KASEI [AK4633] BICK(16fs) SDTO(o) SDTI(i) BICK(32fs) SDTO(o) SDTI(i) Don’t Care Don’t Care 1/fs 1/fs 15:MSB, 0:LSB Figure 28. Mode 0 Timing (BCKP = “0”, MSBS = “1”) BICK(16fs) SDTO(o) SDTI(i) BICK(32fs) SDTO(o) SDTI(i) Don’t Care Don’t Care 1/fs 1/fs 15:MSB, 0:LSB Figure 29.
Page 37: System Reset
[AK4633] System Reset Upon power-up, reset the AK4633 by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The initialization cycle time is selected by ADRST bit (Table 17).
Page 38: Mic Power
ASAHI KASEI [AK4633] MIC Power The MPI pin supplies power for the Microphone. This output voltage scales with 0.8 x AVDD (typ) and the load resistance is minimum 2kΩ. Don’t connect the capacitor directly to MPI pin AK4633 MIC-Power MPI pin ≥...
Page 39: Digital Block
ASAHI KASEI [AK4633] Digital Block Digital Block is composed as Figure 32.The recording and playback single paths are selected by ADCPF bit, PFDAC bit and PFSDO bit (Figure 32~ Figure 35, Table 19) PMADC bit SDTI 1st Order HPFAD bit “1”...
Page 40 ASAHI KASEI [AK4633] Mode ADCPF bit PFDAC bit PFSDO bit Figure Recoding Main Mode Figure 33 Playback Main Mode Figure 34 Loop Back Mode Figure 35 Table 19. Recode/Playback Mode 2nd Order 2 Band (Volume) SMUTE DATT Figure 33. The path at ADCPF bit = “1”, PFDAC bit = “0” and PFSDO bit = “1” (Default)
Page 41 [AK4633] Digital Programmable Filter The AK4633 have 2steps of 1st order HPF and 2 band Equalizer for recording and playback path (Figure 32). (1) High Pass Filter (HPF) Normally, this HPF is used for a Wind-Noise Reduction Filter. This is composed with 2 steps of 1st order HPF. The coefficient of both HPF is same and should be set by F1A13-0 bits and F1B13-0 bits.
Page 42 ASAHI KASEI [AK4633] When the gain of K is set to “-1”, these Equalizers work as notch filter. If the difference between two center frequencies of these notch filters is small, the center frequency will differ from the frequency that is calculated by the above equation.
Page 43 Output Digital Volume2 AK4633 has 4 steps output volume in addition to the volume setting by OVOL7-0 bits. This volume is set by DATT1-0 bits as shown in Table 22.
Page 44: Alc Operation
ASAHI KASEI [AK4633] ALC Operation ALC Operation works in ALC block. When ADCPF bit = “1”, ALC operation is enable for recording path. When ADCPF bit = “0”, ALC operation is enable for playback path. The ON/OFF of ALC operation for recording is controlled by ALC1 bit and the ON/OFF of ALC operation for playback is controlled by ALC2 bit.
Page 45 ASAHI KASEI [AK4633] 2. ALC Recovery Operation The ALC recovery operation waits for the WTM1-0 bits(Table 26) to be set after completing the ALC limiter operation. If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 23) during the wait time, the ALC recovery operation is done.
Page 46 ASAHI KASEI [AK4633] IREF7-0bits GAIN(0dB) Step +36.0 +35.625 +35.25 +19.5 Default 0.375dB +0.375 -0.375 -53.625 -54.0 MUTE Table 28. Reference Level at ALC Recovery operation for recoding OREF5-0bits GAIN(0dB) Step +36.0 +34.5 +33.0 +6.0 Default 1.5dB +1.5 -1.5 -51.0 -52.5 -54.0...
Page 47 ASAHI KASEI [AK4633] 3. The Volume at the ALC Operation The current volume value at the ALC operation is reflected by VOL7-0 bits. It is enable to check the current volume value with reading the register value of VOL7-0 bits.
Page 48 ASAHI KASEI [AK4633] 5. Example of the ALC Operation for Playback Operation Table 33 shows the examples of the ALC setting for playback operation. fs=8kHz fs=16kHz Register Name Comment Data Operation Data Operation −4.1dBFS −4.1dBFS LMTH Limiter detection Level ZELM...
Page 49 ASAHI KASEI [AK4633] The following registers should not be changed during the ALC operation. These bits should be changed after the ALC operation is finished by ALC1 = ALC2 bits =“0” or PMPFIL bit = “0”. • LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, IREF7-0/OREF7-0, ZELM, RFST1-0...
Page 50 ASAHI KASEI [AK4633] SOFTMUTE Soft mute operation is performed in the digital input domain. When the SMUTE bit goes to “1”, the input signal is attenuated by −∞ (“0”) during the cycle of 245/fs (31msec@fs=8kHz). When the SMUTE bit is returned to “0”, the mute is cancelled and the input attenuation gradually changes to 0dB during the cycle of 245/fs (31msec@fs=8kHz).
Page 51 ASAHI KASEI [AK4633] Mono Line Output (AOUT pin) A signal of DAC is output from AOUT pin. When the DACA bit is “0”, this output is OFF. The load resistance is 10kΩ(min). When PMAO bit is “0” and AOPS bit is “0”, the mono line output enters power-down and is pulled down by 100Ω(typ).
Page 52: Speaker Output
Figure 41. Zener diodes should be inserted between speaker and GND as shown in Figure 41, in order to protect SPK-Amp of AK4633 from the power that the piezo speaker outputs when the speaker is pressured. Zener diodes of the following Zener voltage should be used.
Page 53 In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage. Because the SPP and SPN pins rise up at power-save-mode, this mode can reduce pop noise. When the AK4633 is powered-down, pop noise can be also reduced by first entering power-save-mode.
Page 54: Serial Control Interface
ASAHI KASEI [AK4633] Serial Control Interface Internal registers may be written and read by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 2-bit Chip address (2bits, fixed to “10”), Read/Write, Register address (MSB first, 5bits) and Control data (MSB first, 8bits).
Page 55: Register Map
ASAHI KASEI [AK4633] Register Map Addr Register Name Power Management 1 PMPFIL PMVCM PMBP PMSPK PMAO PMDAC PMADC Power Management 2 MCKO PMPLL Signal Select 1 SPPSN BEEPS DACS DACA PMMP MGAIN2 MGAIN0 Signal Select 2 PFSDO AOPS MGAIN1 SPKG1...
Page 56: Register Definitions
ASAHI KASEI [AK4633] Register Definitions Addr Register Name Power Management 1 PMVCM PMBP PMSPK PMAO PMDAC PMADC PMPFIL Default PMADC: ADC Block Power Control 0: Power down (Default) 1: Power up When the PMADC bit changes from “0” to “1”, the initialization cycle (1059/fs=133ms@8kHz when ADRST bit = “0”) starts.
Page 57 ASAHI KASEI [AK4633] Addr Register Name Power Management 2 MCKO PMPLL Default PMPLL: PLL Block Power Control Select 0: PLL is Power down and External is selected. (Default) 1: PLL is Power up and PLL Mode is selected. MCKO: Master Clock Output Enable 0: “L”...
Page 58 ASAHI KASEI [AK4633] Addr Register Name Signal Select 2 PFSDO AOPS SPKG1 SPKG0 BEEPA PFDAC ADCPF MGAIN1 Default ADCPF : Select the input signal to Programmable Filter/ALC 0: SDTI 1: Output from ADC (Default) PFDAC : Select the input signal to DAC...
Page 59 ASAHI KASEI [AK4633] Addr Register Name Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO1 BCKO0 DIF1 DIF0 Default DIF1-0: Audio Interface Format (Table 15) Default: “10” (MSB justified) BCKO1-0: Select BICK output frequency at Master Mode (Table 9) Default: “00” (16fs) PLL3-0: Select input frequency at PLL mode (See Table 4) Default: “0000”...
Page 60 ASAHI KASEI [AK4633] Addr Register Name ALC Mode Control 1 ALC2 ALC1 ZELMN LMAT1 LMAT0 LMTH0 RGAIN0 Default LMTH1-0: ALC Limiter Detection Level / Recovery Waiting Counter Reset Level (Table 23) LMTH1 bit is D6 bit of 0BH. Default: “01”.
Page 61 ASAHI KASEI [AK4633] Addr Register Name ALC Mode Control 3 RGAIN1 LMTH1 OREF5 OREF4 OREF3 OREF2 OREF1 OREF0 Default OREF5-0: Reference value at Playback ALC Recovery Operation. 0.375dB step, 50 Level (Table 29) Default: “28H” (+6.0dB) RGAIN1-0: ALC Recovery Gain Step(Table 27) RGAIN1 bit is D1 bit of 07H.
Page 62 ASAHI KASEI [AK4633] Addr Register Name E1 Co-efficient 0 E1A7 E1A6 E1A5 E1A4 E1A3 E1A2 E1A1 E1A0 E1 Co-efficient 1 E1A15 E1A14 E1A13 E1A12 E1A11 E1A10 E1A9 E1A8 E1 Co-efficient 2 E1B7 E1B6 E1B5 E1B4 E1B3 E1B2 E1B1 E1B0 E1 Co-efficient 3...
Page 63: System Design
ASAHI KASEI [AK4633] SYSTEM DESIGN Figure 45 shows the system connection diagram for the AK4633. An evaluation board [AKD4633] is available which demonstrates the optimum layout, power supply arrangements and measurement results. Single Ended input Analog Supply 2.2∼4.0V 10µ 2.2k 1µ...
Page 64 - All digital input pins should not be left floating. - When the AK4633 is EXT mode (PMPLL bit = “ 0 ” ), a resistor and capacitor of VCOC pin is not needed. - When the AK4633 is PLL mode (PMPLL bit = “ 1 ” ), a resistor and capacitor of VCOC pin is shown in Table 36.
Page 65: Voltage Reference
0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (approx. 0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2πRC). The AK4633 can accept input voltages from AVSS to AVDD.
Page 66: Control Sequence
(5) PLL lock time is 40ms(max) after PMPLL bit changes from “ 0 ” to “ 1 ” and MCKI is supplied from an external source. (6) The AK4633 starts to output the FCK and BICK clocks after the PLL becomes stable. The normal operation of the block which a clock is necessary for becomes possible.
Page 67 (1) After Power Up: PDN pin “ L ” → “ H ” “ L ” time (1) of 150ns or more is needed to reset the AK4633. (2) DIF1-0, FS3-0, PLL3-0, MSBS and BCKP bits should be set during this period.
Page 68 (1) After Power Up: PDN pin “ L ” → “ H ” “ L ” time (1) of 150ns or more is needed to reset the AK4633. (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period.
Page 69 <Example> (1) After Power Up: PDN pin “ L ” → “ H ” “ L ” time (1) of 150ns or more is needed to reset the AK4633. (2) DIF1-0 and FS1-0 bits should be set during this period.
Page 70 ASAHI KASEI [AK4633] MIC Input Recording FS3-0 bits XXXX XXXX (Addr:05H, D5,D2-0) ADRST bit (Addr:05H, D7) MIC Control (Addr:02H, D2-0) ALC1 Control 1 (Addr:06H) ALC1 Control 2 (Addr:08H) IVOL7-0 bits (Addr:09H) ALC1 Control 3 (Addr:07H) Signal Select (Addr:03H) Filter Co-ef XX..X...
Page 71 ASAHI KASEI [AK4633] Example: PLL Master Mode Audio I/F Format:DSP Mode, BCKP=MSBS=“0” Sampling Frequency: 16kHz Pre MIC AMP:+20dB MIC Power On ADC Initialize time : 291/fs ALC1 setting:Refer to Table 32 HPFAD, HPF : ON (fc=150Hz) 2 band EQ : OFF...
Page 72 At first, clocks should be supplied according to “ Clock Set Up ” sequence. (1) Set up a sampling frequency (FS3-0 bit) and ADC initialization cycle. When the AK4633 is PLL mode, Programmable Filter and ADC should be powered-up in consideration of PLL lock time after a sampling frequency is changed.
Page 73 ASAHI KASEI [AK4633] Speaker-amp Output FS3-0 bits XXXX XXXX (Addr:05H, D5,D2-0) (13) DACS bit (Addr:02H, D3) ALC2 Control 1 (Addr:06H) ALC2 Control 2 (Addr:10H) OVOL7-0 bits (Addr:0AH) ALC2 Control 3 (Addr:07H) Signal Select XXXXXXXX 000XX010 (Addr:03H) Filter Co-ef XX..X XX..X...
Page 74 ASAHI KASEI [AK4633] Example: PLL Master Mode Audio I/F Format:DSP Mode, BCKP=MSBS=“0” Sampling Frequency: 16kHz SPKG1-0 bits = “01” ALC2 : ON ALC2 setting:Refer to Table 33 HPF : ON (fc=150Hz) 2 band EQ : OFF (1) Addr:05H, Data:02H (2) Addr:02H, Data:20H...
Page 75 At first, clocks should be supplied according to “ Clock Set Up ” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4633 is PLL mode, DAC and Speaker-Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed.
Page 76 ASAHI KASEI [AK4633] BEEP signal output from Speaker-Amp Example: Clocks can be stopped. CLOCK (1) Addr:00H, Data:70H PMBP bit (Addr:00H, D2) (2) Addr:02H, Data:40H PMSPK bit (Addr:00H, D4) (3) Addr:02H, Data:C0H BEEPS bit BEEP Signal Output (Addr:02H, D6) SPPSN bit...
Page 77 ASAHI KASEI [AK4633] MONO LINEOUT Example: PLL, Master Mode Audio I/F Format :DSP Mode, BCKP=MSBS= “0” Sampling Frequency: 16kHz Digital Volume: 0dB FS3-0 bits XXXX XXXX (Addr:05H, D5, D2-0) (1) Addr:05H, Data:02H (11) DACA bit (Addr:02H, D4) (2) Addr:02H, Data:10H...
Page 78 ASAHI KASEI [AK4633] Stop of Clock Master clock can be stopped when ADC, DAC and programmable filter don’t operate. 1. PLL Master Mode Example: Audio I/F Format: DSP Mode, BCKP = MSBS = “0” BICK frequency at Master Mode : 64fs Input Master Clock Select at PLL Mode : 11.2896MHz...
Page 79: Power Down
If the clocks are supplied, power down VCOM (PMVCM bit: “ 1 ” → “ 0 ” ) after all blocks except for VCOM are powered-down and a master clock stops. The AK4633 is also powered-down by PDN pin = “ L ” . When PDN pin = “ L ” , the registers are initialized.
Page 80 ASAHI KASEI [AK4633] Package 24pin QFN (Unit: mm) 4.0 ± 0.1 2.4 ± 0.15 Exposed 0.40 ± 0.1 PIN #1 ID 0.23 ± 0.05 0.10 (0.35 x 45 ) 0.08 Note) The exposed pad on the bottom surface of the package must be open or connected to GND.
Page 81 ASAHI KASEI [AK4633] MARKING 4633 XXXX XXXX: Date code (4 digit) Pin #1 indication Revision History Date (YY/MM/DD) Revision Reason Page Contents 05/12/26 First Edition 06/04/28 Error Correct Table 19 : PDSDO bit → PFSDO bit Error Correct 2 Band Equalizer : The Coefficient of C is corrected.
Page 82 AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

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Ak4631