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5
D
7
MCH_CFG_5
R1106
2.2KOhm
r0402
@
GND
CFG7 : CPU STRAP
7
MCH_CFG_7
LOW = Mobile Prescott
HIGH = Dothan CPU (Default)
R1103
2.2KOhm
r0402
@
C
GND
7
MCH_CFG_11
R1108
2.2KOhm
r0402
@
GND
7
MCH_CFG_9
B
R1105
2.2KOhm
r0402
GND
7
MCH_CFG_10
R1104
2.2KOhm
r0402
@
GND
A
5
4
7
MCH_CFG_12
CFG5 : DMI STRAP
LOW = DMI X 2
HIGH = DMI X 4 (Default)
CFG11 : PSB 4X CLK ENABLE
LOW = REVERSAL
HIGH =Calistoga(Default)
CFG9 : PCIE GRAPHIC LANE
LOW = REVERSE LANE (Default)
HIGH = NORMAL OPERATION
CFG10: HOST PLL VCO SELECT
LOW = RESERVED
HIGH = MOBILITY
4
3
7
MCH_CFG_13
R1110
2.2KOhm
R1111
r0402
2.2KOhm
@
r0402
@
GND
GND
CFG15 :ICH RESET DISABLE
7
MCH_CFG_15
LOW = ICH RESET DISABLE
HIGH = NORMAL OPERATION
R1109
1KOhm
@
GND
CFG16 : FSB DYNAMIC ODT
7
MCH_CFG_16
LOW = Dynamic ODT Disabled
HIGH = Dynamic ODT Enabled (Default)
R1107
2.2KOhm
r0402
@
GND
CFG18 : GMCH Core Voltage Level
+3VS
LOW = 1.05V (Default)
HIGH = 1.5V
R1102
1KOhm
@
7
MCH_CFG_18
CFG19 : DMI LANE REVERSAL
+3VS
LOW = NORMAL
HIGH = LANES REVERSED
R1101
1KOhm
@
7
MCH_CFG_19
3
2
CFG[17..3] have internal pullup resistors.
CFG[20..18] have internal pulldown resistors.
SDVOCRTL_DATA has internal pulldown
resistors.
<Variant Name>
Title :
Engineer:
ASUSTeK COMPUTER INC
Size
Project Name
A6J
Custom
Date:
Tuesday, November 22, 2005
2
1
D
C
B
A
Calistoga Strapping
Charles Lee
Rev
2.0
Sheet
11
of
63
1
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