LG 22MT57V Service Manual page 26

+1.5V_DDR +1.5V_DDR
A-MVREFDQ A-MVREFCA
CLose to Saturn7M IC
CLose to DDR3
DDR_1600_1G_SS(NEW)
IC1201
K4B1G1646G-BCMA
EAN63370001
M8
A-MVREFCA
VREFCA A0
A1
A2
H1
A-MVREFDQ VREFDQ A3
DDR_EXT A4
R1203 A5
L8
ZQ A6
240
+1.5V_DDR A7
1%
A8
B2
VDD_1 A9
10V D9
DDR_EXT C1205 10uF
VDD_2 A10/AP
G7
C1207 0.1uF
DDR_EXT
VDD_3 A11
K2
DDR_EXT C1208 0.1uF
VDD_4 A12/BC
K8
C1210 0.1uF
DDR_EXT
VDD_5 A13
N1
DDR_EXT C1211 0.1uF
VDD_6
N9
DDR_EXT C1212 0.1uF
VDD_7 NC_5
R1
DDR_EXT C1213 0.1uF
VDD_8
R9
C1214 0.1uF
DDR_EXT VDD_9 BA0
C1215 0.1uF
DDR_EXT BA1
DDR_EXT C1216 0.1uF
BA2
A1
VDDQ_1
A8
VDDQ_2 CK
C1
VDDQ_3 CK
C9
VDDQ_4 CKE
D2
VDDQ_5
E9
VDDQ_6 CS
F1
VDDQ_7 ODT
H2
VDDQ_8 RAS
H9
VDDQ_9 CAS
WE
J1
NC_1
J9
NC_2 RESET
L1
NC_3
L9
NC_4
T7
A-MA14 NC_6 DQSL
DQSL
A9
VSS_1 DQSU
B3
VSS_2 DQSU
E1
VSS_3
G8
VSS_4 DML
J2
VSS_5 DMU
J8
VSS_6
M1
DQL0
VSS_7
M9
VSS_8 DQL1
P1
VSS_9 DQL2
P9
VSS_10 DQL3
T1
VSS_11 DQL4
T9
VSS_12 DQL5
DQL6
DQL7
B1
VSSQ_1
B9
VSSQ_2 DQU0
D1
VSSQ_3 DQU1
D8
VSSQ_4 DQU2
E2
VSSQ_5 DQU3
E8
DQU4
VSSQ_6
F9
VSSQ_7 DQU5
G1
VSSQ_8 DQU6
G9
VSSQ_9 DQU7
DDR_1600_1G_HYNIX
IC1201-*1
H5TQ1G63EFR-PBC
EAN61829003
N3 M8
A0 VREFCA
P7
A1
P3
A2
N2 H1
A3 VREFDQ
P8
A4
P2
A5
R8 L8
A6 ZQ
R2
A7
T8
A8
R3 B2
A9 VDD_1
L7 D9
A10/AP VDD_2
R7 G7
N7 A11 VDD_3 K2
A12/BC VDD_4
T3 K8
NC_7 VDD_5
N1
VDD_6
M7 N9
NC_5 VDD_7
R1
VDD_8
M2 R9
BA0 VDD_9
N8
BA1
M3
BA2
A1
VDDQ_1
J7 A8
CK VDDQ_2
K7 C1
CK VDDQ_3
K9 C9
CKE VDDQ_4
D2
L2 VDDQ_5 E9
CS VDDQ_6
K1 F1
ODT VDDQ_7
J3 H2
RAS VDDQ_8
K3 H9
CAS VDDQ_9
L3
WE
J1
NC_1
T2 J9
RESET NC_2
L1
NC_3
L9
NC_4
F3 T7
DQSL NC_6
G3
DQSL
C7 A9
B7 DQSU VSS_1 B3
DQSU VSS_2
E1
VSS_3
E7 G8
DML VSS_4
D3 J2
DMU VSS_5
J8
VSS_6
E3 M1
DQL0 VSS_7
F7 M9
DQL1 VSS_8
F2 P1
DQL2 VSS_9
F8 P9
DQL3 VSS_10
H3 T1
DQL4 VSS_11
H8 T9
DQL5 VSS_12
G2
DQL6
H7
DQL7 B1
VSSQ_1
D7 B9
DQU0 VSSQ_2
C3 D1
DQU1 VSSQ_3
C8 D8
DQU2 VSSQ_4
C2 E2
DQU3 VSSQ_5
A7 E8
DQU4 VSSQ_6
A2 F9
DQU5 VSSQ_7
B8 G1
DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2015 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE2133(128M)
N3
A-MA0
P7
A-MA1 E11
P3 A-MA0 B_DDR3_A[0]
A-MA2 F12
N2 A-MA1
B_DDR3_A[1]
A-MA3 D10
P8 A-MA2 B_DDR3_A[2]
A-MA4 B10
P2 A-MA3
B_DDR3_A[3]
A-MA5 E15
R8 A-MA4 B_DDR3_A[4]
A-MA6 B11
R2 A-MA5
B_DDR3_A[5]
A-MA7 F14
T8 A-MA6 B_DDR3_A[6]
A-MA8 C11
R3 A-MA7
B_DDR3_A[7]
A-MA9 D14
L7 A-MA8 B_DDR3_A[8]
A-MA10 A12
R7 A-MA9
B_DDR3_A[9]
A-MA11 F16
N7 A-MA10 B_DDR3_A[10]
A-MA12 D13
T3 A-MA11 B_DDR3_A[11]
A-MA13 D15
A-MA12 B_DDR3_A[12]
C12
M7 A-MA13 B_DDR3_A[13]
E13
A-MA14
B_DDR3_A[14]
M2
A-MBA0 A-MCK A9
N8 A-MBA0
B_DDR3_BA[0]
A-MBA1 D16
M3 A-MBA1 B_DDR3_BA[1]
DDR_EXT
A-MBA2 A10
C1209 A-MBA2
B_DDR3_BA[2]
J7
0.01uF C13
K7 50V A-MCK
B_DDR3_MCLK
B13
K9 A-MCKB B_DDR3_MCLKZ
A-MCKE E17
A-MCKE
B_DDR3_MCLKE
A-MCKB
L2
A/B_DDR3_CS B8
K1 A-MODT B_DDR3_ODT
A-MODT C8
J3 A-MRASB B_DDR3_RASZ
A-MRASB +1.5V_DDR B9
K3 A-MCASB B_DDR3_CASZ
A-MCASB D11
R1231
L3 A-MWEB
B_DDR3_WEZ
10K
A-MWEB
F10
DDR_EXT
T2 A-MRESETB
B_RESET
A-MRESETB
D12
A/B_DDR3_CS
B_DDR3_CS0
F3
A-MDQSL A19
G3
B_DDR3_DQSL
A-MDQSLB B18
B_DDR3_DQSU
C7
A-MDQSU C16
B7 A-MDML B_DDR3_DQML
A-MDQSUB D21
A-MDMU B_DDR3_DQMU
E7
A-MDML C18
D3 B_DDR3_DQSBL
A-MDMU C17
B_DDR3_DQSBU
E3
A-MDQL0 A20
F7 A-MDQL0
B_DDR3_DQL[0]
A-MDQL1 A16
F2 A-MDQL1 B_DDR3_DQL[1]
A-MDQL2 C19
F8 A-MDQL2
B_DDR3_DQL[2]
A-MDQL3 C15
H3 A-MDQL3 B_DDR3_DQL[3]
A-MDQL4 C20
H8 A-MDQL4
B_DDR3_DQL[4]
A-MDQL5 C14
G2 A-MDQL5 B_DDR3_DQL[5]
A-MDQL6 B21
H7 A-MDQL6
B_DDR3_DQL[6]
A-MDQL7 B15
A-MDQL7 B_DDR3_DQL[7]
F18
D7 A-MDQU0 B_DDR3_DQU[0]
A-MDQU0 D19
C3 A-MDQU1 B_DDR3_DQU[1]
A-MDQU1 D17
C8 A-MDQU2 B_DDR3_DQU[2]
A-MDQU2 E21
C2 A-MDQU3
B_DDR3_DQU[3]
A-MDQU3 E19
A7 A-MDQU4 B_DDR3_DQU[4]
A-MDQU4 D20
A2 A-MDQU5
B_DDR3_DQU[5]
A-MDQU5 D18
B8 A-MDQU6 B_DDR3_DQU[6]
A-MDQU6 F20
A3 A-MDQU7
B_DDR3_DQU[7]
A-MDQU7
R1237
E9
ZQ
240
1%
DDR_1600_1G_NANYA(NEW)
IC1201-*2
NT5CB64M16FP-EK
EAN63511401
N3 M8
A0 VREFCA
P7
A1
P3
A2
N2 H1
A3 VREFDQ
P8
A4
P2
A5
R8 L8
A6 ZQ
R2
A7
T8
A8
R3 B2
A9 VDD_1
L7 D9
A10/AP VDD_2
R7 G7
N7 A11 VDD_3 K2
A12/BC VDD_4
T3 K8
NC_6 VDD_5
N1
VDD_6
M7 N9
NC_5 VDD_7
R1
VDD_8
M2 R9
BA0 VDD_9
N8
BA1
M3
BA2
A1
VDDQ_1
J7 A8
CK VDDQ_2
K7 C1
CK VDDQ_3
K9 C9
CKE VDDQ_4
D2
L2 VDDQ_5 E9
CS VDDQ_6
K1 F1
ODT VDDQ_7
J3 H2
RAS VDDQ_8
K3 H9
CAS VDDQ_9
L3
WE
J1
NC_1
T2 J9
RESET NC_2
L1
NC_3
L9
NC_4
F3 T7
DQSL NC_7
G3
DQSL
C7 A9
B7 DQSU VSS_1 B3
DQSU VSS_2
E1
VSS_3
E7 G8
DML VSS_4
D3 J2
DMU VSS_5
J8
VSS_6
E3 M1
DQL0 VSS_7
F7 M9
DQL1 VSS_8
F2 P1
DQL2 VSS_9
F8 P9
DQL3 VSS_10
H3 T1
DQL4 VSS_11
H8 T9
DQL5 VSS_12
G2
DQL6
H7
DQL7 B1
VSSQ_1
D7 B9
DQU0 VSSQ_2
C3 D1
DQU1 VSSQ_3
C8 D8
DQU2 VSSQ_4
C2 E2
DQU3 VSSQ_5
A7 E8
DQU4 VSSQ_6
A2 F9
DQU5 VSSQ_7
B8 G1
DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9
+1.5V_DDR
+1.5V_DDR
256SCALER
128SCALER
IC101
IC101-*1
LGE2134(256M)
E11
B_DDR3_A[0]
F12
B_DDR3_A[1]
D10
B_DDR3_A[2]
B10
B_DDR3_A[3]
E15
B_DDR3_A[4]
B11
B_DDR3_A[5]
F14
B_DDR3_A[6]
C11
B_DDR3_A[7]
D14
B_DDR3_A[8]
A12
B_DDR3_A[9]
F16
B_DDR3_A[10]
D13
B_DDR3_A[11]
D15
B_DDR3_A[12]
C12
B_DDR3_A[13]
E13
B_DDR3_A[14]
A9
B_DDR3_BA[0]
D16
B_DDR3_BA[1]
A10
B_DDR3_BA[2]
C13
B_DDR3_MCLK
B13
B_DDR3_MCLKZ
E17
B_DDR3_MCLKE
B8
B_DDR3_ODT
C8
B_DDR3_RASZ
B9
B_DDR3_CASZ
D11
B_DDR3_WEZ
F10
B_RESET
D12
B_DDR3_CS0
A19
B_DDR3_DQSL
B18
B_DDR3_DQSU
C16
B_DDR3_DQML
D21
B_DDR3_DQMU
C18
B_DDR3_DQSBL
C17
B_DDR3_DQSBU
A20
B_DDR3_DQL[0]
A16
B_DDR3_DQL[1]
C19
B_DDR3_DQL[2]
C15
B_DDR3_DQL[3]
C20
B_DDR3_DQL[4]
C14
B_DDR3_DQL[5]
B21
B_DDR3_DQL[6]
B15
B_DDR3_DQL[7]
F18
B_DDR3_DQU[0]
D19
B_DDR3_DQU[1]
D17
B_DDR3_DQU[2]
E21
B_DDR3_DQU[3]
E19
B_DDR3_DQU[4]
D20
B_DDR3_DQU[5]
D18
B_DDR3_DQU[6]
F20
B_DDR3_DQU[7]
E9
ZQ
LCD_TV_SCALER_128M
LCD_TV_SCALER_256M
IC101-*3
IC101-*2
LGE2132(M1A_256M)
LGE2131(M1A_128M)
E11
E11
B_DDR3_A[0]
B_DDR3_A[0]
F12
F12
B_DDR3_A[1]
B_DDR3_A[1]
D10
D10
B_DDR3_A[2]
B_DDR3_A[2]
B10
B10
B_DDR3_A[3]
B_DDR3_A[3]
E15
E15
B_DDR3_A[4]
B_DDR3_A[4] B11
B11
B_DDR3_A[5]
B_DDR3_A[5]
F14
F14
B_DDR3_A[6]
B_DDR3_A[6] C11
C11
B_DDR3_A[7]
B_DDR3_A[7]
D14
D14
B_DDR3_A[8]
B_DDR3_A[8] A12
A12
B_DDR3_A[9]
B_DDR3_A[9]
F16
F16
B_DDR3_A[10]
B_DDR3_A[10]
D13
D13
B_DDR3_A[11]
B_DDR3_A[11]
D15
D15
B_DDR3_A[12]
B_DDR3_A[12]
C12
C12
B_DDR3_A[13]
B_DDR3_A[13]
E13
E13
B_DDR3_A[14]
B_DDR3_A[14]
A9
A9
B_DDR3_BA[0]
B_DDR3_BA[0]
D16
D16
B_DDR3_BA[1]
B_DDR3_BA[1] A10
A10
B_DDR3_BA[2]
B_DDR3_BA[2]
C13
C13
B_DDR3_MCLK
B_DDR3_MCLK
B13
B13
B_DDR3_MCLKZ
B_DDR3_MCLKZ E17
E17
B_DDR3_MCLKE
B_DDR3_MCLKE
B8
B8
B_DDR3_ODT
B_DDR3_ODT
C8
C8
B_DDR3_RASZ
B_DDR3_RASZ
B9
B9
B_DDR3_CASZ
B_DDR3_CASZ
D11
D11
B_DDR3_WEZ
B_DDR3_WEZ
F10
F10
B_RESET
B_RESET
D12
D12
B_DDR3_CS0
B_DDR3_CS0
A19
A19
B_DDR3_DQSL
B_DDR3_DQSL
B18
B18
B_DDR3_DQSU
B_DDR3_DQSU
C16
C16
B_DDR3_DQML
B_DDR3_DQML
D21
D21
B_DDR3_DQMU
B_DDR3_DQMU
C18
C18
B_DDR3_DQSBL
B_DDR3_DQSBL
C17
C17
B_DDR3_DQSBU
B_DDR3_DQSBU
A20
A20
B_DDR3_DQL[0]
B_DDR3_DQL[0]
A16
A16
B_DDR3_DQL[1]
B_DDR3_DQL[1] C19
C19
B_DDR3_DQL[2]
B_DDR3_DQL[2]
C15
C15
B_DDR3_DQL[3]
B_DDR3_DQL[3] C20
C20
B_DDR3_DQL[4]
B_DDR3_DQL[4]
C14
C14
B_DDR3_DQL[5]
B_DDR3_DQL[5] B21
B21
B_DDR3_DQL[6]
B_DDR3_DQL[6]
B15
B15
B_DDR3_DQL[7]
B_DDR3_DQL[7]
F18
F18
B_DDR3_DQU[0]
B_DDR3_DQU[0]
D19
D19
B_DDR3_DQU[1]
B_DDR3_DQU[1]
D17
D17
B_DDR3_DQU[2]
B_DDR3_DQU[2]
E21
E21
B_DDR3_DQU[3]
B_DDR3_DQU[3]
E19
E19
B_DDR3_DQU[4]
B_DDR3_DQU[4]
D20
D20
B_DDR3_DQU[5]
B_DDR3_DQU[5]
D18
D18
B_DDR3_DQU[6]
B_DDR3_DQU[6] F20
F20
B_DDR3_DQU[7]
B_DDR3_DQU[7]
E9
E9
ZQ
ZQ
MA55
M1_DDR (2DDR)
2013/05/23
12
LGE Internal Use Only