1. Manuals
  2. Brands
  3. Synopsys Manuals
  4. Computer Accessories
  5. Identify
  6. User manual

Synopsys Identify User Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Identify Debugger
User Guide
March 2015
https://solvnet.synopsys.com

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Identify and is the answer not in the manual?

Questions and answers

Summary of Contents for Synopsys Identify

  • Page 1 Identify Debugger User Guide March 2015 https://solvnet.synopsys.com...
  • Page 2 Synopsys, Inc., or as expressly provided by the license agreement. Right to Copy Documentation The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any.
  • Page 3 Preface Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Registered Trademarks (®)
  • Page 4 Preface Service Marks (sm) MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc. SystemC is a trademark of the Open SystemC Initiative and is used under license. ARM and AMBA are registered trademarks of ARM Limited. Saber is a registered trademark of SabreMark Limited Partnership and is used under license.

  • Page 5: Table Of Contents

    Simultaneous Debugging ..........45 Identify Debugger User Guide ©...
  • Page 6 Disabling the Counter ..........87 © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 7 Using the Synopsys Debug Port ........
  • Page 8 Contents © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 9 Machine, on page 44 • Simultaneous Debugging, on page 45 • Debugger-Analyst Integration, on page 46 • Waveform Display, on page 51 • Logic Analyzer Interface Parameters, on page 54 Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 10: Chapter 1: Using The Debugger

    Adjust the port setting based on the port where the communication cable is connected. Most often, lpt1 is the correct setting for parallel ports. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 11: Reviewing The Jtag Chain Settings

    2-device chain that has JTAG identification register lengths of 8 and 10 bits. In addition, the device named “fpga” has been enabled for debugging. “fpga” device enabled for debugging Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 12: Saving The Debugged Design

    Invocation, on page 13 Synthesis Tool Launch If you are using a Synopsys FPGA synthesis tool or the Certify tool, invoke the debugger directly from the graphical user interface as follows: • From Synplify Pro or Synplify Premier, highlight the Identify implemen- tation and select Run->Launch Identify Debugger from the menu bar or...

  • Page 13: Debugger Windows

    The debugger runs on both the Windows and Linux platforms. To explicitly invoke the debugger from a Windows system, either: • double click the Identify Debugger icon on the desktop • run identify_debugger.exe from the /bin directory of the installation path To explicitly invoke the debugger from a Linux system: •...

  • Page 14: Iice Instrumentation Window

    The instrumentation window in the debugger, like the instrumentation window in the instrumentor, includes a hierarchy browser on the left and the source code display on the right. Source-Code Display Hierarchy Browser © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 15 (or “P”) icons next to them. Breakpoints that can be activated have small green circular icons in the left margin to the left of the line number. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 16: Console Window

    The debugger console window displays commands that have been executed, including those executed by menu selections and button clicks. The console window also allows you to enter debugger commands and to view the results of command execution. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 17: Project Window

    The project window displays the symbolic view of the project on the left and a Run button with a list of all of the available IICE units that can be debugged on the right. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 18: Commands And Procedures

    The debugger commands to open and save projects are available as menu items and icons. Function Menu Bar Menu Command Icon Open existing project File->Open project Save current File->Save activations activations When opening a project: © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 19: Executing A Script File

    Set Trigger Expressions menu item to bring up the Watchpoint Setup dialog box. There are two forms of watchpoints: value and transition. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 20 In the example below, the transition being defined is a transition from “0010” to “1011.” © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 21 To deactivate a partial-bus watchpoint, click-and-hold on the signal or the associated “P” icon and select the bus segment from the list of segments displayed. The watchpoint popup menu appears. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 22 Active breakpoint (red) Inactive breakpoint (green) To deactivate an active breakpoint, click on the breakpoint icon to toggle it from red to green. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 23: Selecting Multiplexed Instrumentation Sets

    3. The signals group command can be used to assign groups from the console window (see signals, on page 78 of the Reference Manual). Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 24: Activating/Deactivating Folded Instrumentation

    /rtl/cnt_inst0/val /rtl/cnt_inst1/val Either of these instances is activated/deactivated by clicking on the appro- priate line in the list box to bring up the watchpoint menu shown in the following figure. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 25 To activate/deactivate instances of the breakpoint on line 24, select the icon next to line number 24. A list will pop up with the two instrumented instances of the breakpoint available for activation/deactivation: /rtl/inst0/rtl/process_18/if_20/if_23/repeated_unit.vhd:24 /rtl/inst1/rtl/process_18/if_20/if_23/repeated_unit.vhd:24 Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 26: Run Command

    The Run command sends watchpoint and breakpoint activations to the IICE, waits for the trigger to occur, receives data back from the IICE when the trigger occurs, and then displays the data in the source window. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 27 The small green arrow next to the activated breakpoint in the example indicates that this breakpoint was the actual breakpoint that triggered. Note that the green arrow is only present with simple triggering. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 28: Sampled Data Compression

    When enabled, data compression is applied to the sampled data to temporarily remove any data that remains unchanged between cycles (a sample is automatically taken after 64 unchanging cycles). © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 29: Sample Buffer Trigger Position

    Currently, the debugger supports the following trigger positions relative to the sample buffer: • Early • Middle Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 30 To set the trigger position to “late,” use the Debug->Trigger Position->late menu selection or click on the Set trigger position to late in the sample buffer icon. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 31: Sampled Data Display Controls

    To change the radix of a sampled signal: 1. Right click on the signal name or the watchpoint or “P” icon and select Change signal radix to display the following dialog box. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 32 If your design contains entities or modules that are instantiated more than once, it is termed to have a “folded” hierarchy (folded hierarchies also occur when multiple instances are created within a generate loop). By definition, © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 33 Instrumentor User Guide and Activating/Deactivating Folded Instrumentation, on page Displaying Data for Partial Buses When debugging designs with partially instrumented buses, the debugger displays the data values of each of the instrumented segments. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 34 (the value for each instrumented field is listed in field order, and an uninstrumented field value is shown as a U). © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 35: Saving And Loading Activations

    Selecting an existing activation from the drop-down menu overwrites the selected activation. 5. To include the sample data set with the activation, enable the Save current sample data check box. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 36: Cross Triggering

    Cross Triggering Cross triggering allows the trigger from one IICE unit to be used to qualify a trigger on another IICE unit, even when the two IICE units are in different © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 37 IICE unit has occurred (external IICE iiceName units are individually listed) after all Event trigger from local IICE unit occurs after all events occur at all IICE units Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 38: Listing Watchpoints And Signals

    To list categories of watchpoints and signals in the debugger, use the popup Debug menu selection and select the category from the list displayed. The results are displayed in the Find Design Elements dialog box. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 39 Show Disabled Watchpoints To display the disabled (inactive) watchpoints, click the Show disabled watchpoints icon. Show Enabled Watchpoints To display the enabled (active) watchpoints, click the Show enabled watchpoints icon. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 40: Haps Deep Trace Debug

    (8GB dual rank) 1 to 250 140 MHz 134,217,727 268,435,455 251 to 506 70 MHz 67,108,863 134,217,727 507 to 1018 35 MHz 33,554,431 67,108,863 1019 to 2042 17.5 MHz 16,777,215 33,554,431 © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 41: Viewing Captured Deep Trace Debug Samples

    2. In the debugger GUI, open the design definition file (debug.prj). 3. Click the Waveform Display icon. If the sample depth is set to more than 8000000, the tool displays a popup window. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 42: Hardware Configuration Verification

    A self-test is available for verifying the deep trace debug hardware configura- tion. The self-test writes data patterns to the external memory and reads back the data pattern written to detect configuration errors, connectivity problems, and SRAM frequency mismatches. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 43 Selecting 0 uses one test pattern, and selecting 1 uses another pattern. To ensure adequate testing, repeat the command using alternate pattern settings. The self-test can also be run from the command line using the following syntax: iice sampler -runselftest 1|0 Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 44: Debugging On A Different Machine

    Simply call this command from the command line before loading the project file (projectName.prj). The argument is a semi-colon-separated (Windows) or colon-separated (Linux) list of direc- tories in which to find the original source files. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 45: Simultaneous Debugging

    This capability is based on semaphores that allow more than one debugger to share the common port. Debugger 1 pid1 Semaphore PID1 Cable Board Debugger 2 pid2 PID2 FPGA2 FPGA1 Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 46: Debugger-Analyst Integration

    VCD control panel under the RTL view. 3. Click the Open a VCD File icon ( ) or select VCD->Load VCD File from the HDL-Analyst menu to open the Load Identify VCD File dialog box. © 2015 Synopsys, Inc. Identify Debugger User Guide...
  • Page 47 4. In the dialog box, enter the path to the vcd file generated by the debugger (use the browse ... button) and make sure that the Identify Debug box is checked. The Validate VCD File with Netlist check box, when enabled, checks for mismatches between the design netlist and the VCD file loaded.
  • Page 48 Chapter 1: Using the Debugger Debugger-Analyst Integration 7. Close the Load Identify VCD File dialog box. 8. To view values for the signals, select the desired signals in the waveform viewer and select HDL-Analyst->VCD->VCD Properties. On the Parameters tab, enable the Annotate check box.
  • Page 49 • To unload a VCD file, select Unload the VCD File. This option frees up memory used by the debug data without having to close and re-open the HDL Analyst view. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 50 The following additional functions are available from the VCD control panel: • Observing nets on a particular HDL Analyst sheet • Changing the format of signals displayed in the viewer These functions are described in detail in the Synopsys FPGA Synthesis User Guide. © 2015 Synopsys, Inc.

  • Page 51: Waveform Display

    Selecting Options->Debugger preferences from the menu bar brings up the dialog box shown below. The Synopsys DVE waveform viewer is only available on Linux platforms. To use the included GTKWave viewer, click the GTKWave radio button in the Default Waveform Viewer section.
  • Page 52 $PATH environment variable. To invoke the viewer after running the debugger, select Window->Waveform or click on the Open Waveform Display icon. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 53: Generating The Fast Signal Database

    2. Run the instrumented design in the synthesis tool and load the project into the debugger. 3. Use the Debugger Preferences dialog box and make sure that Synopsys Verdi nWave is selected as the default waveform viewer. 4. Setup the trigger conditions and click the Run button to download the sample buffer.

  • Page 54: Logic Analyzer Interface Parameters

    The Logic Analyzer Scan tab defines: • the logic analyzer type • the TLA script program • user name • host name/IP address • if pods are automatically assigned to Mictor connectors © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 55 Clicking the Scan Logic Analyzer button scans the specified IP address and, if scanned successfully: • opens a network connection with the given parameters • retrieves the modules and pods information • displays Logic Analyzer Properties and Logic Analyzer Submit tabs Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 56: Logic Analyzer Properties Tab

    Clicking the Assign Pods button updates the assignments. Logic Analyzer Submit Tab The Logic Analyzer Submit tab submits signal/breakpoint names to the logic analyzer. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 57: Iice Assignments Report Tab

    By default, the report is displayed on the screen (standard out). The report can be redirected to a file using the iice assignmentsreport Tcl command (see iice, on page 51 in the Reference Manual. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 58 Chapter 1: Using the Debugger Logic Analyzer Interface Parameters © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 59 Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 60: Board Query

    The board query utility is initiated from the Certify user interface by selecting Launch Identify in Bring Up and Query Mode from the Tools popup menu. Running this utility creates a Tcl script for generating a first approximation of the board file.
  • Page 61 -interconnect -manual SRAM_1x1_HTII -name SRAM_1x1_HTII-PD-00787 -connector {FB2.A3} board_system_create -interconnect -manual SRAM_1x1_HTII -name SRAM_1x1_HTII-PD-00788 -connector {FB2.A6} # Clocks and Resets board_system_configure -voltage {FB1.V1a} 2.5 board_system_configure -clock {FB1.GCLK1} PLL1 board_system_configure -reset {FB1.RESET_A} 1 Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 62 Chapter 2: Board Bring-up Board Query #Save Board board_system_save -board new_conf_board.vb © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 63: Board Bring-Up

    Board Bring-up The board bring-up utility is initiated from the Certify user interface by selecting Launch Identify in Bring-up and Query Mode from the Tools popup menu. To use this utility, an Identify implementation must be defined for the project...

  • Page 64: Confpro Gui

    ConfPro GUI The ConfPro GUI is launched from the board bring-up utility in the debugger GUI. When you click the ConfPro button, the HAPS Configuration Tool menu shown below is displayed. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 65 Help menu. Complete ConfPro GUI documentation is available by selecting Help->Contents from the top-level menu. The location of the ConfPro installation is specified by selecting Options->Configure Confpro from the debugger menu. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 66: Board Configuration Tests

    Board tests are selected from the Utils & Tests drop-down menu. The same board configuration tests can be run directly from the debugger command prompt without requiring the installation of the Certify prototyping tool. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 67 HSTDM can run. The con_speed test is selected from the Utils & Tests drop-down menu and includes both a Speed and Mode selection. The test is executed by clicking the Run button. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 68 5. Source the connGen.tcl file: source identify_install/lib/bringup_utils/swlib/connGen.tcl To run the connGen.tcl script from the command line: 1. Open the project in Certify (project -load projectPath) 2. Run preparation (project -run compile) © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 69 When you use the connGen.tcl script in the Certify project directory to generate the connectivity.tcl file, the connGen.tcl script automatically orders the entries in the connectPorts statements. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 70: Utility Commands

    This menu is board/system dependent and remains disabled until a board/system selection is made. Selecting a command from the drop-down menu displays a description of the selected command, and clicking the Run © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 71 Sets the I/O voltage for the board regions. The voltage value and region are selected from the corresponding drop-down menus and differ with the board/system selected. Multiple regions can be selected using the Ctrl key. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 72 Frequency field. The frequency value is in kHz unless specified otherwise. The equivalent Tcl command syntax is: haps setclk clockName frequency restart Restarts the board. The equivalent Tcl command syntax is: haps restart © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 73 Output TCL file field. Clicking the Save button prompts for an alternate location to save the Tcl file (by default, the Tcl file is saved to the current working directory). The equivalent Tcl command syntax is: haps vbgen tclFile Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 74 Chapter 2: Board Bring-up Board Bring-up © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 75: Chapter 3: Incremental Flow

    Instrument Design Incremental Synthesize & Re-route Place and Route Debug Debug Requirements The incremental flow supported by the instrumentor/debugger tool set is available only when using a Xilinx Virtex-7 technology. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 76 (original) instrumentation can be re-instrumented. • When the prepare incremental function is disabled, only a subset of the instrument signals in the base instrumentation can be reinstrumented. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 77: Setting Up The Original Design

    3. Instrument and save your original design and close the instrumentor. 4. From the synthesis tool: – right click on the Identify implementation and select Add Place & Route from the popup menu – enable the Xilinx P & R check box –...

  • Page 78: Redefining The Instrumented Signals

    Go to the appropriate directory and use the following command sequence to generate the desired bit file: vivado -mode tcl read_checkpoint dcpFilename write_bitstream bitFilename © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 79: Incremental Implementation Support With Distributed Instrumentation

    MUX group as the deleted signal (the sampling logic in the IICE implementation is the only available resource for the new signal). Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 80 • The real-time debugging feature, which provides scope or logic analyzer access to instrumented signals directly through a Mictor board interface connector installed on the HAPS board, cannot be used with the incre- mental flow. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 81: Chapter 4: Iice Hardware Description

    TAP controller (the builtin option) or using the debug environ- ment implementation of the TAP controller (the soft option). See Chapter 5, Connecting to the Target System, for more information on the JTAG controller. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 82: Breakpoint And Watchpoint Blocks

    "0100" => result <= part_res; if cc = '1' then c_flag <= carry; if result = zero then z_flag <= '1'; else z_flag <= '0'; end if; end if; © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 83: Watchpoints

    ORed together. This effectively allows the breakpoints to operate independently – only one activated breakpoint must trigger in order to cause the sampling buffer to acquire its sample. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 84: Sampling Block

    Eventually, the contents of the sample block are uploaded to the debugger for display and formatting. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 85: Complex Counter

    • The counter target value can be set to any value in the counter’s range. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 86 For example, this mode could be used to trigger on the 12278th time a collision was detected in a bus arbiter. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 87: Disabling The Counter

    1 and its mode to events. Then, the complex counter will pass any received event from the Master Trigger Signal logic on to the sample block with no additional delay. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 88: State Machine Triggering

    A occurs exactly five cycles after pattern B, but only if pattern C does not intervene.” By default, the instrumentor instruments the design according to the simple trigger mode. See the following for more information on how to select the advanced trigger mode. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 89: Advanced Triggering Mode

    • the next-state value nstate • the trigger signal trigger (causes the sample buffer to take a snapshot if high) • the counter-enable signal cnten (if ‘1’, counter is decremented by 1) Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 90 RAM table width and is especially significant in the context of FPGA RAM primi- tives that allow a trade-off of width for depth. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 91 These steps can be done in any order. • setup the values for the trigger conditions using the debugger watch and stop commands. • setup the trigger state machine behavior using the debugger statemachine command. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 92 99). It is also important to note that the initial state for each run is always state 0 and that not all of the available states need to be defined. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 93 • c0,... cn, where n is the number of trigger conditions instrumented. These variables represent the output bit of the respective trigger condi- tion. • titriggerInID – the ID (0 thru 7) of an external trigger input. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 94 -all is specified. If the option -raw is given, the information is returned in a machine-processible form. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 95 These behaviors can be cascaded by moving on to the next behavior instead of triggering in the transition that has -trigger specified, as long as there are trigger conditions and states available. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 96 Please refer to the file syn_trigger_utils.tcl mentioned above for the implementa- tion of these trigger modes using the debugger statemachine command. Users can add their own convenience functions by following the examples in this file. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 97 (the triggers from source IICE units are ignored). iice controller -crosstriggermode DISABLED • The following debugger command causes the destination IICE to trigger when any source IICE triggers or on its own internal trigger. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 98 (c0). This sequence implements the “after iiceID” functionality of the simple- and complex-counter triggering modes. statemachine clear -all statemachine addtrans -from 0 -to 1 -cond "iiceID" statemachine addtrans -from 1 -to 0 -cond "c0" -trigger © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 99: State-Machine Editor

    10 states are defined. Clicking the icon displays the Statemachine Editor dialog box for the selected IICE. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 100 Initialize Counter statemachine transition editor (mutually exclusive with Decrement Counter Triggers sample buffer when condition is true Trigger Sample Buf- Transitions to specified state when condition is true Go to State © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 101 Enter the required parameters into the dialog box. These parameters include events, Boolean functions, transition count, and IICE unit. Click OK after all of the parameters are entered. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 102 • Click OK in the initial Statemachine Editor dialog box when the state-machine triggering condition has been defined. Note that you can view the corresponding state-machine commands in the debugger console window using the statemachine info -all command. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 103: State-Machine Examples

    – From the instrumentor Configure IICE dialog box, select the IICE Controller tab, click the State Machine triggering radio button, and specify the number of trigger states, trigger conditions, and the counter width in the corresponding fields. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 104 = 0 transition on counter = 0 count > 0 count trigger when counter = 0 The following figure shows the state-machine transition editor (click the Add new transition icon). © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 105 • To delete the state transitions from each IICE, use the following debugger command: statemachine clear -iice all • To enable complex counter triggering, use the following instrumentor command: iice controller complex Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 106 – Select the IICE Sampler tab and enable the Allow qualified sampling check box. 2. From the debugger GUI, select qualified_fill from the Sample Mode drop-down menu. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 107 Note: If you use the debugger st_snapshot_intr macro in place of the st_snapshot_fill macro, the sample buffer is continually overwritten until manually interrupted by a stop command. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 108 ; remote_trigger -pid 12 waits for the trigger condition in the active IICE and then sends a trigger to all IICE units in the debugger executable identified by process ID 12. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 109 FPGA or from an IICE module in a second FPGA. For information on using this feature with state-machine triggering, see the Importing External Triggers application note available on SolvNet. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 110 Chapter 4: IICE Hardware Description State Machine Triggering © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 111: Chapter 5: Connecting To The Target System

    Basic Communication Connection • JTAG Communication • JTAG Hardware in Instrumented Designs • Using the Built-in JTAG Port • Using the Synopsys Debug Port • JTAG Communication Debugging • UMRBus Communications Interface Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 112: Basic Communication Connection

    Cable Type The cable type is selected from a drop-down menu in the Communications settings area of the debugger project window (see following figure). © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 113 JTAG port, any Altera cable type can be used (communications are controlled through the Quartus driver). If you are using the soft JTAG port, you must use either a ByteBlaster or ByteBlaster MV hardware cable. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 114 (for example, setsys set lpt_address 0x0378 defines port lpt1). © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 115 To configure a Xilinx USB cable, click the Port Settings button to display the Configure Port Settings dialog box and select the appropriate communication speed frequency from the drop-down menu (see following figure). Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 116 From the project window, click the Port Settings button to display the Configure Port Settings dialog box and select the appropriate parallel port and communi- cation speed frequencies for both the parallel and USB cables from the drop-down menus (see following figure). © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 117 To configure a Catapult EJ-1 cable, select the Catapult_EJ1 setting from the Cable type drop-down menu. Click the Port Settings button to display the Configure Port Settings dialog box and enter the host IP address. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 118: Debugger Configuration

    FPGA board/device (see Client-Server Configuration for Remote Debugging, on page 120). © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 119 – the name of the log file. Start/Stop – server control buttons for starting and stopping the server. The Update log button adds a start/stop entry to the log file. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 120 Comm check button in the debugger project view. If the server starts successfully, you see the xilinxjtag process running in the task manager. If the server cannot be started on the host machine, an error message is displayed. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 121 USB driver installed. If you are using the Altera builtin JTAG, the bin directory for the Quartus software must be included in the users “path” variable. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 122 Be sure to connect ALL six leads. When you instrumented your design, you selected a JTAG connection to use: builtin or Synopsys debug port (soft). If you selected the builtin option, connect the cable to the same leads that you use for the JTAG based programming of the chip.
  • Page 123 Chip Programming Make sure that you program the device with the instrumented version of your design, NOT the original version. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 124: Jtag Communication

    Notice in the second figure that the TCK and TMS connections are connected directly to both devices while the TDI and TDO connections route from one device to the other and loop back to the JTAG cable. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 125 Chapter 5: Connecting to the Target System JTAG Communication JTAG Cable Control Control Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 126: Jtag Hardware In Instrumented Designs

    Consequently, these programming connections must be understood to properly connect the JTAG cable to the board and to properly communicate with the IICE. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 127 FPGAs. In this configuration, the IICE unit or units in each FPGA are individually accessed to provide the required debugging capabilities for their associated portion of the design logic. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 128: Using The Synopsys Debug Port

    Cable FPGA2 Control Using the Synopsys Debug Port By configuring the IICE using the soft JTAG port option, the design instrumen- tation includes a complete, JTAG-compliant TAP controller. The debugger connects the TAP controller to four top-level I/O connections to the design.
  • Page 129 JTAG Hardware in Instrumented Designs Serial JTAG Connection A programmable chip using the Synopsys FPGA Debug Port can also be connected in a serial chain. To allow the debugger to communicate with the device, the configuration of the device chain must be successfully auto-detected or declared using the chain command (see the Reference Manual).

  • Page 130: Boards Without Direct Built-In Jtag Connections

    For example, a board may connect an EEPROM directly to the built-in JTAG port on the programmable device. The EEPROM is directly programmable from the JTAG connection (see following figure). © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 131 JTAG cable to directly connect to the four I/O pins on the program- mable device as shown in the figure below. SYN Debug Port FPGA SYN TAP JTAG Control Cable EEPROM Configuration Port JTAG Control Cable EEPROM Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 132: Setting The Jtag Chain

    • the length of the JTAG instruction register for each device Instruction register length information is usually available in the bsd file for the particular device. Specifically, it is the Instruction_length attribute listed in the bsd file. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 133 Type the following sequence in the console window of the debugger: chain clear chain add prom 8 chain add fpga 5 chain select fpga chain info The following figure shows the results of the above command sequence. Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...

  • Page 134: Jtag Communication Debugging

    Also, the JTAG chain may be experiencing noise immunity/signal integ- rity problems. As a troubleshooting step, select a reduced JTAG clock frequency by clicking Port settings in the debugger project window and selecting a lower clock frequency. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

  • Page 135: On-Chip Identification Register

    This error usually means that the design on the programmable chip is NOT the instrumented version of the design. • ERROR: Instrumented design on FPGA differs from design loaded into Identify Debugger. The debugger verified that the chip is instrumented but the instrumen- tation does not match the project that was loaded into the debugger.

  • Page 136: Umrbus Communications Interface

    Communication interface section of on the Instrumentor Preferences dialog box or set the device jtagport option to umrbus in the console window. • In the debugger, set the com cabletype option to umrbus in the console window. © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 137 Byteblaster JTAGTech3710 data compression Microsemi masking Xilinx parallel DDR3 performance Xilinx USB debug sample data Xilinxauto viewing cables Debugger tool connection Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 138 IICE ncd file cross triggering JTAG connection IICE parameters individual operators condition IICE units cross triggering original source files searchpath incremental flow restrictions original sources © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...
  • Page 139 89, sampling signals triggers saving a project complex script files settings cable UMRBus JTAG chain UMRBus test signal values displaying multiple Identify Debugger User Guide © 2015 Synopsys, Inc. March 2015...
  • Page 140 19, combined with breakpoints deactivating folded hexadecimal values listing multiple transition value waveform display waveform viewers Verdi windows console Xilinx parallel cable settings Xilinx USB cable settings Xilinxauto cable settings © 2015 Synopsys, Inc. Identify Debugger User Guide March 2015...

Table of Contents