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Cypress CYW43340 Manual

Single-chip, dual-band (2.4 ghz/5 ghz) ieee 802.11 a/b/g/n mac/baseband/ radio with integrated bluetooth 5.0
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Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as "Cypress" document as this is the
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  • Page 1 Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.
  • Page 2 (2.4 GHz / 5 GHz) IEEE 802.11 a/b/g and single–stream IEEE 802.11n MAC/ baseband/radio, and Bluetooth 5.0. The CYW43340 includes integrated power amplifiers and LNAs for the 2.4 GHz and 5 GHz WLAN bands, and an integrated 2.4 GHz T/R switch. This greatly reduces the external part count, PCB footprint, and cost of the solution.
  • Page 3 PRELIMINARY CYW43340 Security: Reference WLAN subsystem provides Cisco® Compatible ■ ❐ Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0) WPA™ and WPA2™ (Personal) support for powerful encryp- ❐ Reference WLAN subsystem provides Wi–Fi Protected Set- tion and authentication ❐...

  • Page 4: Table Of Contents

    PRELIMINARY CYW43340 Contents 1. Introduction ..............4 12.1 Signal Assignments ........... 45 1.1 Overview ............... 4 12.2 Signal Descriptions ..........45 1.2 Features ..............5 12.3 I/O States ............54 1.3 Standards Compliance .......... 6 13. DC Characteristics ........... 57 2.

  • Page 5: Introduction

    Figure 2 shows the interconnect of all the major physical blocks in the CYW43340 and their associated external interfaces, which are described in greater detail in the following sections.

  • Page 6: Features

    PRELIMINARY CYW43340 1.2 Features The CYW43340 supports the following WLAN and Bluetooth features: IEEE 802.11a/b/g/n dual-band radio with internal Power Amplifiers, LNAs, and T/R switches ■ Bluetooth 5.0 with integrated Class 1 PA ■ Concurrent Bluetooth, and WLAN operation ■...

  • Page 7: Standards Compliance

    IEEE 802.11h 5 GHz Extensions ❐ IEEE 802.11i MAC Enhancements ❐ IEEE 802.11r Fast Roaming Support ❐ IEEE 802.11k Radio Resource Measurement ❐ The CYW43340 supports the following security features and proprietary protocols: Security: ■ ❐ WPA™ Personal ❐ WPA2™ Personal ❐...

  • Page 8: Power Supplies And Power Management

    2.1 Power Supply Topology One Buck regulator, multiple LDO regulators, and a Power Management Unit (PMU) are integrated into the CYW43340. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth, and WLAN in embedded designs.
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  • Page 10: Wlan Power Management

    2.2 WLAN Power Management The CYW43340 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages.

  • Page 11: Power-Off Shutdown

    VDDIO power applied to it. When the CYW43340 is powered on from this state, it is the same as a normal power-up and the device does not retain any information about its state from before it was powered down.

  • Page 12: Frequency References

    Figure 5 Figure 1. If the TCXO is dedicated to driving the CYW43340, it should be connected to the WRF_XTAL_OP pin through an external 1000 pF coupling capacitor, as shown in Figure 5. The internal clock buffer connected to this pin will be turned OFF when the CYW43340 goes into sleep mode.
  • Page 13 PRELIMINARY CYW43340 Figure 5. Recommended Circuit to Use with an External Dedicated TCXO 1000 pF TCXO WRF_XTAL_OP WRF_XTAL_ON WRF_TCXO_CK WRF_TCXO_VDD Figure 6. Recommended Circuit to Use with an External Shared TCXO To other devices TCXO W RF_TCXO_CK W RF_TCXO_VDD To always present 1.8V supply W RF_XTAL_OP W RF_XTAL_ON Table 3.

  • Page 14: Frequency Selection

    19.2, 19.44, 19.68, 19.8, 20, 26, 37.4, and 52 MHz, but also other frequencies in this range, with approximately 80 Hz resolution. The CYW43340 must have the reference frequency set correctly in order for any of the UART or PCM interfaces to function correctly, since all bit timing is derived from the reference frequency.

  • Page 15: External 32.768 Khz Low-Power Oscillator

    3.4 External 32.768 kHz Low-Power Oscillator The CYW43340 uses a secondary low frequency clock for low-power-mode timing. Either the internal low-precision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage, and temperature, which is adequate for some applications.

  • Page 16: Bluetooth Subsystem Overview

    The CYW43340 is the optimal solution for any Bluetooth voice and/or data application. The Bluetooth subsystem presents a standard Host Controller Interface (HCI) via a high speed UART and PCM for audio. The CYW43340 is qualified for Bluetooth 5.0 and supports all Bluetooth 4.0 features including BR/EDR and LE.

  • Page 17: Bluetooth Radio

    4.2 Bluetooth Radio The CYW43340 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band.

  • Page 18: Bluetooth Baseband Core

    ❐ 5.3 Test Mode Support The CYW43340 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.

  • Page 19: Bluetooth Power Management Unit

    5.4.2 Host Controller Power Management When running in UART mode, the CYW43340 may be configured so that dedicated signals are used for power management hand- shaking between the CYW43340 and the host. The basic power saving functions supported by those hand-shaking signals include the standard Bluetooth defined power savings modes and standby modes of operation.
  • Page 20 Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system and enables the CYW43340 to be fully integrated in an embedded device to take full advantage of the lowest power-saving modes.
  • Page 21 5.4.9 Burst Buffer Operation The CYW43340 has a data buffer that can buffer data being sent over the HCI and audio transports, then send the data at an increased rate. This mode of operation allows the host to sleep for the maximum amount of time, dramatically reducing system current consumption.

  • Page 22: Adaptive Frequency Hopping

    5.5 Adaptive Frequency Hopping The CYW43340 gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel map selection. The link quality is determined using both RF and baseband signal processing to provide a more accurate frequency-hop map.

  • Page 23: Microprocessor And Memory Unit For Bluetooth

    6.2 Reset The CYW43340 has an integrated power-on reset circuit that resets all circuits to a known power-on state. The BT power-on reset (POR) circuit is out of reset after BT_REG_ON goes High. If BT_REG_ON is low, then the POR circuit is held in reset.

  • Page 24: Bluetooth Peripheral Transport Unit

    The CYW43340 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYW43340 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface.
  • Page 25 PRELIMINARY CYW43340 7.1.6 PCM Interface Timing Short Frame Sync, Master Mode Figure 10. PCM Timing Diagram (Short Frame Sync, Master Mode) PCM_BCLK PCM_SYNC PCM_OUT HIGH IMPEDANCE PCM_IN Table 6. PCM Interface Timing Specifications (Short Frame Sync, Master Mode) Ref No. Characteristics...
  • Page 26 PRELIMINARY CYW43340 Short Frame Sync, Slave Mode Figure 11. PCM Timing Diagram (Short Frame Sync, Slave Mode) PCM_BCLK PCM_SYNC PCM_OUT HIGH IMPEDANCE PCM_IN Table 7. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode) Ref No. Characteristics Minimum Typical Maximum Unit PCM bit clock frequency –...
  • Page 27 PRELIMINARY CYW43340 Long Frame Sync, Master Mode Figure 12. PCM Timing Diagram (Long Frame Sync, Master Mode) PCM_BCLK PCM_SYNC PCM_OUT HIGH IMPEDANCE Bit 0 Bit 1 Bit 0 Bit 1 PCM_IN Table 8. PCM Interface Timing Specifications (Long Frame Sync, Master Mode) Ref No. Characteristics...
  • Page 28 PRELIMINARY CYW43340 Long Frame Sync, Slave Mode Figure 13. PCM Timing Diagram (Long Frame Sync, Slave Mode) PCM_BCLK PCM_SYNC PCM_OUT Bit 0 HIGH IMPEDANCE Bit 1 Bit 0 Bit 1 PCM_IN Table 9. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) Ref No. Characteristics...
  • Page 29 PRELIMINARY CYW43340 Short Frame Sync, Burst Mode Figure 14. PCM Burst Mode Timing (Receive Only, Short Frame Sync) PCM_BCLK PCM_SYNC PCM_IN Table 10. PCM Burst Mode (Receive Only, Short Frame Sync) Ref No. Characteristics Minimum Typical Maximum Unit PCM bit clock frequency –...
  • Page 30 PRELIMINARY CYW43340 Long Frame Sync, Burst Mode Figure 15. PCM Burst Mode Timing (Receive Only, Long Frame Sync) PCM_BCLK PCM_SYNC Bit 0 PCM_IN Bit 1 Table 11. PCM Burst Mode (Receive Only, Long Frame Sync) Ref No. Characteristics Minimum Typical Maximum Unit PCM bit clock frequency –...

  • Page 31: Uart Interface

    7.2 UART Interface The CYW43340 uses a UART for Bluetooth. The UART is a standard 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 9600 bps to 4.0 Mbps. The interface features an automatic baud rate detection capability that returns a baud rate selection.

  • Page 32: I 2 S Interface

    S WS is low, and right-channel data is transmitted when I S WS is high. Data bits sent by the CYW43340 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK.
  • Page 33 PRELIMINARY CYW43340 Table 14. Timing for I S Transmitters and Receivers Transmitter Receiver Lower LImit Upper Limit Lower Limit Upper Limit Notes Clock Period T – – – – – – Master Mode: Clock generated by transmitter or receiver 0.35T –...
  • Page 34 PRELIMINARY CYW43340 Figure 17. I S Transmitter Timing > 0.35T > 0.35T = 2.0V = 0.8V > 0 < 0.8T SD and WS T = Clock period = Minimum allowed clock period for transmitter T = T * t is only relevant for transmitters in slave mode. Figure 18. I S Receiver Timing > 0.35T > 0.35 = 2.0V = 0.8V > 0.2T > 0 SD and WS...

  • Page 35: Wlan Global Functions

    8.3 GPIO Interface On the WLBGA package, there are 8 GPIO pins available on the WLAN section of the CYW43340 that can be used to connect to various external devices. Upon power up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output pins via the GPIO control register.

  • Page 36: Uart Interface

    One UART interface can be enabled by software as an alternate function on pins WL_GPIO4 and WL_GPIO_5. Provided primarily for debugging during development, this UART enables the CYW43340 to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART and provides a FIFO size of 64 ×...

  • Page 37: Wlan Host Interfaces

    9. WLAN Host Interfaces 9.1 SDIO v2.0 The CYW43340 WLAN section supports SDIO version 2.0, including the following modes: Default speed up to 25 MHz, including 1- and 4-bit modes (3.3V signaling) High speed up to 50 MHz (3.3V signaling) It also has the ability to map the interrupt signal onto a GPIO pin for applications requiring an interrupt different than what is provided by the SDIO interface.
  • Page 38 PRELIMINARY CYW43340 Figure 21. Signal Connections to SDIO Host (SD 1-Bit Mode) DATA SD Host CYW43340 Figure 22. SDIO Pull-Up Requirements VDDIO_SD (see note) (see note) SD Host CYW43340 DATA[3:0] Note: Per Section 6 of the SDIO specification, 10 to 100 kohm pull-ups are required on the four DATA lines and the CMD line.  This  requirement must be met during all operating states by using external pull-up resistors or properly programming internal SDIO  Host pull-ups.  The CYW43340 does not have internal pull-ups on these lines. Document Number: 002-14943 Rev. *N Page 37 of 96 Arrow.com. Arrow.com.

  • Page 39: Hsic Interface

    PRELIMINARY CYW43340 9.2 HSIC Interface As an alternative to SDIO, an HSIC host interface can be enabled using the strapping option pins strap_host_ifc_[3:1]. HSIC is a simplified derivative of the USB2.0 interface designed to replace a standard USB PHY and cable for short distances (up to 10 cm) on board point-to-point connections.

  • Page 40: Wireless Lan Mac And Phy

    10. Wireless LAN MAC and PHY 10.1 MAC Features The CYW43340 WLAN media access controller (MAC) supports features specified in the IEEE 802.11 base standard, and amended by IEEE 802.11n. The salient features are listed below: Transmission and reception of aggregated MPDUs (A-MPDU) ■...
  • Page 41 PRELIMINARY CYW43340 Figure 24. WLAN MAC Architecture Embedded CPU Interface Host Registers, DMA Engines TX-FIFO RX-FIFO 32 KB 10 KB UCODE Memory Backoff, BTCX TKIP, AES, WAPI SHM  IHR  Shared Memory 6 KB EXT- IHR TX A-MPDU RX A-MPDU MAC-PHY Interface The programmable state machine (PSM) is a micro-coded engine, which provides most of the low-level control to the hardware, to implement the IEEE 802.11 specification.
  • Page 42 PRELIMINARY CYW43340 The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames in the TXFIFO. It interfaces with WEP module to encrypt frames, and transfers the frames across the MAC-PHY interface at the appropriate time determined by the channel access mechanisms.

  • Page 43: Wlan Phy Description

    CYW43340 10.2 WLAN PHY Description The CYW43340 WLAN Digital PHY is designed to comply with IEEE 802.11a/b/g/n single-stream to provide wireless LAN connectivity supporting data rates from 1 Mbps to 150 Mbps for low-power, high-performance handheld applications. The PHY has been designed to work with interference, radio nonlinearity, and impairments. It incorporates efficient implementations of the filters, FFT and Viterbi decoder algorithms.
  • Page 44 One of the key features of the PHY is its space-time block coding (STBC) capability. The STBC scheme can obtain diversity gains in a fading channel environment. On a connection with an access point that uses multiple transmit antennas and supports STBC, the CYW43340 can process two space-time streams to improve receiver performance. Figure 26 is a block diagram showing the STBC implementation in the receive path.

  • Page 45: Wlan Radio Subsystem

    11. WLAN Radio Subsystem The CYW43340 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands.

  • Page 46: Pinout And Signal Descriptions

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  • Page 47 PRELIMINARY CYW43340 Table 17. WLBGA Signal Descriptions WLBGA Ball Signal Name Type Description WLAN RF Signal Interface WRF_RFIN_2G 2.4G RF input WRF_RFIN_5G 5G RF input WRF_RFOUT_2G 2.4G RF output WRF_RFOUT_5G 5G RF output WRF_GPIO_OUT – RF Control Signals RF_SW_CTRL_0 RF switch enable...
  • Page 48 PRELIMINARY CYW43340 Table 17. WLBGA Signal Descriptions (Cont.) WLBGA Ball Signal Name Type Description WLAN GPIO Interface WL_GPIO_0 This pin can be programmed by software to be a GPIO. WL_GPIO_1 This pin can be programmed by software to be a GPIO or an AP_READY or HSIC_HOST_READY input from the host indicating that it is awake.
  • Page 49 PRELIMINARY CYW43340 Table 17. WLBGA Signal Descriptions (Cont.) WLBGA Ball Signal Name Type Description Clocks WRF_XTAL_CAB_XON XTAL oscillator output WRF_XTAL_CAB_XOP XTAL oscillator input WRF_TCXO_CKIN2V TCXO buffered input. When not using a TCXO this pin should be connected to ground. CLK_REQ External system clock request—Used when the...
  • Page 50 Miscellaneous WL_REG_ON Used by PMU to power up or power down the internal CYW43340 regulators used by the WLAN section. Also, when deasserted, this pin holds the WLAN section in reset. This pin has an internal 200 k pull-down resistor that is enabled by default.
  • Page 51 PRELIMINARY CYW43340 Table 17. WLBGA Signal Descriptions (Cont.) WLBGA Ball Signal Name Type Description Integrated Voltage Regulators SR_VDDBATA5V Quiet VBAT SR_VDDBATP5V Power VBAT SR_VLX CBUCK switching regulator output. See Table 35 on page 77 for details of the inductor and capacitor required on this output.
  • Page 52 PRELIMINARY CYW43340 Table 17. WLBGA Signal Descriptions (Cont.) WLBGA Ball Signal Name Type Description Miscellaneous Power Supplies HSIC_DVDD1P2_OUT 1.2V supply for HSIC interface. This pin can be NO_CONNECT when HSIC is not used. VDDC_E9 Core supply for WLAN and BT.
  • Page 53 PRELIMINARY CYW43340 Table 17. WLBGA Signal Descriptions (Cont.) WLBGA Ball Signal Name Type Description VSS_K8 Ground VSS_K10 Ground VSS_K11 Ground VSS_L8 Ground VSS_L9 Ground VSS_L10 Ground VSS_L11 Ground VSS_M8 Ground VSS_M9 Ground VSS_M10 Ground VSS_M11 Ground VSS_N7 Ground VSS_N8 Ground...
  • Page 54 PRELIMINARY CYW43340 12.2.1 WLAN GPIO Signals and Strapping Options The pins listed in Table 18 on page 53 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table.

  • Page 55: I/O States

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  • Page 58: Dc Characteristics

    PRELIMINARY CYW43340 13. DC Characteristics Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. 13.1 Absolute Maximum Ratings Caution! The absolute maximum ratings in Table 21 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration.

  • Page 59: Electrostatic Discharge Specifications

    PRELIMINARY CYW43340 13.3 Electrostatic Discharge Specifications Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging.
  • Page 60 PRELIMINARY CYW43340 Table 24. Recommended Operating Conditions and DC Characteristics (Cont.) Value Parameter Symbol Unit Minimum Typical Maximum Other Digital I/O Pins For VDDIO = 1.8V: Input high voltage 0.65 × VDDIO – – Input low voltage – 0.35 × VDDIO Output high voltage @ 2 mA VDDIO –...

  • Page 61: Bluetooth Rf Specifications

    PRELIMINARY CYW43340 14. Bluetooth RF Specifications Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, limit values apply for the conditions specified in Table 22: “Environmental Ratings,” on page 57 Table 24: “Recommended Operating Conditions and DC Characteristics,”...
  • Page 62 PRELIMINARY CYW43340 Table 25. Bluetooth Receiver RF Specifications Parameter Conditions Minimum Typical Maximum Unit The specifications in this table are measured at the Chip port output unless otherwise specified. Note: General Frequency range – 2402 – 2480 RX sensitivity GFSK, 0.1% BER, 1 Mbps –...
  • Page 63 PRELIMINARY CYW43340 Table 25. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit 2510MHz LTE band7 FDD 20M BW – –26 – 2530MHz LTE band7 FDD 20M BW – –25 – 2550MHz LTE band7 FDD 20M BW –...
  • Page 64 PRELIMINARY CYW43340 Table 25. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit  /4 DPSK (2 Mbps) 698–716 MHz WCDMA – –11 – 776–794 MHz WCDMA – –11 – 824–849 MHz GSM850 – –12 – 824–849 MHz WCDMA –...
  • Page 65 PRELIMINARY CYW43340 Table 25. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit 2110–2170 MHz – –147 – dBm/Hz a. The Bluetooth reference level for the required signal at the Bluetooth chip port is 3 dB higher than the typical sensitivity level. Document Number: 002-14943 Rev. *N Page 64 of 96 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 66 PRELIMINARY CYW43340 Table 26. Bluetooth Transmitter RF Specifications Parameter Conditions Minimum Typical Maximum Unit General Frequency range 2402 – 2480 Basic rate (GFSK) TX power at Bluetooth – 11.0 – QPSK TX Power at Bluetooth – – 8PSK TX Power at Bluetooth –...
  • Page 67 PRELIMINARY CYW43340 Table 27. Local Oscillator Performance Parameter Minimum Typical Maximum Unit LO Performance s Lock time – – Initial carrier frequency tolerance – ±25 ±75 Frequency Drift DH1 packet – ±8 ±25 DH3 packet – ±8 ±40 DH5 packet –...

  • Page 68: Wlan Rf Specifications

    15.1 Introduction The CYW43340 includes an integrated dual-band direct conversion radio that supports either the 2.4 GHz band or the 5 GHz band. The CYW43340 does not provide simultaneous 2.4 GHz and 5 GHz operation. This section describes the RF characteristics of the 2.4 GHz and 5 GHz portions of the radio.

  • Page 69: Ghz Band General Rf Specifications

    PRELIMINARY CYW43340 15.2 2.4 GHz Band General RF Specifications Table 29. 2.4 GHz Band General RF Specifications Item Condition Minimum Typical Maximum Unit TX/RX switch time Including TX ramp down – – µs RX/TX switch time Including TX ramp up –...
  • Page 70 PRELIMINARY CYW43340 Table 30. WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit RX sensitivity 40 MHz channel spacing for all MCS rates (GF) (10% PER for 4096 octet MCS 0 – –89 – a,b. PSDU)
  • Page 71 PRELIMINARY CYW43340 Table 30. WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Blocking level for 3dB RX sensi- 776–794 MHz CDMA2000 –12.3 – – tivity degradation (without 824–849 MHz cdmaOne –9.4 – – external filtering) 824–849 MHz...
  • Page 72 PRELIMINARY CYW43340 Table 30. WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Adjacent channel rejection MCS7 –61 dBm –2 – – MCS0–7 (Difference between MCS6 –62 dBm –1 – – interfering and desired signal (25 MHz apart) at 10% PER for MCS5 –63 dBm...

  • Page 73: Wlan 2.4 Ghz Transmitter Performance Specifications

    PRELIMINARY CYW43340 15.4 WLAN 2.4 GHz Transmitter Performance Specifications Note: The specifications in Table 31 are measured at the chip port output, unless otherwise specified. Table 31. WLAN 2.4 GHz Transmitter Performance Specifications Parameter Condition/Notes Minimum Typical Maximum Unit Frequency range –...

  • Page 74: Wlan 5 Ghz Receiver Performance Specifications

    PRELIMINARY CYW43340 15.5 WLAN 5 GHz Receiver Performance Specifications Note: The specifications in Table 32 are measured at the chip port input, unless otherwise specified. Table 32. WLAN 5 GHz Receiver Performance Specifications Parameter Condition/Notes Minimum Typical Maximum Unit Frequency range –...
  • Page 75 PRELIMINARY CYW43340 Table 32. WLAN 5 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit RX sensitivity 40 MHz channel spacing for all MCS rates (Mixed mode) (10% PER for 4096 octet MCS 0 – –87.5 – PSDU)

  • Page 76: Wlan 5 Ghz Transmitter Performance Specifications

    PRELIMINARY CYW43340 Table 32. WLAN 5 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Alternate adjacent channel 6 Mbps OFDM –78.5 dBm – – rejection 9 Mbps OFDM –77.5 dBm – – (Difference between interfering and desired signal (40 MHz 12 Mbps OFDM –75.5 dBm...

  • Page 77: General Spurious Emissions Specifications

    PRELIMINARY CYW43340 Table 33. WLAN 5 GHz Transmitter Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit TX power at chip port for 6 Mbps – – highest power level setting at 54 Mbps – – 25°C, MCS0 (20 MHz) –...

  • Page 78: Internal Regulator Electrical Specifications

    PRELIMINARY CYW43340 16. Internal Regulator Electrical Specifications Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Functional operation is not guaranteed outside of the specification limits provided in this section.

  • Page 79: Ldo (Ldo3P3)

    PRELIMINARY CYW43340 Table 35. Core Buck Switching Regulator (CBUCK) Specifications (Cont.) Specification Notes Units External inductor, L – – – µH External output capacitor, Cout Ceramic, X5R, 0402, ESR < 30 mΩ at 4 MHz, – µF ±20%, 6.3V, 4.7 µF, ®...

  • Page 80: Ldo (Ldo2P5)

    PRELIMINARY CYW43340 16.3 2.5V LDO (LDO2P5) Table 37. LDO2P5 Specifications Specification Notes Min. Typ. Max. Unit Input supply voltage Min= 2.52+0.15=2.67V Dropout voltage requirement must be met under the maximum load for performance specifications. Output current – – – Output voltage, Vo default = 2.52V...

  • Page 81: Cldo

    PRELIMINARY CYW43340 Table 38. HISCDVDD LDO Specifications (Cont.) Specification Notes Units PSRR at 10 kHz Input ≥ 1.35V, 50 to 300 pF, V = 1.2V – – Load: 80 mA Load: 40 mA PSRR at 100 kHz Input ≥ 1.35V, 50 to 300 pF, V = 1.2V...

  • Page 82: Lnldo

    PRELIMINARY CYW43340 16.6 LNLDO Table 40. LNLDO Specifications Specification Notes Units Input supply voltage, Vin Min = 1.2V + 0.1V = 1.3V. 1.35 Dropout voltage requirement must be met under maximum load. Output current – – Output voltage, V Programmable in 25 mV steps.

  • Page 83: System Power Consumption

    PRELIMINARY CYW43340 17. System Power Consumption Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, these values apply for the conditions specified in Table 24: “Recommended Operating Conditions and DC ■...

  • Page 84: Bluetooth And Ble Current Consumption

    PRELIMINARY CYW43340 17.2 Bluetooth and BLE Current Consumption The Bluetooth current consumption measurements are shown in Table The WLAN core is in reset (WL_REG_ON = low) for all measurements provided in Table ■ The BT current consumption numbers are measured based on GFSK TX output power = 8 dBm.

  • Page 85: Interface Timing And Ac Characteristics

    PRELIMINARY CYW43340 18. Interface Timing and AC Characteristics 18.1 SDIO Timing 18.1.1 SDIO Default Mode Timing SDIO default mode timing is shown by the combination of Figure 31 Table Figure 31. SDIO Bus Timing (Default Mode) SDIO_CLK Input Output ODLY...
  • Page 86 PRELIMINARY CYW43340 18.1.2 SDIO High-Speed Mode Timing SDIO high-speed mode timing is shown by the combination of Figure 32 Table Figure 32. SDIO Bus Timing (High-Speed Mode) 50% VDD SDIO_CLK Input Output ODLY Table 44. SDIO Bus Timing Parameters (High-Speed Mode)

  • Page 87: Hsic Interface Specifications

    PRELIMINARY CYW43340 18.2 HSIC Interface Specifications Table 45. HSIC Timing Parameters Parameter Symbol Minimum Typical Maximum Unit Comments HSIC signaling voltage – I/O voltage input low –0.3 – 0.35 × V – I/O Voltage input high 0.65 × V –...

  • Page 88: Power-Up Sequence And Timing

    (one for WL_REG_ON and one for BT_REG_ON), then only one of the two signals needs to be high to enable the CYW43340 regulators. The CYW43340 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC ■...
  • Page 89 PRELIMINARY CYW43340 Figure 34. WLAN = OFF, Bluetooth = OFF 32.678 kHz Sleep Clock VBAT* VDDIO WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise faster than 40 microseconds or slower than 100 milliseconds. 2. VBAT should be up before or at the same time as VDDIO .  VDDIO should NOT be present first  or be held high before VBAT is high. Figure 35. WLAN = ON, Bluetooth = OFF 32.678 kH z Sleep Clock VBA T 90%  of VH VDDIO ~ 2 Sleep cycles W L_REG _O N...
  • Page 90 PRELIMINARY CYW43340 Figure 36. WLAN = OFF, Bluetooth = ON 32 .678 kH z Sleep C lock V B A T 90 %  of V H V D D IO ~ 2 Sleep cycles W L_R EG _O N B T_ R EG _ O N *N otes: 1. V B A T should no t rise faster than ...

  • Page 91: Package Information

    PRELIMINARY CYW43340 20. Package Information 20.1 Package Thermal Characteristics Table 47. Package Thermal Characteristics Characteristic WLBGA  (°C/W) (value in still air) 36.8  (°C/W) 5.93  (°C/W) 2.82  (°C/W) 9.26  (°C/W) 16.93 Maximum Junction Temperature T 114.08 Maximum Power Dissipation (W) 1.198...

  • Page 92: Mechanical Information

    PRELIMINARY CYW43340 21. Mechanical Information Figure 37. 141-Ball WLBGA Package Mechanical Information Document Number: 002-14943 Rev. *N Page 91 of 96 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 93 PRELIMINARY CYW43340 Figure 38. WLBGA Keep-Out Areas for PCB Layout—Bottom View Note: No top-layer metal is allowed in keep-out areas. Document Number: 002-14943 Rev. *N Page 92 of 96 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 94: Ordering Information

    IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates.

  • Page 95: Document History

    Section 26: “Ordering Information,” on page 194. 03/04/0214 43340–DS106-R: Figure 38: “141-Bump CYW43340 WLBGA Ball Map (Bottom View),” on page 58 and Table 18: “WLBGA Signal Descriptions,” on page 59: Updated signal names for No Connect, VDDC, VDDIO, VSS, VSSC, and WRF_PA5G_VBAT_GND3P3 pins.
  • Page 96 PRELIMINARY CYW43340 Document Title: CYW43340, Single-Chip, Dual-Band (2.4 GHz/5 GHz) IEEE 802.11 a/b/g/n MAC/Baseband/Radio with Inte- grated Bluetooth 5.0 Document Number: 002-14943 Submission Revision Description of Change Date 09/10/2015 43340–DS110-R: Updated: Table 32: “WLAN 2.4 GHz Receiver Performance Specifications,” on page 85...

  • Page 97: Sales, Solutions, And Legal Information

    “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device.

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