Block Diagram - LG RT-44SZ80LB Service Manual

RT- 44SZ80L P
2 nd IF ( 6M)
ATSC/ NTSC
RF
IF_AGC
Tuner
SW
(TDVB- 001P)
MSP
SIF
NTSC Tuner
4450
IIC1
(6700NFNS06C )
V
Rear AV_1
V, LR
3
IN1 TV IN6
Rear AV_2
V, LR
3
IN2
Rear AV_3
V, LR
3
IN5
Fro nt AV_4
V, LR
3
IN4
Rear S_1
YC
2
IN1
A/ V SW
Rear S_2 YC
2
IN2
( CXA2069)
Fro nt S_4
YC
2
IN4
MNT_Out V
1
OUT3
MNT_Out
YC
2
OUT3
OUT1
Ext A LR
2
MSP4450
IIC4
Co mp _1
YCb Cr
3
IN4
Co mp _2
YCb Cr
3
IN3 Vid eo SW
RGB- DTV/ - PC RGBHV
( CXA2181)
5 IN2
uCo m
IIC4 IIC4
( M37151)
NTSC Tuner SIF
So und Pro c
Ext A LR ( MSP4450)
CXA2069
2
MNT_Out
LR
2 IIC4
Variab le_Out
LR
2
So und Pro c
AMP
PWM Co nv.
LR
2
( NSP6241B)
( TAS5112)
RX[ 0: 2] , RXC
8
I2C Ext. DDC( I2C)
BSS83
BSS83
2
( 82B715)
EEPROM( AT24C02)
Reset
TP[ 0: 7] ,
Slim VSB
TP_CLK,
( LGDT3302
TP_valid
10
)
X-t al
OSC 2. 5 V
( 20. 25M)
( 25M) Reg .
Vid eo
V
Dec o d er
( VPC3230D)
LPF
LPF
LPF
OUT1 V, YC
( 8M)
( 8M)
3
( 8M)
SDRAM
( K4S161622E)
OUT2
X-t al
( 24. 57M)
YC
LPF
LPF
Vid eo
2
( 8M)
( 8M)
Dec o d er
( uPD64011A)
V,
IN3
3
MNT_Out
YC
n480i
CPU
YCb Cr
Ac t ive LPF
3
( AF9397)
( AD9883A)
H, V, CLP
HV
EPLD1
3
2
( XC95144XL)
FID
OR3
HV_PC
PC_IN
HV_p o l
CPU
2
LPF
LPF
I2S_In
HD- II
I2S
HD- II
3
Out
RGB
OR1
TMDS Rx 24
( HDCP)
H, V,
OR2
3
Sil169
CLK
PD
Reset CPU
VALID
EPLD1 HD- II
Dat a[ 0: 7] ,
[ MUX,
OR4
9
CLK
3- st at e]
SEL_VSB/ 1394,
SEL_TP
CPU
IIC2
Data[ 0: 7] ,
TP/ D1
9
OR4
9
CLK
Wired -
OR
Reset
IIC2
YCb Cr YCb Cr
OR1
16 24
H, V, CLK H, V, CLK
OR2
3 3
FID FID
OR3
IIC2
Dat a[ 0: 31]
YCb Cr
OR1
24
ADC
H, V,
3
OR2
CLK
X-t al
( 10M )
EPLD_JTAG
EPLD1
4
( XC95144XL
CPU
I2C H ub
_
)
(M3 26V 7F J F P )
[ 0: 1]
IIC1
EN[ 0: 3]
IRQ
IIC2
IIC3 I2C Hub I2C c t rl
( PCA9516) ( PCF8584)
IIC4
HV Sync
HD- II
iEP
YPb Pr ( LGDP4410)
HD- II
IIC2
VCXO
SDRAM
SDRAM
27Mhz
( HY57V643220C)
( HY57V643220C)
RC
FR_60
1. 8 V
Filter
SysClk
Reg .
SDRAM I/ F
HD2_CHA PWM,
Clo c k
LG
HD- ll
Vid eo
LGDT1102
HV Sync
Out
HD2_EXT
YPb Pr
Ho st I/ F
MUX
RDY, Ad d r . [ 1: 12] ,
( 74157)
DREQ, WR, CS, STRB,
IRQ DACK, CLK,
Sel _ HD2
Reset
CPU
Erro r, Emp h SPDIF Rev.
( CS8415A)
Reset
IIC3
Rx,Tx
Reset
KA75270
Ad d r . [ 2: 21] ,
CS, WE, OE,
74HC14
FlashDo w n
Dat a[ 0: 31]
Ad d r0,
Ad d r . [ 2: 13, 22: 23] ,
WBE0, OE, CS
CLK, CKE, CS, WE,
CAS, RAS, DQM[ 0: 3]
Dat a[ 0: 7]
HV Sync
LVDS
LVDS Out p ut
Tx
RGB
( THC63LVD103)
IIC2
CLK Syn.
( LGDPLL)
VDPClk
( 74. 25M)
NT2Clk
( 27M)
EPLD
iEP
iEP
Sel _ DVD
CPU
RS- 232C
( ST3232)
FLASH
FLASH
( 29LV160B)
( AT49LV160)
SDRAM
SDRAM
( HY57V651620B)
( HY57V641620B]
)