Ds90C385 - Hitachi 22LD4200UK Service Manual

36 47 38
37 46 37
38 45 -
39 44 -
40 43 -
41 - -
42 42 36
43 41 35
- - -
- - -
- - -
44 40 34
45 39 33
46 38 32
47 37 31
48 36 30
49 35 29
50 34 28
51 33 27
52 - -
53 32 -
54 31 26
55 30 -
56 29 25
57 28 24
58 27 23
59 26 22
60 25 21
- - -
- - -
61 24 20
62 23 -
63 22 -
64 21 19
65 20 18
66 19 17
- - -
- - -
67 18 16
- - -
- - -
68 17 15

11.21. DS90C385

11.21.1. General Description
The DS90C385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data
streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and
transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and
control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel.
Using a 85 MHz clock, the data throughput is 297.5 Mbytes/sec. Also available is the DS90C365 that
converts 21 bits of LVCMOS/LVTTL data into three LVDS (Low Voltage Differential Signaling) data
streams. Both transmitters can be programmed for Rising edge strobe or Falling edge strobe through a
dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe
Receiver (DS90CF386/DS90CF366) without any translation logic.
The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which
provides a 44 % reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal
means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
11.21.2. Features
• 20 to 85 MHz shift clock support
• Best–in–Class Set & Hold Times on TxINPUTs
• Tx power consumption <130 mW (typ) @85MHz Grayscale
• Tx Power-down mode <200µW (max)
• Supports VGA, SVGA, XGA and Dual Pixel SXGA.
• Narrow bus reduces cable size and cost
22" TFT TV Service Manual
51 39 SC3_IN_R
50 38 SC3_IN_L
49 37 ASG4
48 36 SC4_IN_R
47 35 SC4_IN_L
46 - NC
45 34 AGNDC
44 33 AHVSS
43 - AHVSS
42 - NC
41 - NC
40 32 CAPL_M
39 31 AHVSUP
38 30 CAPL_A
37 29 SC1_OUT_L
36 28 SC1_OUT_R
35 27 VREF1
34 26 SC2_OUT_L
33 25 SC2_OUT_R
32 - NC
31 24 NC
30 23 DACM_SUB
29 22 NC
28 21 DACM_L
27 20 DACM_R
26 19 VREF2
25 18 DACA_L
24 17 DACA_R
23 - NC
22 - NC
21 16 RESETQ
20 15 NC
19 14 NC
18 13 NC
17 12 I2S_DA_IN2
16 11 DVSS
15 - DVSS
14 - DVSS
13 10 DVSUP
12 - DVSUP
11 - DVSUP
10 9 ADR_CL
IN LV
IN LV
AHVSS
IN LV
IN LV
LV or AHVSS
OBL
OBL
OBL
LV
LV
OBL
OBL
OBL
OUT LV
OUT LV
OBL
OUT LV
OUT LV
LV
LV
OUT LV
LV
OUT LV
OUT LV
OBL
OUT LV
OUT LV
LV
LV
IN OBL
LV
LV
LV
IN LV
OBL
OBL
OBL
OBL
OBL
OBL
OUT LV
27
SCART 3 input, right
SCART 3 input, left
Analog Shield Ground 4
SCART 4 input, right
SCART 4 input, left
Not connected
Analog reference voltage
Analog ground
Analog ground
Not connected
Not connected
Volume capacitor MAIN
Analog power supply 8V
Volume capacitor AUX
SCART output 1, left
SCART output 1, right
Reference ground 1
SCART output 2, left
SCART output 2, right
Not connected
Not connected
Subwoofer output
Not connected
Loudspeaker out, left
Loudspeaker out, right
Reference ground 2
Headphone out, left
Headphone out, right
Not connected
Not connected
Power-on-reset
Not connected
Not connected
Not connected
2
I S2-data input
Digital ground
Digital ground
Digital ground
Digital power supply 5V
Digital power supply 5V
Digital power supply 5V
ADR clock