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GOWIN JESD204B User Manual

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Gowin JESD204B IP
User Guide
IPUG1019-1.0E, 05/25/2023

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  • Page 1 Gowin JESD204B IP User Guide IPUG1019-1.0E, 05/25/2023...
  • Page 2 Copyright © 2023 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. is a trademark of Guangdong Gowin Semiconductor Corporation and is registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
  • Page 3 Revision History Date Version Description 05/25/2023 1.0E Initial version published.

  • Page 4: Table Of Contents

    Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................... 1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ................... 1 1.4 Support and Feedback ....................... 2 2 Function Introduction ..................
  • Page 5 Contents 4.3.1 Bus Reset Port ....................... 26 4.3.2 Reset Core Logic via Pins ..................... 26 4.3.3 Reset Core Logic via Registers ..................27 4.3.4 SerDes Related Reset ....................27 4.3.5 Reset Flow ........................27 4.4 Subclass ........................... 27 4.5 SYSREF ........................... 28 4.5.1 SYSREF Timing ......................

  • Page 6: List Of Figures

    Figure 3-2 Receiver Block Diagram ....................6 Figure 3-3 Gowin JESD204B IP TX Port Diagram................7 Figure 3-4 Gowin JESD204B IP RX Core Port Diagram ..............10 Figure 3-5 Write Timing Diagram of Configuration Interface ............. 13 Figure 3-6 Read Timing Diagram of Configuration Interface ............. 13 Figure 3-7 F=2 K=32, TX Data Interface Timing ................
  • Page 7 Table 1-1 Terminology and Abbreviations ..................1 Table 2-1 Gowin JESD204B IP Overview ..................3 Table 2-2 Resource Utilization of Gowin JESD204B IP ..............4 Table 3-1 I/O List of TX Core ......................8 Table 3-2 I/O List of RX Core ......................11 Table 3-3 Gowin JESD204B IP Registers ..................
  • Page 8 Table 3-32 Buffer Adjust [Offset: lane0-0x0F0, lane1-0x130 …… lane3-0x1B0] ......24 Table 6-1 Register Definition ......................40 Table 7-1 Documents List ........................44 Table 7-2 Design Source Code List of Gowin JESD204B IP ............. 44 Table 7-3 Gowin JESD204B IP RefDesign Folder List ..............44 IPUG1019-1.0E...

  • Page 9: About This Guide

    1.1 Purpose About This Guide 1.1 Purpose The purpose of Gowin JESD204B IP User Guide is to help you learn the features and usage of Gowin JESD204B IP by providing the descriptions of functions, GUI, and reference design, etc. 1.2 Related Documents The latest user guides are available on the GOWINSEMI Website.

  • Page 10: Support And Feedback

    1 About This Guide 1.4 Support and Feedback 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below.

  • Page 11: Function Introduction

    2.1 Overview Function Introduction 2.1 Overview JESD204B is a high-speed serial interface used to connect Analog-to- Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) to logic devices. The IP implements the data link layer functions in the JESD204B protocol, including Code Group Sync (CGS), Initial Lane Alignment Sequence (ILAS), user data output, etc.

  • Page 12: Resource Utilization

    2 Function Introduction 2.3 Resource Utilization 2.3 Resource Utilization JESD204B IP can be implemented by Verilog. Its performance and resource utilization may vary when the design is employed in different devices, or at different densities, speeds, or grades. Take GW5AT series as an instance, and the resource utilization is as shown in Table 2-2.

  • Page 13: Functional Description

    3 Functional Description 3.1 System Block Diagram Functional Description 3.1 System Block Diagram Transmitter The transmitter of JESD204B is as shown in Figure 3-1 . Figure 3-1 Transmitter Block Diagram tx_ilas TO SERDES Data Stream INTERFACE data_src data_swap tx_lane0 tx_lane1...

  • Page 14: Receiver

     tx_lmfc_ctrl module: Used to generate a local multiframe clock for subclass 1  Cfg_register module: Used to configure and monitor internal registers 3.2 Receiver The receiver of JESD204B is as shown in Figure 3-2 . Figure 3-2 Receiver Block Diagram FROM SERDES INTERFACE...

  • Page 15: Port List

    Gowin JESD204B IP TX core and RX core interfaces are independent of each other and described separately below. 3.3.1 TX Core Interface The IO ports of the Gowin JESD204B IP TX core are shown in Figure 3-3. Figure 3-3 Gowin JESD204B IP TX Port Diagram IPUG1019-1.0E...

  • Page 16: Table 3-1 I/O List Of Tx Core

    Write strobe signal, fixed to 4’hf SYSREF input, this signal is required when tx_sysref_i configured as subclass 1. JESD204B defines a synchronous signal as a low-level active synchronous request tx_sync_n_i signal, so the signal remains low until the comma alignment is complete and high when ILA and normal data are requested.
  • Page 17 3 Functional Description 3.3 Port List Signal Name Description asserted in the same cycle, depending on the bytes per frame (e.g., F = 1, tx_data_sof = 1111). End of frame boundary indication; this signal is 4 bits, and is used to indicate the tx_data_eof_o frame last byte position in tx_data in the clock cycle.

  • Page 18: Rx Core Interface

    3 Functional Description 3.3 Port List 3.3.2 RX Core Interface The IO ports of the Gowin JESD204B IP RX core are shown in Figure 3-4. Figure 3-4 Gowin JESD204B IP RX Core Port Diagram IPUG1019-1.0E 10(45)

  • Page 19: Table 3-2 I/O List Of Rx Core

    Bus strobe signal, fixed to 4’hf. rx_cfg_strb_i[3:0] SYSREF input, this signal is required rx_sysref_i when configured as subclass 1. JESD204B defines a synchronous signal as a low-level active synchronous request signal, so the rx_sync_o signal remains low until the comma alignment is complete and high when ILA and normal data are requested.
  • Page 20 3 Functional Description 3.3 Port List Signal Name Description  When rx_data_sof = 1000, rx_data contains the last 3 bytes of the previous frame in bits [23:0] and the first byte of the new frame is in bits [31:24]. Note! Multiple bits of rx_data_sof can be asserted in the same cycle, depending on the bytes per frame (e.g., F = 1, rx_data_sof = 1111).

  • Page 21: Interface Timing

    3 Functional Description 3.4 Interface Timing Signal Name Description the core Lane PCS RX clock; if it is multilane, gt_pcs_rx_clk_o the first lane PCS RX clock is output by default. Lane RX PMA layer lock indication, gt_pma_rx_lock_o[N -1:0] 1: lock. gt_rx_k_lock_o[N -1:0] Lane Comma lock indication, 1: lock.

  • Page 22: Rx Core Interface

    Data Interface Timing Figure 3-8 F=2 K=32, RX Data Interface Timing 3.5 Register Description Gowin JESD204B IP contains TX and RX cores registers, and is configured through bus interface with addresses in octets. Table 3-3 Gowin JESD204B IP Registers RX CORE REGISTER...

  • Page 23: Table 3-4 Version [Offset:0X004]

    3 Functional Description 3.5 Register Description RX CORE REGISTER TX CORE REGISTER 0x02C Alarm Status Alarm Status 0x030 RXBUF_DELAY Reserved 0x034 ERR_REPORT Reserved 0x038 LINK_DEBUG Reserved 0x040 CLEAR_ERR Reserved 0x080 Reserved Lane ID Lane0 0x084 Reserved Lane ID Lane1 0x088 Reserved Lane ID Lane2 0x08C...

  • Page 24: Table 3-5 Reset [Offset:0X008]

    3 Functional Description 3.5 Register Description Default Description 15:8 Version: Minor Version: Revision Table 3-5 Reset [Offset:0x008] Default Description 31:1 Reserved Reset Write 1 to hold the reset Write 0 to release the reset and the core starts to run. Table 3-6 ILA Support [Offset:0x00C] Default Description...

  • Page 25: Table 3-9 Test Modes [Offset:0X018]

    3 Functional Description 3.5 Register Description Default Description 1111: 15 core_clk clock cycles delay 0000: 0 core_clk clock cycle delay Reserved SYSREF Always 1: Re-aligns LMFC counter on all SYSREFs 0: Only aligns LMFC counter on the first SYSREF detected following reset, and ignores subsequent SYSREFs.

  • Page 26: Table 3-12 Sync Status [Offset:0X024]

    3 Functional Description 3.5 Register Description Table 3-12 Sync Status [Offset:0x024] Default Description 31:5 Reserved SYSREF Captured (Subclass 1 Only) 1: SYSREF captured 0: SYSREF not captured Reserved SYNC Status 1: Link SYNC completed 1: Link SYNC not completed Table 3-13 Link Error Status (Lines 0 to 7) [Offset:0x028] Default Description 31:24...

  • Page 27: Table 3-15 Rxbuf_Delay (Rx Only) [Offset:0X030]

    3 Functional Description 3.5 Register Description Default Description 1: SYSREF misaligned to LMFC Reserved RxBufOvrflow_alm 1: RX lane alignment buffer overflow Table 3-15 RXBUF_DELAY (RX ONLY) [Offset:0x030] Default Description 31:10 Reserved RX buffer latency can be programmed in conjunction with the RX Buffer Adjust values read from the lanes to minimize overall RX latency.

  • Page 28: Table 3-18 Err_Clear [Offset:0X040]

    Table 3-20 ILA Config Data 0 [Offset: lane0-0x0C0, lane1-0x100 …… lane3-0x180] Default Description 31:7 Reserved JESD204 version 000: JESD204A 001:JESD204B Reserved Subclass: 000- Subclass 0 001- Subclass 1 010- Subclass 2 Note! This is a register that is included per lane (RX core only).

  • Page 29: Table 3-23 Ila Config Data 3 [Offset: Lane0-0X0Cc, Lane1-0X10C

    3 Functional Description 3.5 Register Description Table 3-23 ILA Config Data 3 [Offset: lane0-0x0CC, lane1-0x10C …… lane3-0x18C] Default Description 31:22 Reserved 21:17 R(RX) L (Lanes per Link), binary value. 16:12 R(RX) LID (Lane ID), binary value BID (bank ID), binary value. For TX core, set the field to be transmitted in R(RX) 11:8...

  • Page 30: Table 3-26 Ila Config Data 6 [Offset: Lane0-0X0D8, Lane1-0X118

    3 Functional Description 3.5 Register Description Default Description For RX core, capture the field from the ILA sequence per lane. 11:9 Reserved S (Samples per Converter per Frame). Binary value minus 1 R(RX) For TX core, set the field to be transmitted in WR(TX) the ILA sequence for all lanes.

  • Page 31: Table 3-28 Test Mode Error Count [Offset: Lane0-0X0E0, Lane1-0X120

    3 Functional Description 3.5 Register Description Default Description Reserved PHADJ (Phase Adjust Request) [Subclass 2 Only]. Binary value R(RX) For TX core, set the field to be transmitted in the ILA sequence for all lanes. WR(TX) For RX core, capture the field from the ILA sequence per lane.

  • Page 32: Table 3-31 Test Mode Multiframe Count [Offset: Lane0-0X0Ec, Lane1-0X12C . Lane3-0X1Ac]

    3 Functional Description 3.5 Register Description Table 3-31 Test Mode Multiframe Count [Offset: lane0-0x0EC, lane1-0x12C . lane3-0x1AC] Default Description Test Mode Multiframe Count 31:0 Count the total ILA multiframe received when Test Mode = 010 (Continuous ILA). Note! This is a register that is included per lane. Table 3-32 Buffer Adjust [Offset: lane0-0x0F0, lane1-0x130 ……...

  • Page 33: Design Considerations

    4.9152 Gbs, the core clock frequency is 122.88 MHz. The RX and TX data interfaces operates at this core clock frequency. This clock will be connected not only to the JESD204B core, but also to the internal SerDes PCS clock interface.

  • Page 34: Serdes Pcs Clock

    4.3 Reset 4.2.4 SerDes PCS Clock The JESD204B core outputs the SerDes lane PCS RX clock; if it is multilane, the first lane PCS RX clock is output by default. This clock frequency is the same as the core clock. It is also possible to connect the gt_pcs_tx_clk_o or gt_pcs_rx_clk_o pin to the core_clock port to use as the core clock.

  • Page 35: Reset Core Logic Via Registers

    The registers are not affected by this operation. Its function is the same as the reset via pin. 4.3.4 SerDes Related Reset The JESD204B core connecting to SerDes provides an interface for PMA and PCS resets, and the gt_fabric_rstn_i pin is active for both transceiver PMA.

  • Page 36: Sysref

    4.5 SYSREF 4.5 SYSREF 4.5.1 SYSREF Timing When JESD204B is used in Subclass 1, the SYSREF signal is the master timing reference for the system. To achieve accurate deterministic latency, the SYSREF signal and the core clock must be captured synchronously.

  • Page 37: Sysref On Link Resynchronization

    4 Design Considerations 4.5 SYSREF The system must ensure that the SYSREF for the JESD204B core is generated after the core completes its reset. This is especially important if the system is running One-shot SYSREF. 4.5.4 SYSREF on Link Resynchronization...

  • Page 38: Minimum Deterministic Latency Support

    8. The reset of the JESD204B RX core and the full link resynchronization cycle must occur before the modified latency setting takes effect. The following figure shows an example of the minimum latency.

  • Page 39: Link Test Mode

    4.7.4 RPAT This mode transmits a continuous random sequence. This mode is generated by the RPAT module and must be selected in Gowin IDE and will take up additional resources. You need to set TX core register 0x18 to 0x4 to enable this mode.

  • Page 40: Data Interface

    4.9 Data Interface The DATA Stream TX and RX interfaces are used to pass JESD204B formatted data to and from the core. The data input and output by the core...

  • Page 41: Interface Configuration

    Interface Configuration Find SerDes IP in the IP library, click SerDes IP and Figure 5-1 pops up. Select "JESD204B" in the protocol box, then click "Create" button, and the interface configuration of JESD204B IP pops up. Figure 5-1 Open SerDes IP Gowin JESD204B IP configuration interface is shown in Figure 5-2.

  • Page 42: Figure 5-2 Gowin Jesd204B Ip Configuration Interface 1

    5 Interface Configuration Figure 5-2 Gowin JESD204B IP Configuration Interface 1  Core Mode: You can select "Receive", "Transmit", and "Both Receive And Transmit".  Number of Lanes: Indicates the number of lanes in the core with value of 1-4.

  • Page 43: Figure 5-3 Gowin Jesd204B Ip Configuration Interface 2

     Config Clock Frequency: Sets the clock frequency of the configuration bus, and the frequency range can be from 1MHz to 100MHz. Figure 5-3 Gowin JESD204B IP Configuration Interface 2  Line Rate: Lane line rate  Reference_Clock_Source: Reference clock source; you can select clock source 0 and 1, which is related to the pin connection.

  • Page 44: Figure 5-4 Jesd204B: Jesd204B_Top

    5 Interface Configuration  JESD204B LaneX connect with: This option is used to set the lane correspondence between JESD204B and SerDes. Currently only 4 lanes are supported. After the parameters are configured, click "OK"; SerDes interface shows the configured protocols and lane locations, as well as the use of PLL.

  • Page 45: Reference Design

    Gowinsemi website. 6.1 Applications The JESD204B is mainly used to connect logic devices to ADCs or DACs. The following diagram describes how the FPGA connects to ADCs or DACs through four lanes using JESD204B interface.

  • Page 46: Reference Design

    6 Reference Design 6.2 Reference Design 6.2 Reference Design This chapter is intended to introduce the example and using of Gowin JESD204B IP reference design. 6.2.1 Hardware Platforms Figure 6-3 Platforms Diagram o_rx_syn i_tx_sync led1~4 i_sysref FPGA JESD204B 50MHz 100MHz...

  • Page 47: Implementation Diagram

    The UART_BUS_Top module does the necessary parsing of the custom bus protocol into the APB interface, and mounts APB1 to manage the global parameters, APB2 to manage the JESD204B TX CORE, and APB3 to manage the JESD204B RX CORE respectively.

  • Page 48: Bus Protocol And Address

    SerDes RX PCS reset Used to verify that the serial 0x12 to bus module works 0: Operating properly. 1: Reset JESD204B TX core reset Used to verify that the serial 0x13 to bus module works 0: Reset properly. 1: Operating...

  • Page 49: On-Board Testing

    6 Reference Design 6.3 On-Board Testing Offset address Default Description tx_sync. Test Data Used to verify that the serial 0x16 to bus module works 0: Transmits 0 properly. 1: Transmits DDS 32'h202 0x8A Development Date 30406 32'h000 0x8B Development Version 00041 [0]: TX CORE sync indication –...
  • Page 50 6 Reference Design 6.3 On-Board Testing the serial instruction works. Enter R 008A Return G 008A 20230406 Then the communication between PC and FPGA is OK, otherwise, you have to check the reason why they can't communicate first before proceeding to the next step. 2.

  • Page 51: Figure 6-5 Capture Dds Data

    6 Reference Design 6.3 On-Board Testing Send instructions R 0090, R 0091 If the feedback instructions G 0090 00000003 G 0091 00000003 The return values are 3, which means that both TX and RX have been successfully linked. At this time, if all four indicators are on, it also means that both TX and RX have been successfully linked.

  • Page 52: File Delivery

    7.2 Design Source Code (Encryption) The encrypted code file contains Gowin JESD204B IP RTL encrypted code which is used for GUI in order to cooperate with Gowin Software to generate the IP core required by users. Table 7-2 Design Source Code List of Gowin JESD204B IP...
  • Page 53 7 File Delivery 7.3 Reference Design Name Description Cos_sin_table.v Sine and cosine table generation module sysreg.v SysReg generation module Gowin_pll.v PLL IP file IPUG1019-1.0E 45(45)

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