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I.
GENERAL DESCRIPTION
The EM78P451 is an 8-bit microprocessor with low-power and high-speed CMOS technology. Its operation kernel
is implemented by RISC-like architecture. The one time programmable(OTP) version is flexible no matter on mass
production or engineering test. Users can get any volume with a favorable price. This device is equiped with the
function of Serial Peripheral Interface (SPI) and easy-implemented RS-232. These are very suitable for the wire
communication. Only 57 instructions need learn. This product is supported by EMC in-circuit emulator, macro assembler
and Easy C Compiler.
II.
FEATURES
• Operating voltage range: 2.2V~5.5V.
• Available in temperature range: 0°C~70°C.
• Operating frequency range:
Crystal mode: DC~20MHz at 5V, and DC~8MHz at 3V.
RC mode: DC~4MHz at 5V, and DC~4MHz at 3V.
• Serial Peripheral Interface (SPI) available.
• 4K x 13 bits on chip ROM (EM78P451).
• 11 special function registers.
• 140 x 8 bits general-purpose registers (SRAM).
• 5 bi-directional I/O ports (35 I/O pins).
• 3 LED direct sinking pins with internal serial resistors.
• Built-in RC oscillator.
• Built-in power-on reset.
• Five stacks for subroutine and interrupt.
• 8-bit real time clock/counter (TCC) with the overflow interrupt.
• Two machine clocks or four machine clocks per instruction cycle.
• Power-down mode.
• Programmable wake-up from sleep circuit on I/O ports.
• Programmable free running on-chip watchdog timer.
• 12 wake-up pins.
• Two open-drain pins.
• Two R-option pins.
• Package :
(1) 40 pin DIP : EM78P451P.
(3) 42 pin SHRINK : EM78P451R
• Reloadable counter available.
• Four types of interrupts.
1. Pin changed (/INT).
2. SPI completed.
3. TCC over flow.
4. Reloadable counter match.
* This specification is subject to be changed without notice.
(2) 40 pin SOP : EM78P451M.
(4) 44 pin QFP : EM78P451AQ.
1
EM78P451
7.23.2001
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Summary of Contents for EMC EM78P451
- Page 1 EM78P451 GENERAL DESCRIPTION The EM78P451 is an 8-bit microprocessor with low-power and high-speed CMOS technology. Its operation kernel is implemented by RISC-like architecture. The one time programmable(OTP) version is flexible no matter on mass production or engineering test. Users can get any volume with a favorable price. This device is equiped with the function of Serial Peripheral Interface (SPI) and easy-implemented RS-232.
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Page 2: Pin Assignments
EM78P451 III. PIN ASSIGNMENTS Fig. 1 Pin assignments FUNCTIONAL BLOCK DIAGRAM Fig. 2 Functional block diagram PIN DESCRIPTION Table 1 Pin description-EM78P451 Symbol Type Function Description R-OSCI In XTAL mode: Crystal input; In RC mode: 56 Kohm±5% pull-high to generate 1.8432MHz. -
Page 3: Function Description
EM78P451 Symbol Type Function Description P70~P72 LED direct-driving pin with internal serial resistor as used to be output. Defined in software. By connecting P74 and P76 together. P74 can be pulled high in software. P76 can be defined as an open-drain output. - Page 4 • In the case of EM78P451, the two most significant bits (A10 and A11) will be loaded with the contents of bits PS0~PS1 in the status register (R3) upon the execution of a "JMP", "CALL", or any instructions which would change the contents of R2.
- Page 5 EM78P451 • Bit 0 (C) Carry flag • Bit 1 (DC) Auxiliary carry flag • Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. • Bit 3 (P) Power-down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP"...
- Page 6 EM78P451 10. R3F (Interrupt Status Register) TM1IF RBFIF EXIF TCIF • Bit 0 (TCIF) TCC overflowing interrupt flag. Set as TCC overflows, reset by software. • Bit 1 (EXIF) External interrupt flag. Set by falling edge on the /INT pin, reset by software.
- Page 7 EM78P451 VI.2 Special Purpose Registers 1. A (Accumulator) • Internal data transfer, or instruction operand holding. • A non-addressable register. 2. CONT (Control Register) /PHEN /INT PSR2 PSR1 PSR0 • Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
- Page 8 EM78P451 • Only the lower 6 bits of the IOC9 register are used. 4. IOCD (Pull-high Control Register) /PU9 /PU8 /PU6 /PU5 • The default values of /PU5, /PU6, /PU8, and /PU9 are “1” which means the pull-high function is disabled.
- Page 9 EM78P451 • Bit 6 (ODE) Open-drain control bit. 0: Both P76 and P77 are normally I/O pins. 1: Both P76 and P77 pins have the open-drain function inside. The ODE bit can be read and written. • Bits 1~2 and 7 Not used.
- Page 10 EM78P451 VI.3 TCC/WDT Presacler There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available only for either the TCC or the WDT at the same time and the PAB bit of the CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the prescaler ratio.
- Page 11 EM78P451 Fig. 7 The circuit of I/O port and I/O control register Fig. 8 Block diagram of Reset of controller VI.5 SERIAL PERIPHERAL INTERFACE MODE 1. Overview & Features Overview: * This specification is subject to be changed without notice.
- Page 12 SCK pin. A couple of 8-bit data are transmitted and received at the same time. If EM78P451, however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted on a basis of both the clock rate and the selected edge.
- Page 13 EM78P451 EM78P451 EM78P451 Master 2 Master 1 Slave 6 Slave 1 Slave 2 for master 1 Slave 3 for Master 1/2 Slave 4 for Master 1/2 Slave 5 for Master 2 Fig. 11 The SPI configuration of Single-mater and Multi-slave 2.
- Page 14 EM78P451 • Edge Select: Selecting the appropriate clock edges by programming the ES bit. 3. Signal & Pin Description The four pins, SDI, SDO, SCK, and /SS, which are shown in Fig. 12, will be explained in detail as follows: SDI/P92 (Pin 7): •...
- Page 15 EM78P451 Table 2 Related control registers of the SPI mode Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0D *SPIC/RD ES/0 SPIE/0 SRO/0 SPISE/0 SBR2/0 SBR1/0 SBR0/0 0x0F INTC/IOCF T1IE/0...
- Page 16 The edge of SCK is selected by programming bit, CES. The waveform shown in Fig. 12 can be used no matter EM78P451 is either in a master mode or in a slave mode with /SS disabled. However, the waveform in Fig. 13 can only be implemented in a slave mode with /SS enabled.
- Page 17 EM78P451 Fig. 13 SPI Mode with /SS enabled 6. Software Application of SPI Example of SPI ;Define RAM == 0 ;Indirect Addressing Register == 3 ;Status Register == 4 ;RAM Select Register == 9 ;Port 9 SPIRB == 0XA ;SPI Read Buffer SPIWB == 0XB ;SPI Write Buffer...
- Page 18 EM78P451 ;Define pin C_WDT ==0XD ;Enable Watchdog Timer<bit 4> ;Port9<bit 5> ORG 0x02 INT_VECT: ;The initial address of interrupt subroutine I_A,A ;Save Acc SWAP ;No status flags effected SWAPA ;Save PSW, and no status flags effected as well I_PSW, A P9,5 ;SPI disabled by setting //SS(port9<bit 5>) to 1...
- Page 19 EM78P451 BS P9, 5 ; SPI disabled by setting /SS(port9<bit 5>) to 1 ; Enable the interrupt function (User Program) DISI ; In the SLAVE mode, trying to keep the RUN bit to 1 as possible. JBC SPIC, RUN ; Check if RUN==0 JMP START TO RUN;...
- Page 20 EM78P451 Fig. 14 TIMER1 block diagram OSC/4: Input clock. Prescaler: Option of 1:1, 1:4, 1:8, or 1:16 defined by T1CLK1 and T1CLK2(T1CON<1, 0>). It is cleared while a value is written to TMR1, T1CON or any kind of reset. PWP: Pulse width preset register;...
- Page 21 (wake-up). In addition to the basic SLEEP1 MODE, EM78P451 has another sleep mode (caused by clearing "SLPC" bit of IOCE register, named as SLEEP2 MODE). In the SLEEP2 MODE, the controller can be awakened by (a) input triggered, refer to Fig.15.
- Page 22 EM78P451 The flag in the Interrupt Status Register (R3F) is set regardless of the status of its mask bit or the execution of ENI instruction. Note that reading R3F will get the output of logic AND of R3F and IOCF. Refer to Fig. 15.
- Page 23 EM78P451 Table 9 The list of the instruction set of EM78P451 INSTRUCTION STATUS BINARY MNEMONIC OPERATION AFFECTED 0 0000 0000 0000 0000 No Operation None 0 0000 0000 0001 0001 Decimal Adjust A 0 0000 0000 0010 0002 CONTW A→CONT...
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Page 24: Absolute Maximum Ratings
EM78P451 INSTRUCTION STATUS BINARY MNEMONIC OPERATION AFFECTED 0 0111 00rr rrrr 07rr SWAPA R R(0-3)→A(4-7) R(4-7)→A(0-3) None 0 0111 01rr rrrr 07rr SWAP R R(0-3)↔R(4-7) None 0 0111 10rr rrrr 07rr JZA R R+1→A, skip if zero None 0 0111 11rr rrrr... -
Page 25: Ac Electrical Characteristic
Ta = 25°C Tdrh Device reset hold period Ta = 25°C Note : N* = selected prescaler ratio. X. Application Software (SPI transceiver) #This demostration program was witten in EMC++. #EM45 ;DEFINE CPU RAM == 0 ;DEFINE BIT == 1 #DEFINE B_KEY R_BIT.0... - Page 26 EM78P451 SPIC == 0XD TMR1 == 0XE ;DEFINE PROT == 0XF #DEFINE P_START P9.0 R_3F == 0X3F #DEFINE P_MS_SEL P9.1 #DEFINE P_SPI_SS P9.5 R_ACC == 0X10 R_ACC2 == 0X11 ORG 0 R_ACC3 == 0X12 == 0X13 MAIN() I_PSW == 0X14...
- Page 27 EM78P451 RETI D7=1 R_0=0 D6=0 R_0=0 MAIN() D7=0 WHILE++RSR!=0X40 DISI RSR=0 P5=0 P_SPI_SS=1 !P5=0 P6=0 !P6=0XFF P7=0 LOOP: !P7=0 WDTC P8=0 !P8=0 P9=0 IF P_MS_SEL==0 IF P_MS_SEL SPIWB=R_CODE !P9=0B00000111 DISI SPIC=0B01000100 IF SPI_RUN==0 ELSE IF P_SPI_SS==0 !P9=0B00100111 R_CODE++ SPIC=0B01000101 ENDIF * This specification is subject to be changed without notice.
- Page 28 EM78P451 SPI_RUN=1 ENDIF ENDIF ENDIF IF P_START==0 IF B_KEY==0 B_KEY=1 IF SPI_RUN==0 P_SPI_SS=0 SPIWB=0xAA FOR R_ACC=1,R_ACC!=0,R_ACC++ NEXT SPI_RUN=1 ENDIF ENDIF ELSE B_KEY=0 ENDIF GOTO LOOP ORG 0XFFF JMP MAIN * This specification is subject to be changed without notice. 7.23.2001...
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Page 29: Timing Diagrams
EM78P451 XI. TIMING DIAGRAMS * This specification is subject to be changed without notice. 7.23.2001... - Page 30 EM78P451 * This specification is subject to be changed without notice. 7.23.2001...
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Page 31: Application Circuit
EM78P451 XII. APPLICATION CIRCUIT * This specification is subject to be changed without notice. 7.23.2001...
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