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Audio Precision PSIA-2722 User Manual

Programmable serial interface adapter
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Summary of Contents for Audio Precision PSIA-2722

  • Page 3 PSIA-2722 User’s Manual Installation and Operation of the Audio Precision Programmable Serial Interface Adapter...
  • Page 4 Audio Precision®, System One®, System Two™, System Two Cascade™, System One + DSP™, System Two + DSP™, Dual Domain®, FASTTEST®, APWIN™, 2700 Series, AP2700, ATS™...

  • Page 5: Table Of Contents

    ......5 PSIA-2722 Components ......6 Power Supply .
  • Page 6 PSIA Receiver: Frame, Bit & Master Clock OUT ... . . 37 PSIA Receiver: Frame & Bit Clock OUT, Master Clock IN ..37 PSIA-2722 User’s Manual...
  • Page 7 N*Fs Table ....... . . 42 Using INTERVU with PSIA-2722 ..... . 42...
  • Page 8 PSIA-2722 User’s Manual...

  • Page 9: Safety Information

    PSIA-2722 contain user-replaceable fuses. Use only the AP power supply PN 4540.0020 or PN 4540.0051 with the PSIA-2722. The use of other power supplies may result in damage to the PSIA-2722, electrical shock hazard from the power supply or the PSIA-2722, and loss of fire hazard protection.

  • Page 10: Safety Symbols

    PROTECTIVE EARTH TERMINAL—This symbol marks a terminal that is bonded to conductive parts of the instrument. Confirm that this terminal is connected to an external protective earthing system. PSIA-2722 User’s Manual...

  • Page 11: Chapter 1 Introduction

    2322, with a key difference: the PSIA-2722 is software controlled. Where con- figuring the SIA-2322 involved the manual setting of a number of DIP switches for each test setup, PSIA-2722 is configured from the PSIA panel in the instrument control software. The setting of master clock rate, N*Fs clock rate, bit rate, number of channels, word length and sample rate is more intu- itive and is aided by automatic calculations.

  • Page 12: Capabilities

    The instrument parallel digital output and input provide data connections for the PSIA; additional cables connect the instrument master clock and the APIB control bus to the PSIA-2722. The PSIA is powered by a separate 5 VDC power supply. The PSIA provides all necessary serial input, output and clock ports for de- vice connection, as well as provision for oscilloscope monitoring of the vari- ous signals.

  • Page 13: Data Settings

    Voltage levels PSIA clock and data ports can be set to interface with common logic fami- lies: 5.0 V TTL § 3.3 V TTL § 3.3 V CMOS § 2.4 V CMOS § 1.8 V CMOS § PSIA-2722 User’s Manual...

  • Page 14: Documentation

    Chapter 1: Introduction Documentation Documentation This PSIA-2722 User’s Manual is the primary document for the PSIA. Con- verter testing also requires a good understanding of many of the functions of the Audio Precision instrument; these are covered in detail in the instrument’s User’s Manual.

  • Page 15: Installation And Setup

    Installation and Setup Figure 2. PSIA-2722 and a System Two Cascade Plus. The PSIA-2722 is an accessory to Audio Precision’s System Two Cascade, Cascade Plus and 2700 Series digitally-capable instruments. Since the PSIA operations for all these systems are identical, in this manual the designation “instrument”...

  • Page 16: Psia-2722 Components

    These are used for connection to the DUT. This manual. § Power Supply Use only the power supply provided by Audio Precision (AP part number 4540.0020 or 4540.0051) for powering the PSIA. There is no user-replaceable fuse for either power supply. PN 4540.0020 The PN 4540.0020 DC power supply accommodates mains voltages from...

  • Page 17: Connecting The Psia To The Instrument

    Connecting the PSIA to the instrument Chapter 2: Installation and Setup mains power cord is functioning properly. If the ON indicator still does not light, contact Audio Precision for a replacement supply. PN 4540.0051 The PN 4540.0051 DC power supply accommodates mains voltages from 100 VAC to 240 VAC and mains frequencies from 50 Hz to 60 Hz.
  • Page 18 If you connect the PSIA to the instrument after the control software has been launched, choose Utilities > Restore Hardware to enable the software to recognize the presence of the PSIA. All four instrument-to-PSIA cables must be connected for the PSIA to operate properly. PSIA-2722 User’s Manual...

  • Page 19: Chapter 3 Converter Testing

    Chapter 3 Converter Testing Figure 4. PSIA-2722 with Audio Precision instrument and coverter test fixture. PSIA-2722 is designed to enable testing of audio analog-to-digital convert- ers (ADCs), digital-to-analog converters (DACs) and other digital devices that have data or clock characteristics that are not compatible with the AES3 / IEC60958 (also called AES/EBU and SPDIF) digital serial interface standards.

  • Page 20: Relationship Between Psia And The Instrument

    Precision instrument and the PSIA-2722, including connection diagrams and PSIA software panel operation. Examples of actual converter setups are detailed on the Audio Precision Web site. See Appendix B for more informa- tion about test configuration examples and sample files.

  • Page 21: Psia Transmitter And Receiver Connections

    Chapter 3: Converter Testing PSIA Transmitter and Receiver Connections Figure 6. The PSIA-2722 front panel. The PSIA-2722 communicates with the device under test through its front- panel Transmitter and Receiver ports. Use the six-cable harnesses provided to connect the PSIA transmitter or re- ceiver to the DUT.
  • Page 22 With the loop-back cables connected, re-set the PSIA controls for the § data configuration, clock rates and logic voltages required for testing your DUT. Run your test again to verify that the test is still compatible and properly configured for these new settings. PSIA-2722 User’s Manual...

  • Page 23: Connections For Adc Testing

    LOGIC FAMILY Use only 50 Ohm cables for all BNC connections Figure 7. ADC testing with the PSIA-2722. First, set the PSIA LOGIC VOLTAGE LEVEL (see page 33) to the correct voltage setting for the logic circuits in the ADC.

  • Page 24: Connections For Dac Testing

    LOGIC FAMILY Use only 50 Ohm cables for all BNC connections Figure 8. DAC testing with the PSIA-2722. First, set the PSIA LOGIC VOLTAGE LEVEL (see page 33) to the correct voltage setting for the logic circuits in the DAC.

  • Page 25: Connections For Src Testing

    FRAME CLK DATA MASTER CLK N*Fs CLK BIT CLK CHANNEL CLK FRAME CLK DATA 5 3.3 3.3 2.4 1.8 CMOS LOGIC FAMILY Use only 50 Ohm cables for all BNC connections Figure 9. SRC testing with the PSIA-2722. PSIA-2722 User’s Manual...
  • Page 26 For other combinations of sample rate, a second ex- ternal master clock must be used. Make your generator and analyzer settings compatible with the characteris- tics of your device. Apply power to the DUT. PSIA-2722 User’s Manual...

  • Page 27: The Transmitter And Receiver Panels

    Figure 11. The PSIA Receiver panel. Click on the PSIA Transmitter (green) or PSIA Receiver (red) buttons on the Toolbar, or choose Panels > PSIA Transmitter or Panels > PSIA Re- ceiver on the Main Menu to open the panels. PSIA-2722 User’s Manual...

  • Page 28: Transmitter And Receiver Settings

    “shift left” setting. For convenience, I S (see page 20) settings can me made with one click, and compatible settings can be copied from the Transmitter panel to the Re- ceiver panel using the Loop-Back button. PSIA-2722 User’s Manual...

  • Page 29: Duplicated Controls And Displays

    PSIA panels. Common settings made on one of these panels will be reflected on the others. The figures above and below highlight the duplicated settings and displays. Figure 13. Controls in common with PSIA Receiver and instrument DIO Input. PSIA-2722 User’s Manual...

  • Page 30: Channel Data Assignment

    Transmitter or Receiver panel. See page 33. One-click I S bus settings The PSIA I S button provides a one-click method to conform the Transmit- ter or Receiver settings to the Philips I S (Inter-IC Sound) standard. See Fig- ure 14. PSIA-2722 User’s Manual...

  • Page 31: Transmit Data Clock Edge

    Bit Clock rising edge Bit Clock Data synched to A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 Bit Clock falling edge Figure 16. Data sync relationship to Bit Clock edges. PSIA-2722 User’s Manual...

  • Page 32: Preemphasis (Transmitter Only)

    Ref entry field. Rate Ref enables you to specify a reference frequency by which to scale the embedded audio frequency before transmission. Audio fre- quency scaling for digital signals is discussed above and in the instrument User’s Manual. PSIA-2722 User’s Manual...

  • Page 33: Channel Data

    Bits per channel display The top line of this display shows the number of bits per channel, set below in the Clocks matrix. 32 bits per channel, for example, is shown as 0------->31, as in Figures 17 and 18. PSIA-2722 User’s Manual...

  • Page 34: Msb First: Transmitter

    On the Special: Walking Ones waveform panel, set Samples/Step to the same value as Fs. This will cause the bit to “walk” at a rate of one step per second. Figure 19. Walking One signal, moving right-to-left (MSB first) (red arrow added). PSIA-2722 User’s Manual...

  • Page 35: Data And Padding Controls

    If the leading (left) Pad field is set to fewer than the number of channel bits minus the number of audio bits, the necessary padding bits will be added after the audio bits, and the number of these bits will be displayed in the trailing Pad field. PSIA-2722 User’s Manual...

  • Page 36: Left And Right Justify: Transmitter

    The bits are labeled from the left from the most significant bit (MSB, or bit 24 of the word) to the least significant bit (LSB, or bit 1 of the word) on the right. The Data Bit indicators examine the signal in intervals of approximately 1/4 second. PSIA-2722 User’s Manual...

  • Page 37: The Clocks Control Matrix

    § The Clock controls Several fields enable you to control various aspects of the relationship of each clock with the other clocks. Because of their different functions, each clock signal has a different combination of controls available. PSIA-2722 User’s Manual...

  • Page 38: Direction

    Channel Clock transitions are aligned with the rising edge or the falling edge of the Bit Clock transitions. Frame Clock and Channel Clock edge sync can be set independently for Transmitter and Receiver. Invert Waveform (Frame, Channel and N*Fs Clocks) See Figure 20. PSIA-2722 User’s Manual...

  • Page 39: Shift One Bit Left (Frame Clock Only)

    Frame Clock B7 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 Data Shift One Bit Left Figure 21. Shift Frame Clock One Bit Left. See Figures 20 and 21. PSIA-2722 User’s Manual...

  • Page 40: Bit Wide Pulse (Frame Clock And Channel Clock)

    Figure 23. Channel Clock and Frame Clock Normal Pulse width and Bit-Wide Pulse. PSIA Clock Rate and Factor Settings See Figure 20. PSIA can transmit and receive a number of clock rates. Depending upon configuration, these rates can be set or influenced by user entry, instrument PSIA-2722 User’s Manual...

  • Page 41: Frame Clock (Fs) Rate Setting

    Bit Clock direction. Channels per Frame See Figure 20. You must specify the number of channels per frame for each PSIA con- verter test. The valid entry range for the channels field in the PSIA is 1 to 256. PSIA-2722 User’s Manual...

  • Page 42: Setting The Bits Per Channel

    1 to 256. If you specify a value for N that cannot be achieved with an integer divider in this range, the PSIA will show an invalid clock frequency for N*Fs, indicated by a dashed line “--------Hz”. PSIA-2722 User’s Manual...

  • Page 43: M, The Master Clock Multiplier

    Fs and bits / channel and channels factors. These displays are accurate if the master clock (or bit clock, if PSIA is slaved to a bit clock) frequency is accurate and the user settings are correct. PSIA-2722 User’s Manual...

  • Page 44: Logic Voltage Controls

    Logic Voltage controls Figure 24. The PSIA Logic Voltage controls. The PSIA-2722 can accommodate TTL logic at 5 V and 3.3 V voltage lev- els, and CMOS logic at 3.3 V, 2.4 V and 1.8 V voltage levels. For circuit protection, tests are loaded with the output voltages OFF. When output voltages are ON, a user selection of a higher voltage resets the output voltages to OFF.
  • Page 45 For ADC testing, only the PSIA Receiver panel is necessary. You may § close the Transmitter panel. For DAC testing, only the PSIA Transmitter panel is necessary. You may close the Receiver panel. Apply power to the DUT and begin your testing PSIA-2722 User’s Manual...

  • Page 46: Common Converter Testing Configurations

    PSIA. Frame clock rate (Fs) field is a nominal entry for calculation purposes. § Nominal Fs should be master clock ÷ M. PSIA-2722 User’s Manual...

  • Page 47: Psia Receiver: Frame, Bit & Master Clock Out

    Figure 28. Receiver: Frame and Bit Clock OUT, Master Clock IN. In this configuration the PSIA is the slave, with either the DUT or an exter- nal device providing the master clock, from which the other clocks are derived and output by the PSIA. PSIA-2722 User’s Manual...
  • Page 48 Master clock multiplier field (M) is available for numerical entry. § Actual Fs = master clock ÷ M. § ´ ´ Bit clock rate = Fs channels bits § Master clock rate is determined by external settings. § PSIA-2722 User’s Manual...

  • Page 49: Appendix A Miscellany

    = number of bits (as entered in factor field). § DUT = device under test: an ADC, DAC, etc. § ADC = analog to digital converter. § DAC = digital to analog converter. § SRC = sample rate converter. § PSIA-2722 User’s Manual...

  • Page 50: Oscilloscope Examples

    Storage Oscilloscope, triggered on the Frame Clock. Figure 29. Master clock, bit clock, frame clock, 48 kHz Fs, 32- bit word, 16-bit data, right justified. Figure 30. Master clock, bit clock, frame clock, 48 kHz Fs, 32- bit word, 24-bit data, left justified. PSIA-2722 User’s Manual...
  • Page 51 24-bit data, left justified, I S (shift one bit left). Figure 33. Master clock, bit clock, frame clock, 48 kHz Fs, 32- bit word, 24-bit data, walking-one data moving right-to-left (MSB first) (red arrow added). PSIA-2722 User’s Manual...

  • Page 52: N*Fs Table

    The table below shows the master clock frequencies (N*Fs) for a variety of combinations of sample rates (Fs) and multipliers (N). Shaded cells indicate frequencies that are compatible with PSIA-2722 operation but must be pro- vided by an external clock.

  • Page 53: Configuration Examples And Files

    Configuration Examples and Files Eval boards and sample files The Audio Precision technical support staff have evaluated a number of converters using the PSIA, and their recommendations for PSIA configuration are available on the Audio Precision Web site at audioprecision.com. Browse to Products: Measurement Instruments: PSIA-2722: Device Connectivity.
  • Page 54 Appendix B: Configuration Examples and Files Eval boards and sample files Figure 34. Typical converter evaluation board Web page, this one being for the AK4393. Links lead to manufacturer documentation. PSIA-2722 User’s Manual...

  • Page 55: Appendix C Connection Guidelines

    It is useful to view the clock and data waveforms simultaneously on a multi- channel oscilloscope while configuring and testing the PSIA. A four-channel scope is optimal, displaying Bit Clock, Channel Clock, § Frame Clock and Data. Alternatively, a two-channel scope is sufficient, displaying Frame Clock § and Data. PSIA-2722 User’s Manual...

  • Page 56: Triggering

    Trigger from the Frame Clock channel. Oscilloscope Connections The PSIA-2722 provides oscilloscope probe pick-off jacks for monitoring the clock and data ports. A 2.5 mm probe jack is located adjacent to the BNC connector for each port. These jacks are intended to interface directly with any...

  • Page 57: Appendix D Specifications

    Impedance (W) Tx Master Clock >10 k 5.5 V Tx NFs Clock Tx Bit Clock >10 k 5.5 V Tx Channel Clock Tx Frame Clock 30 k 5.5 V Tx Data Rx Master Clock 30 k 5.5 V PSIA-2722 User’s Manual...

  • Page 58: Ac Characteristics

    Bit Clock IN 15 ns Bit Clock OUT 15 ns Note 1: The Bit Clock is synchronous with the Master Clock Out, but does not have a guaranteed phase relationship. Table 4. Output latency, Clock to Out PSIA-2722 User’s Manual...

  • Page 59: Setup And Hold, Inputs

    Maximum APIB bus configuration with PSIA: 1 instrument (2700 Series or System Two Cascade Plus) § 1 PSIA-2722 § 16 Audio Precision switchers § 1 DCX-127 § a total of 33' (10 m) of APIB cable (not including the 1' [.3 m] patches.
  • Page 60 Appendix D: Specifications APIB PSIA-2722 User’s Manual...

  • Page 61: Ap Basic Extensions For Psia

    In output (master) mode, the master clock is provided by the PSIA. See Also AP.PSIA.Rx.MasterClk.Factor, AP.PSIA.Rx.BitClkDir, AP.PSIA.Rx.FrameClkDir Example Sub Main AP.S2CDio.OutFormat = 3 ' PSIA output AP.PSIA.MasterClkDir = 1 ' Tx out, Rx in AP.PSIA.OutputsOn = True ' Outputs on PSIA-2722 User’s Manual...
  • Page 62 This command turns the PSIA outputs on or off. When the outputs are Description off, they are tri-stated. When the outputs are on, they are driven according to the voltage setting. See Also AP.PSIA.VoltageSetting See AP.PSIA.MasterClkDir. Example Property AP.PSIA.Rx.BitClk.Dir AP.PSIA.Tx.BitClk.Dir Syntax AP.PSIA.Rx.BitClk.Dir AP.PSIA.Tx.BitClk.Dir PSIA-2722 User’s Manual...
  • Page 63 (for Tx) or the digital input resolution field (for Rx). The maximum number of bits per channel is 32. See Also AP.PSIA.Rx.BitClk.Dir, AP.S2CDio.InResolution, AP.S2CDio.OutResolution Example See AP.PSIA.Rx.BitClk.Dir. PSIA-2722 User’s Manual...
  • Page 64 ' 50% duty cycle AP.PSIA.Tx.ChannelClk.EdgeSync = 0 ' assert on rising edge AP.PSIA.Tx.ChannelClk.Factor = 2 ' 2 channels AP.PSIA.Tx.ChannelClk.InvWfm = True ' invert channelclk AP.PSIA.Tx.ChannelClk.BitWidePulse = False ' 50% duty cycle AP.PSIA.Rx.ChannelClk.EdgeSync = 1 ' latch on falling edge PSIA-2722 User’s Manual...
  • Page 65 For the receiver side (Rx), this command selects whether the channel clock input is latched at the rising or falling edge of the bit clock. See Also AP.PSIA.Rx.ChannelClk.BitWidePulse, AP.PSIA.Rx.ChannelClk.Dir, AP.PSIA.Rx.ChannelClk.InvWfm. Example See AP.PSIA.Rx.ChannelClk.BitWidePulse. PSIA-2722 User’s Manual...
  • Page 66 (non-inverted), the channel clock is high at the start of the subframe, and low for the rest of the subframe. When set to True (inverted), the channel clock is low at the start of the subframe, and high for the rest of the subframe. PSIA-2722 User’s Manual...
  • Page 67 AP.PSIA.Tx.Data.ChannelB Syntax AP.PSIA.Rx.Data.ChannelB AP.PSIA.Tx.Data.ChannelB A+1 to n–1, where A is the number of channels specified for Data Type Integer Channel A and n is one less than the number of channels specified by the associated ChannelClk.Factor command PSIA-2722 User’s Manual...
  • Page 68 See Also AP.PSIA.Rx.ChannelClk.EdgeSync, AP.PSIA.Rx.FrameClk.EdgeSync Example Sub Main AP.PSIA.Tx.ChannelClk.Factor = 4 ' 4 channels... AP.PSIA.Tx.BitClk.Factor = 32 ' ...of 32-bit data AP.PSIA.Tx.Data.EdgeSync = 0 ' assert on rising edge AP.PSIA.Tx.Data.ChannelA = 1 ' assign ChA data to channel 1 PSIA-2722 User’s Manual...
  • Page 69 ' channel 1 data -> ChB of analyzer AP.PSIA.Rx.Data.MsbFirst = True ' accept audio word MSB first ' Note: the following two lines are equivalent AP.PSIA.Rx.Data.Justify(apbRight) ' accept right-justified audio word AP.PSIA.Rx.Data.PadBits = AP.PSIA.Rx.BitClk.Factor - AP.S2CDio.InResolution End Sub PSIA-2722 User’s Manual...
  • Page 70 For the transmitter side (Tx), this command specifies whether audio data is sent Most Significant Bit (MSB) first or Least Significant Bit (LSB) first. For the receiver side (Rx), this command specifies whether audio data is accepted MSB first or LSB first. See Also AP.PSIA.Rx.Data.Justify PSIA-2722 User’s Manual...
  • Page 71 See Also AP.PSIA.Tx.Data.PostPadType, AP.PSIA.Tx.Data.PrePadType, AP.PSIA.Rx.BitClk.Factor, AP.S2CDio.InResolution, AP.S2CDio.OutResolution See AP.PSIA.Rx.Data.EdgeSync. Example Property AP.PSIA.Rx.FrameClk.BitWidePulse AP.PSIA.Tx.FrameClk.BitWidePulse Syntax AP.PSIA.Rx.FrameClk.BitWidePulse AP.PSIA.Tx.FrameClk.BitWidePulse Boolean Data Type Bit-wide pulse (one period of the bit clock) True Approximately 50% duty cycle False PSIA-2722 User’s Manual...
  • Page 72 ' shift one bit left AP.PSIA.Tx.FrameClk.BitWidePulse = False ' 50% duty cycle AP.PSIA.Tx.FrameClk.Rate("Hz") = 44100 ' CD sample rate AP.PSIA.Rx.FrameClk.Dir = 1 ' input AP.PSIA.Rx.FrameClk.EdgeSync = 1 ' latch on bitclk fall AP.PSIA.Rx.FrameClk.InvWfm = True ' inverted PSIA-2722 User’s Manual...
  • Page 73 PSIA. In input (slave) mode, the frame clock is provided by an external source. See Also AP.PSIA.Rx.FrameClk.BitWidePulse, AP.PSIA.Rx.FrameClk.EdgeSync, AP.PSIA.Rx.FrameClk.InvWfm, AP.PSIA.Rx.FrameClk.Rate, AP.PSIA.Rx.FrameClk.ShiftOneBitLeft See AP.PSIA.Rx.FrameClk.BitWidePulse. Example Property AP.PSIA.Rx.FrameClk.EdgeSync AP.PSIA.Tx.FrameClk.EdgeSync Syntax AP.PSIA.Rx.FrameClk.EdgeSync AP.PSIA.Tx.FrameClk.EdgeSync Data Type Integer Rising edge Falling edge PSIA-2722 User’s Manual...
  • Page 74 When set to True (inverted), the frame clock is low at the start of the frame, and high for the rest of the frame. See Also AP.PSIA.Rx.FrameClk.BitWidePulse, AP.PSIA.Rx.FrameClk.Dir, AP.PSIA.Rx.FrameClk.EdgeSync, AP.PSIA.Rx.FrameClk.Rate, AP.PSIA.Rx.FrameClk.ShiftOneBitLeft Example See AP.PSIA.Rx.FrameClk.BitWidePulse. PSIA-2722 User’s Manual...
  • Page 75 This command allows the frame clock to be asserted (when associated frame clock direction is OUT) or latched (when associated frame clock direction is IN) one bit time before the actual start of the frame. Typically, this is used in the I S bus standard. When PSIA-2722 User’s Manual...
  • Page 76 Philips I S (Inter-IC Sound) bus. See Also AP.PSIA.Rx.FrameClk.ShiftOneBitLeft Example Sub Main AP.PSIA.Tx.I2S ' I2S output format AP.PSIA.Tx.LoopBack ' copy settings to receiver End Sub Property AP.PSIA.Rx.MasterClk.Factor AP.PSIA.Tx.MasterClk.Factor Syntax AP.PSIA.Rx.MasterClk.Factor AP.PSIA.Tx.MasterClk.Factor Long 1 or more Data Type PSIA-2722 User’s Manual...
  • Page 77 Boolean Inverted N*Fs clock True Non-inverted N*Fs clock False Description This command sets the polarity of the N*Fs clock. When set to False (non-inverted), the N*Fs clock is high at the start of the frame, and low PSIA-2722 User’s Manual...
  • Page 78 See Also AP.PSIA.Rx.NFsClk.Factor Example See AP.PSIA.MasterClkDir. Property AP.PSIA.Tx.BitClk.Dir AP.PSIA.Rx.BitClk.Dir Property AP.PSIA.Tx.BitClk.Factor AP.PSIA.Rx.BitClk.Factor Property AP.PSIA.Tx.ChannelClk.BitWidePulse AP.PSIA.Rx.ChannelClk.BitWidePulse Property AP.PSIA.Tx.ChannelClk.EdgeSync AP.PSIA.Rx.ChannelClk.EdgeSync Property AP.PSIA.Tx.ChannelClk.Factor AP.PSIA.Rx.ChannelClk.Factor Property AP.PSIA.Tx.ChannelClk.InvWfm AP.PSIA.Rx.ChannelClk.InvWfm PSIA-2722 User’s Manual...
  • Page 79 Property AP.PSIA.Tx.Data.EdgeSync AP.PSIA.Rx.Data.EdgeSync Method AP.PSIA.Tx.Data.Justify AP.PSIA.Rx.Data.Justify Property AP.PSIA.Tx.Data.MSBFirst AP.PSIA.Rx.Data.MSBFirst Property AP.PSIA.Tx.Data.PadBits AP.PSIA.Rx.Data.PadBits Property AP.PSIA.Tx.Data.PostPadType Syntax AP.PSIA.Tx.Data.PostPadType Data Type Integer Low: Set post (trailing) padding bits to logical low High: Set post (trailing) padding bits to logical high PSIA-2722 User’s Manual...
  • Page 80 MSB is the sign bit. Therefore if the audio word is ordered MSB first, and AP.PSIA.Tx.Data.PrePadType = 2, then the audio word will be sign extended by the leading pad bits. See Also AP.PSIA.Tx.Data.PostPadType, AP.PSIA.Rx.Data.PadBits See AP.PSIA.Rx.Data.EdgeSync. Example PSIA-2722 User’s Manual...
  • Page 81 AP.PSIA.Tx.FrameClk.BitWidePulse Appendix E: AP Basic Extensions for PSIA Property AP.PSIA.Tx.FrameClk.BitWidePulse AP.PSIA.Rx.FrameClk.BitWidePulse Property AP.PSIA.Tx.FrameClk.Dir AP.PSIA.Rx.FrameClk.Dir Property AP.PSIA.Tx.FrameClk.EdgeSync AP.PSIA.Rx.FrameClk.EdgeSync Property AP.PSIA.Tx.FrameClk.InvWfm AP.PSIA.Rx.FrameClk.InvWfm Property AP.PSIA.Tx.FrameClk.Rate AP.PSIA.Rx.FrameClk.Rate Property AP.PSIA.Tx.FrameClk.ShiftOneBitLeft AP.PSIA.Rx.FrameClk.ShiftOneBitLeft Method AP.PSIA.Tx.I2S AP.PSIA.Rx.I2S PSIA-2722 User’s Manual...
  • Page 82 Transmitter bit clock ® receiver bit clock Transmitter frame clock ® receiver frame clock Transmitter data ® receiver data Example See AP.PSIA.Rx.I2S. Property AP.PSIA.Tx.MasterClk.Factor AP.PSIA.Rx.MasterClk.Factor Property AP.PSIA.Tx.NFsClk.Factor AP.PSIA.Rx.NFsClk.Factor Property AP.PSIA.Tx.NFsClk.InvWfm AP.PSIA.Rx.NFsClk.InvWfm Property AP.PSIA.VoltageSetting Syntax AP.PSIA.VoltageSetting Data Type Constant 1.8 V CMOS PSIA_1_8_CMOS PSIA-2722 User’s Manual...
  • Page 83 Description This command sets the input and output voltages according to the logic family and voltage supplied. Note: the outputs must be on for signal to appear at the PSIA outputs. See Also AP.PSIA.OutputsOn See AP.PSIA.MasterClkDir. Example PSIA-2722 User’s Manual...
  • Page 84 Appendix E: AP Basic Extensions for PSIA AP.PSIA.VoltageSetting PSIA-2722 User’s Manual...
  • Page 85 DAC......39 Left justify ..... . 26 PSIA-2722 User’s Manual...
  • Page 86 SIA-2322 comparison to PSIA-2722 ... . . 1 Loop back..... . 34 Slave mode .

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