Renesas VersaClock 6E Series Register Descriptions And Programming Manual
Renesas VersaClock 6E Series Register Descriptions And Programming Manual

Renesas VersaClock 6E Series Register Descriptions And Programming Manual

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Register Descriptions

The register descriptions section describes the behavior and function of the customer-programmable non-volatile-memory registers in the
VersaClock 6E family of clock generators.
Table 1. VersaClock 6E Family Products
Product
5P49V6965
5P49V6967
5P49V6968
5P49V6975
For details of product operation, refer to the product datasheet.

VersaClock 6E Family Register Set

The device contains volatile (RAM) 8-bit registers and non-volatile 8-bit registers
Programmable (OTP), and bit values can only be changed from 1 (unburned state) to 0.
The OTP registers include factory trim data and four user configuration tables
format or methods for programming factory trim data, which is programmed by the factory before shipment.
Each configuration table contains all the information to set up the device's output frequencies. When these configuration tables are
programmed, the device will automatically load the RAM registers with the desired configuration on power-up. The device initializes in
2
either I
C mode or selection-pin mode, depending on the state of the OUT0/SELB_I2C pin on power-up, and remains in the selected
mode until power is toggled
selection-pin mode, the SEL0 and SEL1 inputs are decoded to select one of the four configuration tables CFG0-CFG3.
The RAM registers
(Table
4) include Status registers for read-back of the device's operating conditions in I
Figure 1. Register Maps
©2017-2022 Renesas Electronics Corporation
VersaClock
Table 1
showcases the array of products under the VersaClock 6E family.
5-Output VersaClock 6E
8-Output VersaClock 6E with 4 LP-HCSL Outputs
12-Output VersaClock 6E with 8 LP-HCSL Outputs
5-Output VersaClock 6E with Internal Crystal
(Table
2). When powered up in I²C mode, the first configuration table, CFG0, is loaded. When powered up in
®
6E Family Register Descriptions
Description
(Figure
1). The non-volatile registers are One-Time
(Figure
1,
Table
1
and Programming Guide
Package
3). This document does not describe the
2
C mode.
24 pins
40 pins
48 pins
24 pins
July 1, 2022

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Summary of Contents for Renesas VersaClock 6E Series

  • Page 1: Register Descriptions

    SEL0 and SEL1 inputs are decoded to select one of the four configuration tables CFG0-CFG3. The RAM registers (Table 4) include Status registers for read-back of the device's operating conditions in I C mode. Figure 1. Register Maps ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 2: Table Of Contents

    Revision History ....................58 ©2017-2022 Renesas Electronics Corporation...
  • Page 3: User Configuration Table Selection

    User configuration settings bank 0. 0x06A–0x0C3 CFG1 User configuration settings bank 1. 0x0C4–0x11D CFG2 User configuration settings bank 2. 0x11E–0x177 CFG3 User configuration settings bank 3. 0x178–0x1AF Factory Use Factory settings–do not over-program. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 4: Versaclock 6E Family Power-Up Behavior

    OTP user configuration tables have been programmed. • Factory programmed product is typically shipped in this condition. Device has factory trim performed and with required customization written into OTP memory. Renesas programs user customization at factory test. Please visit our website for device customization request.
  • Page 5: Otp Programming

    Read register 0x9F: If bit D1 = 0, programming was successful. Test if OTP programming was successful. If bit D1 = 1, programming failed. Write register 0x9F = 0x00. Reset margin read status bit. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 6 • Reg Address (hex): 73 74 75 76 77 78 • Configuration 0: 00 4E 34 E1 00 00 3. Start Burn with Reg 0x72 set to F8. 4. Wait 500ms. 5. Reset Burn Start Bit 0x72 set to F0. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 7: In-System Versaclock 6E Otp Non-Volatile Programming Via I2C

    Device I2C_ADDR If I2C_ADDR = 0 then D0 and if I2C_ADDR = 1 then D4. * The trim values are commonly written with default values and the OTP_TRIM bit is left at “1”. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 8: Factory Reserved Registers For Internal Use Only

    ADC gain setting - Factory reserved bits Table 10. RAM0 – 0x03: Factory Reserved Bits - ADC Gain Setting Bits Default Value Name Function ADC gain[15:8] ADC gain setting - Factory reserved bits ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 9 Table 12. RAM0 – 0x05: Factory reserved bits - ADC OFFSET Bits Default Value Name Function ADC offset[15:8] ADC offset - Factory reserved bits Table 13. RAM0 – 0x06: Factory Reserved Bits Bits Default Value Name Function TEMPY[7:0] Factory reserved bits ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 10 Table 15. RAM0 – 0x08: Factory Reserved Bits Bits Default Value Name Function GAIN<7:0> Unused Factory reserved bits Table 16. RAM0 – 0x09: Factory Reserved Bits Bits Default Value Name Function test[3:0] Factory reserved bits NP[3:0] Factory reserved bits ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 11 Table 19. RAM0 – 0x0C: Factory Reserved Bits Bits Default Value Name Function bandgap_trim_dn [5:0] bandgap voltage trim, one step is 1.2mV lower than current. unused bit unused bit ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 12 Table 22. RAM0 – 0x0F: Factory Reserved Bits Bits Default Value Name Function CLK1_amp[2] CLK1_amp[1] CLK1_amp[0] CLK2_amp[2] clk_amp: tune the amplitude of PAD, 1LSB is 10%, default is in the middle level–Factory reserved bits. CLK2_amp[1] CLK2_amp[0] CLK3_amp[2] CLK3_amp[1] ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 13: Configuration Registers

    Output Divider 1 Spread Modulation Rate Configuration Register 0x29 0x029 0x083 0x0DD 0x137 Output Divider 1 Spread Modulation Rate Configuration Register 0x2A 0x02A 0x084 0x0DE 0x138 Output Divider 1 Skew Integer Part 0x2B 0x02B 0x085 0x0DF 0x139 ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 14 0x158 Output Divider 3 Skew Integer Part 0x4B 0x04B 0x0A5 0x0FF 0x159 Output Divider 3 Skew Integer Part 0x4C 0x04C 0x0A6 0x100 0x15A Output Divider 3 Integer Part 0x4D 0x04D 0x0A7 0x101 0x15B ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 15: Configuration Register Detail And Functionality Description

    0x69 0x069 0x0C3 0x11D 0x177 Configuration Register Detail and Functionality Description Shutdown Function The shutdown logic offers flexible configuration of shutdown signaling and clock output enable control. The shutdown logic is summarized Table ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 16: Setting Up A Low-Power Shutdown Mode Through I2C

    3. Enable shutdown functionality by either writing 0x83 or 0x43 to register 0x10, for crystal clock source or external clock respectively. 4. Disable all output dividers by writing 0x80 to registers 0x21, 0x31, 0x41, and 0x51. 5. Take the SD/OE input pin 7 high. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 17 CLK_OS checks the shut down truth table. See Shutdown Function section. CLK1_OS CLK_OS checks the shut down truth table. See Shutdown Function section. CLK2_OS CLK_OS checks the shut down truth table. See Shutdown Function section. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 18: Crystal Load Capacitor Registers

    = (6.92pF+ 7.5pF + 1.5pF)/2 = 7.9pF which is the closest value to 8pF. Here, Cstray = 1.5pF; Package stray = 7.5pF The binary settings corresponding to this value will be: X1 = X2 = “10000”. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 19 Note: The 5P49V6975 use a pre-trimmed integrated crystal. Therefore, bits D7–D2 in registers 0x12 and 0x13 should be set to 1 to prevent inaccuracy of the output frequencies. Table 30. RAM1 – 0x14: Factory Reserved Bits Bits Default Value Name Function xtal_reg_amp_sel[3:0] Unused Factory reserved bit. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 20: Pll Pre-Divider Options

    Use bit D7 for divide by 2. Ref_div[6:0] Use “Bypass_prediv” bit in Table 32 for divide by 1. When “Bypass_prediv” is 1, register 0x15 setting is don't care. When “Sel_prediv2” is 1, Ref_div[6:0] setting is don't care. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 21: Pll Fractional Feedback Divider And Loop Filter

    Example: The circuit uses a 25MHz crystal and we want the VCO to be 2500MHz. The value of M needs to be 2500 / 25 = 100. FB_intdiv[11:0] = DEC2HEX(100) = 0 64 or 0000 0110 0100 binary. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 22 Unused Factory reserved bit. Table 36. RAM1 – 0x19: Feedback Fractional Divider Registers Bits Default Value Name Function The Feedback fractional divider has 24 bits divided amongst 3 registers (0x19, 0x1A and FB_frcdiv[23:16] 0x1B). ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 23 VCO regulator voltage adjustment (00, 01, 10, 11). D4 D3 = 00 or 01 sets LDO to 1.1V, cnf_vreg_vco[1:0] D4 D3 = 10 sets LDO to 1.2V, D4 D3 = 11 sets the LDO to 1.25V. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 24 1 means the part will reset. Used to re-synchronize the outputs when reprogramming of the device is performed (default value). vco_monitor_en Enable VCO monitoring and select automatically the VCO band. en_pll_bias Enable or disable biasing blocks in the PLL. Active high. Enable by default. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 25: Pll Loop Filter Settings

    1.5K = 11110. lpf_cnf_rz[4:0] 46.5K = 00000. Setting 11111 is not allowed. LPF 2nd pole capacitance control. lpf_cnf_cp[2:0] 000 = 12pF to 100 = 28pF step of 4pF. Settings above 100 are not allowed. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 26: Fractional Output Dividers And Spread Spectrum

    SS%AMT, from ±0.25% to ±2.5% center spread and - 0.5% to -5% down spread between 30 and 63kHz may be generated, independent of the output clock frequency. Five variables define spread spectrum in FODx (see Table 43). ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 27 N. N is always greater than or equal to the non-spread value of N, therefore the output frequency is always less than or equal to the non-spread frequency. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 28 30 bits of the 32 bit hex value and assign them to ODx_offfset[29:0]. In this manner it can be seen that ODx_offset is the value of FRAC(N), appropriately adjusted should center spread be enabled. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 29: Example Of Fod Calculation For Ssce = 1

    (HEX) (real) (HEX) (HEX) (HEX) 97.1455 14.41137 1.411373 1694FB7 98.147 14.26432 1.264318 143AA55 99.1485 14.12023 1.120234 11EC7A4 100.15 13.97903 0.979031 FAA1CE 101.1515 13.84063 0.840625 D73337 102.153 13.70493 0.704933 B4767A 103.1545 13.57188 0.571875 92666A ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 30 Only when an FOD gets its input clock from the PLL can the fractional part of the divider be used. When using the clock from a previous output, the FOD can only be used in integer mode. The following pages explain how to set up the MUX. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 31: Output Divider Control Settings (Table 47 Through Table 50)

    1100: FOD2 disabled and OUT2 uses clock from OUT1. En_aux1 needs to be 1. int_mode2 1111: FOD2 uses clock from OUT1 and OUT2 uses clock from FOD2. En_aux1 needs to be en_fod2 “int_mode2” sets integer mode for FOD2 (fractional settings will be ignored). ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 32 1100: FOD4 disabled and OUT4 uses clock from OUT3. En_aux3 needs to be 1. int_mode4 1111: FOD4 uses clock from OUT3 and OUT4 uses clock from FOD4. En_aux3 needs to be en_fod4 “int_mode4” sets integer mode for FOD1 (fractional settings will be ignored). ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 33 Unused Factory reserved bit. Table 53. RAM3 – 0x3D: Output Divider 2 Integer Part Bits Default Value Name Function OD2_intdiv[11:4] Output divider 2 integer part has 12 bit spread over 2 registers x3D and x3E. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 34 Output divider 3 integer part has 12 bit spread over 2 registers x4D and x4E. unused bits Unused Factory reserved bit. unused bits Unused Factory reserved bit. unused bits Unused Factory reserved bit. unused bits Unused Factory reserved bit. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 35: Output Divider Fractional And Spread Settings (Table 59 Through Table 94)

    If ODx_ssce = 0, contents of ODx_period and ODx_step are don't care only the ODx_offset are taken into account. If ODx_ssce =1, means the spread is enabled for center spread offset. (See example of spread calculation “Example of FOD calculation for SSCE = 1”) ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 36 Table 61. RAM2 – 0x24: Output Divider 1 Fractional Settings Bits Default Value Name Function OD1_offset[13:6] 30 bits to configure the fraction value of FOD1 in register address x22, x23, x24 and x25. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 37 24 bits used for modulation step size in register x26 x27 and x28. Table 64. RAM2 – 0x27: Output Divider 1 Step Spread Configuration Register Bits Default Value Name Function OD1_step[15:8] 24 bits used for modulation step size in register x26 x27 and x28. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 38 Function OD1_period[4:0] 13 bits used to configure spread modulation period in register x29 and x2A. Unused Bits Unused Factory reserved bit. Unused Bits Unused Factory reserved bit. Unused Bits Unused Factory reserved bit. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 39 Table 70. RAM3 – 0x34: Output Divider 2 Fractional Settings Bits Default Value Name Function OD2_offset[29:6] 30 bits to configure the fraction value of FOD2 in register address x32, x33, x34 and x35. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 40 24 bits used for modulation step size in register x36 x37 and x38. Table 73. RAM3 – 0x37: Output Divider 2 Step Spread Configuration Register Bits Default Value Name Function OD2_step[15:8] 24 bits used for modulation step size in register x36 x37 and x38. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 41 Function OD2_period[4:0] 13 bits used to configure spread modulation period in register x39 and x3A. unused bit Unused Factory reserved bit. unused bit Unused Factory reserved bit. unused bit Unused Factory reserved bit. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 42 Table 79. RAM4 – 0x44: Output Divider 3 Fractional Settings Bits Default Value Name Function OD3_offset[29:6] 30 bits to configure the fraction value of FOD3 in register address x42, x43, x44 and x45 ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 43 24 bits used for modulation step size in register x46 x47 and x48. Table 82. RAM4 – 0x47: Output Divider 3 Step Spread Configuration Register Bits Default Value Name Function OD3_step[15:8] 24 bits used for modulation step size in register x46 x47 and x48. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 44 Default Value Name Function OD3_period[4:0] 13 bits used to configure spread modulation period in register x49 and x4A. unused Unused Factory reserved bit. unused Unused Factory reserved bit. unused Unused Factory reserved bit. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 45 Table 88. RAM5 – 0x54: Output Divider 4 Fractional Settings Bits Default Value Name Function OD4_offset[29:6] 30 bits to configure the fraction value of FOD4 in register address x52, x53, x54 and x55. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 46 24 bits used for modulation step size in register x56 x57 and x58. Table 91. RAM5 – 0x57: Output Divider 4 Step Spread Configuration Register Bits Default Value Name Function OD4_step[15:8] 24 bits used for modulation step size in register x56 x57 and x58. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 47 Function OD4_period[4:0] 13 bits used to configure spread modulation period in register x59 and x5A. unused bits Unused Factory reserved bit. unused bits Unused Factory reserved bit. unused bits Unused Factory reserved bit. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 48: Skew

    INT (Skew) = INT((1+46.8/360)*14) - INT(14) = 15 - 14 = 1. FRAC (Skew) = (1+46.8/360)*14 - INT(14) - 1 = 0.82. Translating these two values to register settings: = 001 (hex)   = 74 (hex)   ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 49: Output Divider Skew Integer And Fractional Part Registers Settings (Table 95 Through Table 107)

    Table 95. RAM2 – 0x2B: Output Divider 1 Skew Integer Part Bits Default Value Name Function OD1_intskew[11:4] 12 bits are used to set Output Divider 1 skew integer part in register x2B and x2C. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 50 Table 98. RAM3 – 0x3B: Output Divider 2 Skew Integer Part Bits Default Value Name Function OD2_intskew[11:4] 12 bits are used to set Output Divider 2 skew integer part in register x3B and x3C. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 51: Output Divider Integer Settings (Table 51 Through Table 58)

    Table 101. RAM4 – 0x4B: Output Divider 3 Skew Integer Part Bits Default Value Name Function OD3_intskew[11:4] 12 bits are used to set Output Divider3 skew integer part in register x4B and x4C. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 52 6 bits are used to set Output Divider3 skew fractional part. Table 104. RAM5 – 0x50: Unused Factory Reserved Register Bits Default Value Name Function unused factory Unused Factory reserved bits. reserved bits ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 53 Table 107. RAM5 – 0x5F: Output Divider 4 Skew Fractional Part Bits Default Value Name Function unused bits Unused Factory reserved bit. unused bits Unused Factory reserved bit. OD4_frcskew[5:0] 6 bits are used to set Output Divider4 skew fractional part. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 54: Clock Output Configurations Registers

    This bit is used to disable the output value. clk1_amuxen2 Active High (1) to disable output. This bit is used to enable the clock output. en_clkbuf1 Active High (1) to enable the clock output. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 55 This bit is used to disable the output value. clk2_amuxen2 Active High (1) to disable output. This bit is used to enable the clock output. en_clkbuf2 Active High (1) to enable the clock output. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 56 This bit is used to disable the output value. clk3_amuxen2 Active High (1) to disable output. This bit is used to enable the clock output. en_clkbuf3 Active High (1) to enable the clock output. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 57 This bit is used to disable the output value. clk4_amuxen2 Active High (1) to disable output. This bit is used to enable the clock output. en_clkbuf4 Active High (1) to enable the clock output. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 58: Revision History

    Added note 4 in VersaClock 6E Family Power-Up Behavior section. ▪ August 30, 2018 Removed references for 5P49V60. ▪ Added value for Cz in PLL Loop Filter Settings section. November 6, 2017 Initial release. ©2017-2022 Renesas Electronics Corporation July 1, 2022...
  • Page 59 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
  • Page 60 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.

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