Patch Ideas - Xaoc Devices ROSTOCK Operator's Manual

note: The length of the loop will equal the
length of the pipeline. If you change the length,
it will cause glitches, as discussed in the previ-
ous section. Shortening the loop while playing
back the data will overwrite the unused mem-
ory cells with the shortened loop. If the length
is increased afterward, the pipeline will still
contain the shortened loop only.
The scramble button (together with the sig-
nal sent to the control input jack) changes the
looping behavior. When activated, the pipeline
is fed with both the input and output bits, com-
bined using logic XOR (fig. 3 shows the truth
table for this function). For example, if the in-
put bit is a constant 1, the stream of data bits
from the output will be inverted and written
back to the input, thus generating a cyclic pat-
tern every two lengths of the pipeline. Feeding
the input with more or less varying data and
operating the scramble function allows for
creating cyclic binary patterns of various
complexity, similar to 8 channels of a bina-
ry Turing machine, or a 256-valued discrete
state machine, or anything in between, de-
pending on how you patch them.
You can reset the loop's content at any point
by pressing the small clear button or plug-
ging a gate signal into the control input jack
above it.
CLOCKS
In general, the physical delay offered by Ros-
tock may be changed continuously within an
extreme range by varying the source clock.
Note that this delay is inversely proportional
to the clock frequency: you can increase the
delay 1000 times by slowing the clock down
input a
0
0
1
1
fig. 3: the truth table of the 'xor' function
by 1000 times. This, however, comes at the
cost of temporal resolution because data will
be sampled 1000 times slower.
By default, Rostock uses the source clock that
arrives together with the input data via the
Leibniz interface to drive its internal shift
registers. Since each data bit is processed by
a separate chip, it is possible to change the
timing of each bit's pipeline by replacing the
default clock using the front panel jacks. For
data representing audio, this will naturally
destroy the signal integrity as individual bits
will be delayed differently. However, when you
use individual Leibniz bits as channels of a
trigger sequence, this timing behavior is ideal
for creating rhythmic changes.
note: There is no limit to how slow the clock
can be, and it doesn't even have to be a regu-
lar pulse train. You can plug a stream of ran-
dom gates or bits of the binary data there.
The Leibniz hardware makes no distinction
between clocks and binary gate signals.

PATCH IDEAS

• Using Drezno with Rostock allows for ex-
perimenting with short delays on analog CV
6
input b output
0 0
1 1
0 1
1 0