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AMS AS585X User Manual

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User Guide
UG000439
AS585X
Standard Board
AS585X-CB-EK-ST
v1-00 • 2020-Apr-21

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  • Page 1 User Guide UG000439 AS585X Standard Board AS585X-CB-EK-ST v1-00 • 2020-Apr-21...

  • Page 2: Table Of Contents

    AS585X Eval Kit Power Module ....10 Table of Abbreviations ....71 AS585X Eval Kit DAC Module ....11 AS585X Eval Kit COB Sample Board ..12 Troubleshooting ......72 AS585X Eval Kit COF Sample Board ..13 Connection Issue ........72 FPGA Board ..........

  • Page 3: Introduction

    (like noise and input linearity) and the connection to an X-Ray photodetector panel. Two different AS585X samples are included in the Eval Kit in order to perform the complete evaluation: AS585X Chip-on-Board (COB) sample: The AS585X die is directly bonded to the AS585X sample board, which is equipped with the signal generator circuitry.
  • Page 4 In the COF the signal generator circuitry is not implemented, therefore it is not possible to stimulate the input channels externally. An FPGA Module controls the AS585X SPI interface to read and write register values, the AS585X Low-Voltage Differential Signaling (LVDS) interface to transfer the data off-chip, as well as the Eval Kit input signal generator.

  • Page 5: Eval Kit Content

    Document Feedback AS585X Introduction Eval Kit Content Figure 1: Included Components (part 1) 1x AS585X Chip-on-Board (COB) Sample DAC Module Board 1x AS585X Chip-on-Flex (COF) Sample Power Module with adapter board AS585X Eval Kit Base Board FPGA Board Metallic shield cover 1x FPGA Adaptor Board Eval Kit Manual •...

  • Page 6: Ordering Information

    Figure 2: Included Components (part 2) 1x FPGA Power Supply 1x ams neckband 1x USB 3.0 Cable 1x ams pen 1x USB memory stick with AS585X Eval Kit 1x Eval Kit User Guide Software Ordering Information Ordering Code Description AS585X-CB-EK-ST AS585X Standard Board Eval Kit Manual •...

  • Page 7: Getting Started

    Getting Started System Requirement The AS585X Eval Kit software requires Windows 7 SP1 or later and a port USB 3.0. Eval Kit Assembly Attach the Base Board to the FPGA Adapter Board. The FPGA Module is already pre-mounted on the FGPA Adapter Board.
  • Page 8 Document Feedback AS585X Getting Started Figure 4: Eval Kit Powered by ±8 V External Power Supplies and 5 V FPGA Power Supply The Eval Kit is shipped with the jumper configured to supply the +5 V from the FPGA Adapter Board.

  • Page 9: Hardware Description

    Hardware Description Hardware Description Eval Kit is composed of five boards: The Base Board on which an AS585X sample is mounted, an FPGA board and its adapter, a Power Module and a DAC Module. Figure 5: AS585X Eval Kit Hardware Eval Kit Manual •...

  • Page 10: As585X Eval Kit Base Board

    The Power Module is an adjustable voltage power module with 4 outputs, namely VDD1, VDD2, VDD3 and VDD4. VDD1 is used to supply power to the analog AS585X circuitry while VDD2 is used to supply the digital one. VDD1 delivers 1A of load current while other outputs are limited to 0.5 A of load current.

  • Page 11: As585X Eval Kit Dac Module

    Base Board, which adds further series resistance. When the AS585X device is used at maximum power mode (load current = 600 mA), this implies a 50 mV analog voltage supply drop, please refer to the example of the AS585X working point in Figure 8 shown below (red line).

  • Page 12: As585X Eval Kit Cob Sample Board

    AS585X Hardware Description The DAC module is used to generate the input signals for the evaluation of the AS585X. The DAC Module uses a 20-bit DAC, with an output non-linearity verified to be below ±15 µV over its entire 0 to 5 V range. The non-linearity of the DAC itself is not taken into account and not corrected during the linearity measurement of the AS585X.

  • Page 13: As585X Eval Kit Cof Sample Board

    Figure 13: AS585X Eval Kit COF Sample with Adapter Board The Chip-on-Flex is the default package type of the AS585X, where the die is bonded on a flex substrate. Such package allows the direct connection to an X-Ray photodetector panel.

  • Page 14: Fpga Board

    Figure 14: OpalKelly XEM6310-LX45 The FPGA used in the AS585X Eval Kit is an Opal Kelly XEM6310-LX45. The AS585X software loads into the FPGA a dedicated firmware, through which the FPGA manages the AS585X digital signals (SPI interface, the LVDS readout, clock generation) and the baseboard circuitry (DAC, Charge Step Generator, PSRR VDDA Step Generation) Eval Kit Manual •...

  • Page 15: Software Description

    Follow the instructions of the wizard to unpack and install the user interface and all required software packages to run the Eval Kit. The software does not run if no AS585X Eval Kit hardware is connected. Getting Started Start the AS585X Eval Kit software using the shortcut ( ) on the desktop.

  • Page 16: Gui Description

    AS585X Eval Kit Software GUI GUI Description The AS585X GUI is composed of one information panel at the bottom and three tabs at the top: “Single Frame” tab: Is used to acquire images (or single frames) and to evaluate its related noise level.
  • Page 17 CRC error is detected. LVDS Timeout Indicates if LVDS reading fails. It is usually green; it becomes red only when the LVDS reading fails. Current Configuration Indicates the configuration stored on the AS585X. Exit Stop button “Single Frame” Tab 4.4.2...
  • Page 18 Description Take Single Frame Capture an image Readings AS585X LVDS output (counts) in LSB vs. number of samples (consecutive) for all selected channels. 2D Reading AS585X LVDS output (counts) in LSB represented as intensity (grey scale) for all selected channels (x-axis) and acquired samples (y-axis).
  • Page 19 'A' Related input charge can be calculated as described in chapter 5.2 CSA Operation Overview and chapter 6 Evaluation Modes INL of AS585X for output from “capacitors A” in LSB calculated with fixed INL with capacitors 'A' point method Maximum INL averaged over selected channels from “capacitors A”...
  • Page 20 From the “Configuration selection”, it is possible to select the saved configuration. As soon as the configuration is selected, the register map gets loaded on the AS585X. All the fields on the measurement setting as well as the AS585X register map can be edited. Eval Kit Manual • PUBLIC UG000439 •...
  • Page 21 Document Feedback AS585X Software Description Save Configuration If needed, it is possible to save changes into a new configuration, by pressing on the “Save configuration” button. A window will pop up, asking to type the name of the new configuration...
  • Page 22 Document Feedback AS585X Software Description Disable Standard Configuration Protection If it is required to edit the preinstalled configurations, it is possible to disable this function by ticking the option “Disable Standard Configuration Protection”, and then typing the same name of the configuration to be edited.
  • Page 23 In this section, settings related to the “Channel Selector” are located. Refer to the note section on the GUI left hand side or to the schematic for a detailed description about the AS585X Sample channels. Input Digital Signals Settings (from FPGA) In this section, settings related to the Input Digital Signals Settings (from FPGA) are located.
  • Page 24 AS585X Software Description AS585X Configuration In this section, settings related to the “AS585X Configuration” are located, where it is possible to edit the AS585X register map. Refer to Chapter 8 Register Description of the datasheet for the complete description. Raw Data Save In this section, settings related to the Raw Data Saving are located.

  • Page 25: As585X Operation

    AS585X Operation Introduction In order to evaluate the AS585X performance figures, with the Eval Kit it is possible to emulate the operating condition of the device as if it was connected to an X-ray flat panel detector. The charge signal from an X-ray flat panel detector can be emulated by generating charge on capacitors connected to AS585X inputs.

  • Page 26: Csa Operation Overview

    Document Feedback AS585X AS585X Operation CSA Operation Overview The CSA operation is divided in 3 main phases, namely the reset phase, the offset phase and the signal phase: Reset phase: During this phase, the output voltage of the CSA has the same value as on the CSA_VREF_IN pin (typically 1.75V).
  • Page 27 Document Feedback AS585X AS585X Operation Where ● is the charge injected INJ1 ● are the capacitors used for the charge injection and defined in the Charge Injection Register A (Address 0x06) cap_q_trans1 ● or V are the voltages on pins Vcharge or VchargeAux. Charge can be injected...
  • Page 28 Document Feedback AS585X AS585X Operation Where ● the CSA output voltage during the offset phase CSA_OFFSET ● is the Feedback capacitance of the CSA and defined in the Control Register A (Address 0x02) csa_gain ● is the charge injected during the signal phase, which can be internally or externally...

  • Page 29: Timing

    AS585X Operation Timing As described in Chapter 7.10.4 Readout Mode 4 – All Parallel of the datasheet, in the AS585X the CSA charge acquisition of row n, the ADC signal conversion of the previous row n-1 and LVDS data output of row n-2 are done in parallel. The user needs to make sure that the LVDS readout of row n- 2 is completed before the ADC conversion of row n-1 is finished.
  • Page 30 ● Control Register A (Address 0x02) adc_pwr ● Control Register A (Address 0x02) adc_osr as summarized in Figure 33 Figure 33: AS585X Minimum Charge Acquisition Time and Minimum ADC Conversion Time CSA Power ADC Power AS585X Minimum Charge Minimum ADC...
  • Page 31 4144 = 259 words (start word + temperature word +256 channels + end word) * 16-bit per word ● Factor 2 because of the dual data rate Figure 34: AS585X Data Output Time LVDS Clock Frequency Data Output Time 12.95 μs 160 MHz 14.8 μs...
  • Page 32 AS585X Operation AS585X TIME Registers (Address 0x20 – 0x33) 5.3.3 The timing management on the AS585X is defined in the Time Registers. The content of such registers is expressed in number of ACLK cycles after the SYNC. Information When the ADC is in low power mode (<adc_pwr>=0), only even values are allowed in the time...
  • Page 33 Document Feedback AS585X AS585X Operation Figure 36: Example: TIME Registers (Address 0x20 – 0x33) Content of the Configuration “Internal-Charge- Generation-Holes_20_us” Eval Kit Manual • PUBLIC UG000439 • v1-00 • 2020-Apr-21 │ 33...
  • Page 34 CSA and ADC are configured in high power mode (<csa_pwr>=11, <adc_pwr>=1). In general, the acquisition time needs to fulfil the following condition Equation 12: ���������������������� �������� ≥ ������ [��ℎ�������� ���������������������� ��������, ������ �������������������� ��������] Figure 37: AS585X Acquisition Time ADC Power Minimum ADC AS585x Option Conversion...
  • Page 35 It is important that the CSA reset start at least after 1 ACLK cycle and to leave 1 ACLK cycle between each phase when the ADC is in high power mode (<adc_pwr>=1). These values must be doubled when the ADC is in low power mode (<adc_pwr>=0). Figure 39: AS585X CSA Reset Start Minimum ADC Power AS585X...
  • Page 36 Document Feedback AS585X AS585X Operation Figure 40: AS585X Time Between CSA Phases ADC Power Min Time Typ Time Max Time AS585X Minimum ADC Option Between Between Between Version Conversion Time Phases Phases Phases <adc_pwr> 2 ACLK 2 ACLK 38 μs...
  • Page 37 Document Feedback AS585X AS585X Operation Figure 42: AS585X CSA Phases with Internal Charge Injection SYNC Reset phase Offset phase Signal phase charge1 charge2 charge3 CSA_MAX CSA_OFFSET CSA_OUT CSA_RESET CSA_SIGNAL CSA_MIN Charge acquisition time Figure 43: Example: Register Map of the Configuration “Internal-Charge-Generation-Holes_20_us”...
  • Page 38 Injection In the AS585X, the CSA output is fed into the low-pass filter. The filter time constant can be configured by changing the resistor value on bits <lpf_tc>. For fast settling, a filter acceleration circuit, which shortens the resistor by setting <lpf_acc> to logic 1 is implemented.
  • Page 39 Document Feedback AS585X AS585X Operation Figure 45: AS585X Delay between CSA Phase Start and Filter Acceleration Min Delay Between Typ Delay Between Max Delay Between ADC Power AS585X CSA Phase Start CSA Phase Start CSA Phase Start Option Version and Filter...
  • Page 40 ADC Conversion 2 ADC conversion time Each AS585X ADC does the sequential acquisition of two channels; therefore, during the conversion time two reset phases and two conversion phases take place. As described in the Chapter 7.8 Analog to Digital Converter (ADC) of the datasheet, the ADC conversion phase is defined by the oversampling ratio (OSR) in: ●...
  • Page 41 Document Feedback AS585X AS585X Operation Figure 51: AS585X ADC Conversion Time ADC Power Option AS585x Version ADC Conversion <adc_pwr> <adc_osr> AS585X 148 ACLK cycles AS585X 176 ACLK cycles AS5850 74 ACLK cycles AS5850 88 ACLK cycles Concerning the ADC reset phase, when the ADC is in high power mode (<adc_pwr>=1) its absolute minimum duration is at least 1 ACLK cycle longer than CDS reset duration.
  • Page 42 Document Feedback AS585X AS585X Operation Figure 53: Example: Register Map of the Configuration “Internal-Charge-Generation-Holes_20_us” Parameter Register Value ADC reset duration t_adcreset_dur 6 ACLK Cycle ADC reset start 1 t_adcreset_start1 0 ACLK Cycle ADC reset start 2 t_adcreset_start2 80 ACLK Cycle...
  • Page 43 Functional Diagram of Flat Panel and AS585X Front-End In the AS585X operation, the CSA receive charge from a TFT panel and the timing is controlled by a line driver. Refer to Chapter 7.3 of the datasheet for the complete description.
  • Page 44 Document Feedback AS585X AS585X Operation Figure 55: Main CSA Phases During AS585X Operation Reset phase Offset phase Signal phase charge1 charge2 injection (Line driver) CSA_MAX CSA_OFFSET CSA_RESET CSA_OUT CSA_SIGNAL CSA_MIN As shown in Figure 55, the line driver needs to close slightly after the signal phase starts and needs to open slightly after the signal phase ends.

  • Page 45: Evaluation Modes

    Evaluation Modes No Charge Generation In “No charge generation” mode, no charge is injected on the AS585X. Therefore, it is possible to evaluate the AS585X noise and the output in no signal condition (baseline). It can be evaluated with both the COB and COF samples.

  • Page 46: Internal Charge Generation (Holes)

    The offset charge is injected from the pin VchargeAux that is connected to GND while the signal charge is injected from the pin Vcharge that is driven by the DAC. It can be evaluated with both the COB and COF samples. Figure 57: AS585X Eval Kit Hardware Architecture DAC Module 256x 128x...
  • Page 47 Document Feedback AS585X Evaluation Modes Figure 58: Control Register A (Address 0x02) and B (Address 0x03) Content of the Configuration “Internal-Charge-Generation-Holes_20_us” Figure 59: Charge Injection Register A (Address 0x06), B (Address 0x07) and C (Address 0x08) Content of the Configuration “Internal-Charge-Generation-Holes_20_us”...
  • Page 48 Document Feedback AS585X Evaluation Modes Figure 60: TIME Registers (Address 0x20 – 0x33) Content of the Configuration “Internal-Charge- Generation-Holes_20_us” Eval Kit Manual • PUBLIC UG000439 • v1-00 • 2020-Apr-21 │ 48...
  • Page 49 Document Feedback AS585X Evaluation Modes 6.2.1 Electrons Internal Charge Injection during the Offset Phase from VchargeAux As shown in the “Internal-Charge-Generation-Holes_20_us” register map, the offset phase starts at 27 and ends at 92 as ● TIME Registers (Address 0x25) t_offset_start=27 ●...
  • Page 50 Document Feedback AS585X Evaluation Modes If a positive charge is to be injected during the signal phase, a negative charge is required during the offset phase in order to exploit the full input range. The Eval Kit does not allow control on the voltage applied to the pin VchargeAux (shorted to GND), therefore only discrete values of negative charge can be injected, according to the available combinations allowed by cap_q_trans1 and n_q_trans1.
  • Page 51 Document Feedback AS585X Evaluation Modes 6.2.3 Holes Internal Charge Injection During the Signal Phase from Vcharge As shown in the “Internal-Charge-Generation-Holes_20_us” register map, the signal phase starts at 93 and ends at 158 ● TIME Registers (Address 0x27) t_signal_start=93 ●...
  • Page 52 Document Feedback AS585X Evaluation Modes With an offset charge of -0.35 pC, the condition described in Equation 8 is fulfilled �� 2���� �������� ���������� + | �� | → 0.6���� < |�� | < + 0.35���� ������������ ������������ 6.2.4 CSA Output Voltage Signal Phase The CSA output voltage at the end of the signal phase is: ��...
  • Page 53 Document Feedback AS585X Evaluation Modes ● is the CSA output voltage during the offset phase CSA_OFFSET ● baseline is ~-29300 LSB ● ADC resolution is ~40µV/LSB ● CSA Polarity is the polarity selection (electrons or holes) and defined in the Control Register B (Address 0x03) csa_pol=0: Positive charge (holes) →...

  • Page 54: Internal Charge Generation (Electrons)

    1.75V on such pin. Being the VchargeAux pin tied to GND and not being able to be driven to an arbitrary voltage, this operation is not possible. It can be evaluated with both the COB and COF samples. Figure 65: AS585X Eval Kit Hardware Architecture DAC Module 256x 128x...
  • Page 55 Document Feedback AS585X Evaluation Modes Figure 66: Control Register A (Address 0x02) and B (Address 0x03) Content of the Configuration “Internal-Charge-Generation-Electrons_20_us” Figure 67: Charge Injection Register A (Address 0x06), B (Address 0x07) and C (Address 0x08) Content of the Configuration “Internal-Charge-Generation-Electrons_20_us”...
  • Page 56 Document Feedback AS585X Evaluation Modes Figure 68: TIME Registers (Address 0x20 – 0x33) Content of the Configuration “Internal-Charge- Generation-Electrons_20_us” Eval Kit Manual • PUBLIC UG000439 • v1-00 • 2020-Apr-21 │ 56...
  • Page 57 Document Feedback AS585X Evaluation Modes 6.3.1 No Charge Injection during the Offset Phase from VchargeAux As it is not possible to inject a suitable positive charge during the offset phase for CSA voltage offset adjustment, the internal charge generation circuit 1 is disabled ●...
  • Page 58 Document Feedback AS585X Evaluation Modes Figure 69: Measurement Settings Substituting the values ● Charge Injection Register B (Address 0x07) cap_q_trans2=1000: C =800fF ● Charge Injection Register B (Address 0x07) n_q_trans2=1: N QTRANS2 It becomes = 800���� ∙ ( 1.5 − 1.75�� ) ∙ 1 = −0.2����...
  • Page 59 Document Feedback AS585X Evaluation Modes Figure 70: Charge Injection Timing Diagram During the 3 CSA Phases Reset phase Offset phase Signal phase charge1 charge2 injection (Line driver) CSA_MAX CSA_SIGNAL CSA_RESET CSA_OFFSET CSA_OUT CSA_MIN 6.3.4 ADC Digital Output The expected ADC output is calculated as Equation 19: ��...
  • Page 60 Document Feedback AS585X Evaluation Modes Figure 71: Typical Internal-Charge-Generation-Electrons Single Frame Eval Kit Manual • PUBLIC UG000439 • v1-00 • 2020-Apr-21 │ 60...

  • Page 61: External Charge Generation (Holes)

    External Charge Generation (holes) In the “External Charge Generation-XX” mode, the charge signal is generated externally by applying a voltage step to a set of capacitors connected to the AS585X frontend inputs, thus emulating the charge signal from an X-ray flat panel detector.
  • Page 62 Document Feedback AS585X Evaluation Modes Figure 72: AS585X Eval Kit Hardware Architecture DAC Module DETECTORS 256x 128x 41-48, DOUT_P 73-80, 187-194, charge LVDS 219-226 caps ampl DOUT_N line Temperature sensor VDDA 3.5 V Power VDDA_ADC Power supply Module VDDD & reset...
  • Page 63 Document Feedback AS585X Evaluation Modes Figure 74: Charge Injection Register A (Address 0x06), B (Address 0x07) and C (Address 0x08) Content of the Configuration “External-Charge-Generation-Holes_20_us” Eval Kit Manual • PUBLIC UG000439 • v1-00 • 2020-Apr-21 │ 63...
  • Page 64 Document Feedback AS585X Evaluation Modes Figure 75: TIME Registers (Address 0x20 – 0x33) Content of the Configuration “External-Charge- Generation-Holes_20_us” Eval Kit Manual • PUBLIC UG000439 • v1-00 • 2020-Apr-21 │ 64...
  • Page 65 Document Feedback AS585X Evaluation Modes 6.4.1 Electrons Internal Charge Injection during the Offset Phase from VchargeAux As in “Internal-Charge-Generation-Holes_20_us”, an offset charge of 0.35 pC is injected for CSA voltage adjustment = 200���� ∙ ( −1.75�� ) ∙ 1 = −0.35����...
  • Page 66 Document Feedback AS585X Evaluation Modes �� 0.6���� ������������ �� = �� − ( ) = 2.17�� − ( ) = 1.46�� ������_������������ ������_������������ �� 0.84���� ���� Figure 77: Charge Injection Timing Diagram During the 3 CSA Phases. Reset phase Offset phase...
  • Page 67 Figure 79: Typical External-Charge-Generation-Holes Single Frame External charge injection is possible only on the channels connected to the Charge Capacitors, which are 32 on the AS585X sample boards. Eval Kit Manual • PUBLIC UG000439 • v1-00 • 2020-Apr-21 │ 67...

  • Page 68: External Charge Generation (Electrons)

    Document Feedback AS585X Evaluation Modes External Charge Generation (electrons) The “External Charge Generation (electrons)” mode can be evaluated only with the COB sample. The amount of charge externally injected with the Eval Kit charge generation circuitry is expressed in Equation 15 ∙...
  • Page 69 Document Feedback AS585X Evaluation Modes 6.5.1 Timing The step function can be inverted by adjusting the timing: rise the level of the step during the reset phase and then let it fall back to the low level slightly after the start of the signal phase, leaving it to the low level for the rest of the acquisition, as described in paragraph 5.3.3 Line Driver Timing.

  • Page 70: Other Operation Modes

    AS585X Other Operation Modes Other Operation Modes In order to enable a wide range of applications, the AS585X is highly configurable and it has several other operation modes with respect to those treated in this manual, such as: ● Binning mode ●...

  • Page 71: Table Of Abbreviations

    Document Feedback AS585X Table of Abbreviations Table of Abbreviations Figure 82: Table of Abbreviations Abbreviation Explanation Analog-to-Digital Converter Correlated Double Sampling Charge Sensing Amplifier Integral Nonlinearity Low-Pass Filter Least Significant Bit LVDS Low-Voltage Differential Signaling Serial Peripheral Interface Abbreviation Explanation Eval Kit Manual •...

  • Page 72: Troubleshooting

    Document Feedback AS585X Troubleshooting Troubleshooting Connection Issue Please check the correct driver installation in the Device Manager. To start the Device Manager click the Start button and type in the Start Search box device manager and then press enter. Figure 83:...

  • Page 73: Crc Fail

    Document Feedback AS585X Troubleshooting CRC Fail Figure 84: CRC Fail If this dialog message pops up, please check the power supply on the board. If the power supply is connected properly and the problem persists, please use another external power supply instead of the supplied one, as described in section 2.2.

  • Page 74: Revision Information

    Document Feedback AS585X Revision Information Revision Information Changes from previous version to current revision v1-00 Page Initial version ● Page and figure numbers for the previous version may differ from page and figure numbers in the current revision. ● Correction of typographical errors is not explicitly mentioned.

  • Page 75: Legal Information

    AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein.
  • Page 76 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ams OSRAM AS5850_EK...

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