Summary of Contents for Abov A31G22x
- Page 1 A31G22x Clock Setting Guide Application Note Version 1.01 Global Top Smart MCU Innovator, ABOV Semiconductor www.abovsemi.com...
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Page 2: Table Of Contents
Contents A31G22x Clock Setting Guide Contents Glossary ............................4 Introduction ............................ 5 Clock System ..........................6 3.1. SCU Block Diagram ......................6 3.2. Clock Sources for Peripherals ..................... 8 Clock Sources ..........................11 4.1. LSI Clock ........................... 12 4.1.1. F/W Configuration ....................12 4.2. - Page 3 Figure 7. XTAL Oscillator Circuit ......................15 Figure 8. HSE Clock F/W Configuration ....................16 Figure 9. PLL Block Diagram of A31G22x Series ................. 17 Figure 10. PLL Clock F/W Configuration Example 1 ................19 Figure 11. PLL Clock F/W Configuration Example 2 ................21 Figure 12.
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Page 4: Glossary
1. Glossary A31G22x Clock Setting Guide Glossary Table 1. Definition of Terms Term Description HCLK AHB Clock PCLK APB Clock MCLK Main Clock Low Speed Internal Clock High Speed Internal Clock Low Speed External Clock High Speed External Clock Phase Locked Loop Clock... -
Page 5: Introduction
2. Introduction Introduction A31G22x has an SCU (System Control Unit) that can control the system settings flexibly to meet the requirements of an application. Specifically the SCU allows users to configure a main system clock by selecting and setting a clock source for the user system. -
Page 6: Clock System
3.1. SCU Block Diagram A31G22x series has two main operating clocks. One is HCLK which produces a clock signal both for CPU and AHB bus. The other is PCLK using APB bus which produces a clock signal for peripheral systems. -
Page 7: Figure 1. Clock Tree Configuration
A31G22x Clock Setting Guide 3. Clock System WDTRC Cortex M0+ HCLK 32.250k (N=16) Memory FCLK 500kHz (N=1,2,4) MCLK PCLK APB Bus Interface SCU_PCER1,2 [1:0] Divider SXIN 32.768kHz (N=1,2,4) CLKO MCLKSEL (N= 1 to 255) MCLK PLLBYPASS SYSTICK SCU_MCCR1 32MHz (N=1,2,4,8,6,32) -
Page 8: Clock Sources For Peripherals
3. Clock System A31G22x Clock Setting Guide 3.2. Clock Sources for Peripherals Figure 2 shows how to set the peripheral clock. Selecting a peripheral clock is a typical method of MCCRn and PCLK. Exceptionally WT, WDT, LCD use other clocks besides MCCRn and PCLK. (n = 1, 2, 3, 4, 5, 6 and 7). -
Page 9: Table 3. Clock Sources Of Peripherals
A31G22x Clock Setting Guide 3. Clock System Table 3 shows the Clock Buses and Clock Sources that A31G22x supports for each peripheral. Table 3. Clock Sources of Peripherals Peripheral Clock Clock Bus Clock Source Core HCLK CFMC HCLK / PCLK... - Page 10 3. Clock System A31G22x Clock Setting Guide Table 3. Clock Sources of Peripherals (continued) Peripheral Clock Clock Bus Clock Source PCLK WDTRC LSI/16 SCU_MCCR3 MCLK PCLK PCU Debounce Clock SCU_MCCR4 MCLK USART PCLK UART PCLK PCLK PCLK PCLK WDTRC LSI/16...
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Page 11: Clock Sources
4. Clock Sources Clock Sources A31G22x allows users to configure the main clock and peripheral clock by using the clock sources listed in Table 4 . Various functions of user application can be implemented using these clock sources. Table 4. Definition of Clock Sources... -
Page 12: Lsi Clock
4. Clock Sources A31G22x Clock Setting Guide 4.1. LSI Clock LSI is an internal oscillator operating at a low speed of 500kHz, and begins to oscillate when power is first applied to the initialized MCU. It is used as a clock source in Low Power mode too. -
Page 13: Lse Clock
A31G22x Clock Setting Guide 4. Clock Sources 4.3. LSE Clock The LSE is an auxiliary external crystal (SXTAL) that operates at a low speed of 32.768kHz. The LSE clock can be used as a system clock or peripheral clock. It is used as a clock source in Low Power mode too. -
Page 14: F/W Configuration
4. Clock Sources A31G22x Clock Setting Guide 4.3.2. F/W Configuration SXIN and SXOUT pins of the LSE clock must be set before enabling the LSE clock. After enabling the LSE clock, stabilization time for the SXTAL is required. Next, users must set the LSE clock source as the system clock and update the global variables representing HCLK and PCLK to have the system operation frequency value. -
Page 15: Hse Clock
A31G22x Clock Setting Guide 4. Clock Sources 4.4. HSE Clock HSE clock is a main external crystal (XTAL) that operates at the high speed ranging from 1MHz to 16MHz. It can be used as an input source setting the main clock and PLL clock or a peripheral clock. -
Page 16: F/W Configuration
4. Clock Sources A31G22x Clock Setting Guide 4.4.2. F/W Configuration XIN and XOUT pins of the HSE clock must be set before enabling the HSE clock. After enabling the HSE clock, stabilization time for the XTAL is required. Next, users must set the HSE clock source as the system clock and update the global variables representing HCLK and PCLK to have the system operation frequency value. -
Page 17: Pll Clock
PLLINCLK Pre-Divider Value 0 to 7 POSTDIV1 Post Multiplier Value 0 to 255 POSTDIV2 Post Divider Value 0 to 15 OUTDIV Output Divider Value 0 to 15 PLLMODE Frequency Doubler Value 0 to 11 Figure 9. PLL Block Diagram of A31G22x Series... -
Page 18: Calculating Pll Output Frequency
4. Clock Sources A31G22x Clock Setting Guide 4.5.2. Calculating PLL Output Frequency PLL of A31G22x series can set the output frequency, f , in 1MHz increments accurately. The formula for the f is introduced below. Input range of the f... -
Page 19: F/W Configuration
A31G22x Clock Setting Guide 4. Clock Sources 4.5.3. F/W Configuration Example 1 Figure 10 and the procedure listed below show an example code that outputs PLL 48MHz frequency using the HSI clock source. Figure 10. PLL Clock F/W Configuration Example 1 Enable the HSI clock source. - Page 20 4. Clock Sources A31G22x Clock Setting Guide Set N1 to the value that allows f to be less than 200MHz. * (N1 + 1) = 2MHz * (47 + 1) = 96MHz Set D to the value that allows f to be less than 250MHz.
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Page 21: Figure 11. Pll Clock F/W Configuration Example 2
A31G22x Clock Setting Guide 4. Clock Sources Example 2 Figure 11 and the procedure listed below describe an example code that outputs PLL 48MHz frequency using the HSE clock source that operates with 8MHz XTAL. Figure 11. PLL Clock F/W Configuration Example 2 Set XIN and XOUT pins and enable HSE clock source. - Page 22 4. Clock Sources A31G22x Clock Setting Guide Set N1 to the value that allows f to be less than 200MHz. * (N1 + 1) = 2MHz * (47 + 1) = 96MHz Set D to the value that allows f to be less than 250MHz.
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Page 23: Flash Access Timing
Flash Access Timing 5.1. Wait Time Configuration Users of A31G22x can set the Wait-time in WAIT field (CFMC_CFG[10:8]) of the CFMC_CFG register after setting the system main clock. The Wait-time settings implies the Flash access speed and affects system performance. -
Page 24: Output Of System Main Clock
A31G22x Clock Setting Guide Output of System Main Clock A31G22x provides a function that outputs the system main clock (MCLK) frequency to a port. Set the PF4 pin as an Alternative Function, and select a CLKO function. Configure the SCU_COR register to enable the CLKO Divider and set its value: ①... -
Page 25: Figure 14. Oscilloscope Measurement Of Clko Pin Output
A31G22x Clock Setting Guide 6. Output of System Main Clock Users can measure the signal at the CLKO pin (PF4) by connecting an oscilloscope probe. The signal is about 50kHz Pulse Wave resulted from the LSI clock divided by 10. -
Page 26: Examples
7. Examples A31G22x Clock Setting Guide Examples A31G22x provides an example code setting the system clock for each clock source. This can be viewed in Keil uVISION 5 and IAR Embedded Workbench compiler. Example Code_A31G22x\Examples\ClkChange\* Each example project changes the system clock to the clock that users want to use after clock initialization. -
Page 27: References
A31G22x Clock Setting Guide 8. References References A31G22x User’s Manual A31G22x Datasheet ... -
Page 28: Revision History
Revision History A31G22x Clock Setting Guide Revision History Version Date Description 1.00 20.12.10 Initial preliminary version created 1.01 21.01.18 Revised description in 3.1, Figure 2, 4.3, 4.4, and 4.5. Added CLKO formula in Chapter 6. - Page 29 ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders.