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Infineon Technologies Cypress CYW20733 Manual

Single-chip bluetooth transceiver wireless input devices
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Summary of Contents for Infineon Technologies Cypress CYW20733

  • Page 1 Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.
  • Page 2 Wireless Input Devices The Cypress CYW20733 is a Bluetooth 3.0 + EDR compliant, stand-alone baseband processor with an integrated 2.4 GHz trans- ceiver. The device is ideal for applications in wireless input devices including game controllers, keyboards, and joysticks. Built-in firmware adheres to the Bluetooth Human Interface Device (HID) profile and Bluetooth Device ID profile specifications.
  • Page 3 CYW20733 Figure 1. Functional Block Diagram Muxed on GPIO RTSN RTSN MISO 1.2V SDA/ CTSN CTSN VDDC Speaker MOSI VSS, BSC/SPI VDDO, 28 ADC VDDC Inputs Master 1.2V Digital Class-D Test Periph Processing Interface Audio Speaker Driver UART UART Block Unit (BSC is I2C- compat)

  • Page 4: Table Of Contents

    CYW20733 Contents 1.Functional Description ........4 1.14 Infrared Modulator ..........18 1.15 Infrared Learning ..........19 1.1 Integrated Radio Transceiver ......4 1.1.1 Transmitter Path ........4 1.16 Shutter Control for 3D Glasses ......19 1.1.2 Receiver Path .......... 4 1.17 Triac Control ............20 1.1.3 Local Oscillator ........

  • Page 5: Functional Description

    CYW20733 1. Functional Description 1.1 Integrated Radio Transceiver The CYW20733 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has been designed to provide low power, low cost, robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band.

  • Page 6: Microprocessor Unit

    CYW20733 1.2 Microprocessor Unit The CYW20733 microprocessor unit (µPU) runs software from the link control (LC) layer up to the Human Interface Device (HID). The microprocessor is based on an ARM7™ 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The µPU has 320 KB of ROM for program storage and boot-up, 80 KB of RAM for scratch-pad data, and patch RAM code.

  • Page 7: External Reset

    CYW20733 1.2.4 External Reset An external active-low reset signal, RESET_N, can be used to put the CYW20733 in the reset state. The RESET_N pin has an internal pull-up resistor and, in most applications, it does not require that anything be connected to it. RESET_N should only be released after the VDDO supply voltage level has been stabilized.

  • Page 8: Test Mode Support

    CYW20733 Enhanced power control ■ HCI read, encryption key size command ■ The CYW20733 supports all of the new Bluetooth version 2.1 features: Extended inquiry response ■ Sniff subrating ■ Encryption pause and resume ■ Secure simple pairing ■ Link supervision timeout changed event ■...

  • Page 9: Uart Interface

    CYW20733 4 MHz maximum (Compatibility with high-speed I C-compatible devices is not guaranteed.) ■ The following transfer types are supported by the BSC: Read (up to 127 bytes can be read) ■ Write (up to 127 bytes can be written) ■...

  • Page 10: Pcm Interface

    CYW20733 Table 3. CYW20733 Peripheral UART Pin Name pUART_TX pUART_RX pUART_CTS_N pUART_RTS_N Configured pin name – – – – 1.5 PCM Interface The CYW20733 PCM interface can connect to linear PCM codec devices in master or slave mode. In master mode, the device generates the PCM_BCLK and PCM_SYNC signals.

  • Page 11: Slot Mapping

    CYW20733 1.5.2 Slot Mapping Table 4. PCM Interface Time-Slotting Scheme Audio Sample Rate Time-Slotting Scheme 8 kHz The number of slots depends on the selected interface rate, as follows: Interface rate Slot 1281 2562 5124 10248 204816 16 kHz The number of slots depends on the selected interface rate, as follows: Interface rate Slot 2561...
  • Page 12 CYW20733 Figure 4. Recommended Oscillator Configuration—12 pF Load Crystal Table 5. Reference Crystal Electrical Specifications Parameter Conditions Unit Input signal amplitude – – 2000 mVp-p Nominal frequency – – 24.000 – Oscillation mode – Fundamental – Frequency tolerance @25°C – ±10 –...

  • Page 13: Gpio Port

    CYW20733 Figure 5. 32-kHz Oscillator Block Diagram 32.768 kHz XTAL Table 6. XTAL Oscillator Characteristics Parameter Symbol Conditions Minimum Typical Maximum Unit Output frequency – – 32.768 – oscout Frequency tolerance – Crystal – – dependent Start-up time – – – startup W XTAL drive level...

  • Page 14: Theory Of Operation

    CYW20733 Hardware debouncing and noise/glitch filtering. ■ Low-power consumption. Single-digit µA-level sleep current. ■ 1.9.1 Theory of Operation The key scan block is controlled by a state machine with the following states: Idle The state machine begins in the idle state. In this state, all column outputs are driven high. If any key is pressed, a transition occurs on one of the row inputs.

  • Page 15: Pwm

    CYW20733 The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input multiplexers that select the ADC input signal (V ) and the ADC reference signals (V Table 7.

  • Page 16: Serial Peripheral Interface

    CYW20733 Figure 6. PWM Block Diagram pwm_cfg_adr register pwm#_init_val_adr register pwm#_togg_val_adr register pwm#_cntr_adr cntr value is ARM readable pwm_out Example: PWM cntr w/ pwm#_init_val = 0 (dashed line) PWM cntr w/ pwm#_init_val = x (solid line)                   10'H3FF pwm_togg_val_adr 10'Hx 10'H000 pwm_out 1.13 Serial Peripheral Interface The CYW20733 has two independent SPI interfaces. One is a master-only interface (SPI_1) and the other (SPI_2) can be either a master or a slave.
  • Page 17 CYW20733 Table 9. CYW20733 Second SPI Set (Master Mode) Configuration SPI_CLK SPI_MOSI SPI_MISO SPI_CS – – – – – – – – – – – – – – – – – – – – – – – – a. Any GPIO can be used as SPI_CS when SPI is in master mode. Document No.
  • Page 18 CYW20733 Table 10. CYW20733 Second SPI Set (Slave Mode) Configuration SPI_CLK SPI_MOSI SPI_MISO SPI_CS Document No. 002-14859 Rev. *S Page 17 of 67...

  • Page 19: Infrared Modulator

    CYW20733 Table 10. CYW20733 Second SPI Set (Slave Mode) (Cont.) Configuration SPI_CLK SPI_MOSI SPI_MISO SPI_CS 1.14 Infrared Modulator The CYW20733 includes hardware support for infrared TX. The hardware can transmit both modulated and unmodulated waveforms. For modulated waveforms, hardware inserts the desired carrier frequency into all IR transmissions. IR TX can be sourced from firmware-supplied descriptors, a programmable bit, or the peripheral UART transmitter.

  • Page 20: Infrared Learning

    CYW20733 Figure 7. Infrared TX Infrared‐LD CYW20733 IR TX 1.15 Infrared Learning The CYW20733 includes hardware support for infrared learning. The hardware can detect both modulated and unmodulated signals. For modulated signals, the CYW20733 can detect carrier frequencies between 10–500 kHz and the duration that the signal is present or absent. The CYW20733 firmware driver supports further analysis and compression of a learned signal.

  • Page 21: Triac Control

    CYW20733 The CYW20733 can provide up to four synchronized control signals for left and right eye shutter control. These four lines can output pulses with microsecond resolution for on and off timing. The total cycle time can be set for any period up to 65535 msec. The pulses are synchronized to each other for left and right eye shutters.

  • Page 22: High-Current I/O

    CYW20733 Figure 10. Class-D Block Diagram 667 kHz or 1.33 MHz PWM Modulator 150 kHz From FIFO To Class-D Hi-Fi Rate audio amplifier ΔΣ- 16 LPF Adapter MOD. 8 kHz 128 kHz 16 kHz 256 kHz M = 160 or 320 22.05 kHz 352.8 kHz 44.1 kHz...

  • Page 23: Power Management Unit

    CYW20733 Figure 11. Motor/Vibrator Circuit MA2S111 CYW20733 Motor 10 uF 1.21 Power Management Unit The Power Management Unit (PMU) provides power management features that can be invoked by software through power management registers or packet handling in the baseband core. 1.21.1 RF Power Management The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans- ceiver, which then processes the power-down functions accordingly.

  • Page 24: Pin Assignments

    CYW20733 2. Pin Assignments Table 12. Pin Descriptions Pin Number Power Do- Pin Name Description 81-pin 121-pin 56-pin main FBGA FBGA Radio I/O VDDTF RF antenna port RF Power Supplies VDDIF VDDIF IFPLL power supply VDDLNA VDDLNA RF front-end supply VDDRF VDDRF VCO, LOGEN supply...
  • Page 25 CYW20733 Table 12. Pin Descriptions (Cont.) Pin Number Power Do- Pin Name Description 81-pin 121-pin 56-pin main FBGA FBGA PCM2/I PCM_SYNC I/O, PD VDDM Frame synchronization for PCM interface. Alternate function: • S word select PCM_CLK I/O, PD VDDM Clock for PCM interface. Alternate function: •...
  • Page 26 CYW20733 Table 13. GPIO Pin Descriptions Pin Number Pin Name Default Di- Power Alternate Function Description 81-pin 121-pin 56-pin rection State Domain FBGA FBGA Input Floating VDDO • GPIO: P0 • Keyboard scan input (row): KSI0 • A/D converter input 29 •...
  • Page 27 CYW20733 Table 13. GPIO Pin Descriptions (Cont.) Pin Number Pin Name Default Di- Power Alternate Function Description 81-pin 121-pin 56-pin rection State Domain FBGA FBGA Input Floating VDDO • GPIO: P9 • Keyboard scan output (column): KSO1 • A/D converter input 26 •...
  • Page 28 CYW20733 Table 13. GPIO Pin Descriptions (Cont.) Pin Number Pin Name Default Di- Power Alternate Function Description 81-pin 121-pin 56-pin rection State Domain FBGA FBGA – Input Floating VDDO • GPIO: P22 • Keyboard scan output (column): KSO14 • A/D converter input 13 •...
  • Page 29 CYW20733 Table 13. GPIO Pin Descriptions (Cont.) Pin Number Pin Name Default Di- Power Alternate Function Description 81-pin 121-pin 56-pin rection State Domain FBGA FBGA Input Floating VDDO • GPIO: P32 • A/D converter input 7 • Quadrature: QDX0 • SPI_2: SPI_CS (slave only) •...

  • Page 30: Ball Maps

    CYW20733 Table 13. GPIO Pin Descriptions (Cont.) Pin Number Pin Name Default Di- Power Alternate Function Description 81-pin 121-pin 56-pin rection State Domain FBGA FBGA – – Input Floating VDDO • GPIO: P41 • pcm2_sync – – Input Floating VDDO •...
  • Page 31 CYW20733 Figure 12. 81-Pin FBGA Ball Map LDOOUT LDOIN VDDC VDDO PWM0 P39/ VDDIF RESET_N PWM1 XTALI32K VDDTF PWM2 P38/ PWM3 XTALO32K VDDLNA PCM_ VDDRF PCM_IN PCM_ PCM_ VDDPX SYNC UART_ UART_ RTS_N CTS_N UART_ UART_ XTALI XTALO VDDM VDDC Document No.

  • Page 32: 121-Pin Fbga Ball Map

    CYW20733 2.1.2 121-Pin FBGA Ball Map Figure 13 shows the 121-pin FBGA package ball map. Figure 13. 121-Pin FBGA Ball Map LDOIN VDDC XTALI32K VDDO PWM2 PWM0 LDOOUT XTALO32K VDDO PWM1 VDDIF RESET_N PWM3 VDDTF VDDO VDDLNA VDDRF VDDPX PCM_ PCM_CLK VSSSP VSSSP...

  • Page 33: 56-Pin Qfn Diagram

    CYW20733 2.1.3 56-Pin QFN Diagram Figure 14 shows the 56-pin QFN package. Figure 14. 56-Pin QFN Diagram RESET_N LDOIN LDOOUT VDDC VDDIF VDDTF VDDLNA VDDRF VDDPX Document No. 002-14859 Rev. *S Page 32 of 67...

  • Page 34: Specifications

    CYW20733 3. Specifications 3.1 Electrical Characteristics Table 14 shows the maximum electrical rating for voltages referenced to the VDD pin. Table 14. Maximum Electrical Rating Rating Symbol Value Unit DC supply voltage for RF domain – 1.32 DC supply voltage for Core domain –...
  • Page 35 CYW20733 Table 17. ADC Specifications Parameter Symbol Conditions Unit ADC Characteristics Number of Input channels – – – – – Channel switching rate – – – Input signal range – – 3.63 s Reference settling time – – – – Input resistance Single-ended, input range of 0–1.2V –...
  • Page 36 CYW20733 Table 20. Current Consumption, Class 1 Operational Mode Conditions Unit Receive (1 Mbps) Peak current level during reception of a basic-rate packet. 28.2 Transmit (1 Mbps) Peak current level during the transmission of a basic-rate packet: GFSK 63.1 output power = 10 dBm. Receive (EDR) Peak current level during the reception of a 2 or 3 Mbps rate packet.
  • Page 37 CYW20733 Table 21. Current Consumption, Class 2 (0 dBm) Operational Mode Conditions Unit Receive (1 Mbps) Peak current level during the reception of a basic-rate packet. 29.0 Transmit (1 Mbps) Peak current level during the transmission of a basic-rate packet: GFSK 39.3 output power = 0 dBm.

  • Page 38: Rf Specifications

    CYW20733 Table 22. Current Consumption Operational Mode Conditions Unit A Sleep Internal LPO is in use. 46.5 A HIDOFF – A Inquiry scan (1.28 sec.) Periodic scan rate is R1 (1.28 seconds). A Page Scan (R1) Periodic scan rate is R1 (1.28 seconds). A Inquiry Scan + Page Scan (R1) Both inquiry and page scans are interlaced together at a...
  • Page 39 CYW20733 Table 23. Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit Spurious Emissions 30 MHz to 1 GHz – – – –57 1 GHz to 12.75 GHz – – – –47 a. All specifications are single ended. Unused inputs are left open. b.

  • Page 40: Timing And Ac Characteristics

    CYW20733 3.3 Timing and AC Characteristics In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams. 3.3.1 UART Timing Table 25. UART Timing Specifications Reference Characteristics Unit Delay time, UART_CTS_N low to UART_TXD valid –...

  • Page 41: Spi Timing

    CYW20733 3.3.2 SPI Timing Figure 16. SPI Timing Diagram SCLK Mode 1 SCLK Mode 3 MOSI Invalid bit MISO Table 26. SPI1 Timing Values—SCLK = 12 MHz and VDDM = 1.8V Reference Characteristics Symbol Typical Unit Output setup time, from MOSI Tds_mo – –...

  • Page 42: Bsc Interface Timing

    CYW20733 Table 27. SPI1 Timing Values—SCLK = 12 MHz and VDDM = 3.3V Reference Characteristics Symbol Typical Unit Output setup time, from MOSI data valid to Tds_mo – – sample edge of SCLK Output hold time, from sample Tdh_mo – –...
  • Page 43 CYW20733 Table 29. BSC Interface Timing Specifications (up to 1 MHz) Reference Characteristics Unit STOP condition setup time – Output valid from clock – Bus free time – a. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

  • Page 44: Pcm Interface Timing

    CYW20733 Table 30. BSC Interface Timing Specification (1 MHz through 4 MHz) Reference Characteristics Unit Clock frequency 1.000 4.000 START condition setup time – START condition hold time – Clock low time ½ SCL period – Clock high time ½ SCL period –...
  • Page 45 CYW20733 PCM Electrical Timing Slave—Long Frame Sync ■ PCM Electrical Timing Master—Long Frame Sync ■ PCM Electrical Timing Burst (Slave Rx Only)—Long Frame Sync ■ Note: The TX and RX timings are combined on the same diagram. The CYW20733 can only either transmit or receive in a given slot. PCM Electrical Timing Slave —...
  • Page 46 CYW20733 PCM Electrical Timing Master—Short Frame Sync Figure 19. PCM Electrical Timing Master—Short Frame Sync Diagram PCM_BCLK PCM_SYNC PCM_OUT High impedance Bit 15 (Previous Frame) Bit 0 Bit 15 (Previous Frame) Bit 0 PCM_IN Table 32. Values of PCM Electrical Timing Master—Short Frame Sync Characteristics Reference Characteristics Minimum Typical Maximum Unit PCM bit clock frequency...
  • Page 47 CYW20733 Table 33. Values of PCM Electrical Timing Burst (Slave Rx-Only)—Short Frame Sync Characteristics Reference Characteristics Minimum Typical Maximum Unit PCM bit clock frequency – – PCM bit clock low time 20.8 – – PCM bit clock high time 20.8 –...
  • Page 48 CYW20733 PCM Electrical Timing Master—Long Frame Sync Figure 22. PCM Electrical Timing Master—Long Frame Sync Diagram PCM_BCLK PCM_SYNC PCM_OUT High impedance Bit 0 Bit 1 PCM_IN Bit 0 Bit 1 Table 35. Values of PCM Electrical Timing Master—Long Frame Sync Characteristics Reference Characteristics Minimum Typical Maximum Unit PCM bit clock frequency...

  • Page 49: I 2 S Timing

    CYW20733 Table 36. Values of PCM Electrical Timing Burst (Slave Rx Only)—Long Frame Sync Characteristics Reference Characteristics Minimum Typical Maximum Unit PCM bit clock frequency – – PCM bit clock low time 20.8 – – PCM bit clock high time 20.8 –...
  • Page 50 CYW20733 Table 37. Values of I S Electrical Timing Slave—Short Frame WS Characteristics Reference Characteristics Minimum Typical Maximum Unit I2S_IN setup – – I2S_IN hold – – S Electrical Timing Master—Short Frame WS Figure 25. I S Electrical Timing Master — Short Frame WS Diagram I2S_BCLK I2S_WS I2S_OUT...
  • Page 51 CYW20733 S Electrical Timing Burst (Slave Rx Only)—Short Frame WS Figure 26. I S Electrical Timing Burst (Slave Rx Only) — Short Frame WS Diagram I2S_BCLK I2S_WS I2S_IN Bit 15 (previous frame) Bit 0 Table 39. Values of I S Electrical Timing Burst (Slave Rx-Only)—Short Frame WS Characteristics Reference Characteristics Minimum...
  • Page 52 CYW20733 Table 40. Values of I S Electrical Timing Slave—Long Frame WS Characteristics Reference Characteristics Minimum Typical Maximum Unit S bit clock frequency – – S bit clock low time – – S bit clock high time – – I2S_WS setup time –...
  • Page 53 CYW20733 S Electrical Timing Burst (Slave Rx Only)—Long Frame WS Figure 29. I S Electrical Timing Burst (Slave Rx Only) — Long Frame WS Diagram I2S_BCLK I2S_WS I2S_IN Bit 0 Bit 1 Table 42. Values of I S Electrical Timing Burst (Slave Rx Only)—Long Frame WS Characteristics Reference Characteristics Minimum...

  • Page 54: Mechanical Information

    CYW20733 4. Mechanical Information Figure 30. 81-Pin FBGA Document No. 002-14859 Rev. *S Page 53 of 67...
  • Page 55 CYW20733 Figure 31. 121-Pin FBGA Document No. 002-14859 Rev. *S Page 54 of 67...
  • Page 56 CYW20733 Figure 32. 56-Pin QFN Document No. 002-14859 Rev. *S Page 55 of 67...

  • Page 57: Tape Reel And Packaging Specifications

    CYW20733 4.0.1 Tape Reel and Packaging Specifications Table 43. CYW20733 8 × 8 × 1.0 mm FBGA 81-Pin Tape Reel Specifications Quantity per reel 2500 pieces Reel diameter 13 inches Hub diameter 7 inches Tape width 16 mm Tape pitch 12 mm Table 44.
  • Page 58 CYW20733 Figure 33. CYW20733 Reel/Labeling/Packaging Specification Reel Specifications: (Per MSL Labeling Specification – P-PDE-1051) (Per Standard Barcode Label Specification – P-PDE-1101) Device Orientation/Mix Lot Number: Document No. 002-14859 Rev. *S Page 57 of 67...
  • Page 59 CYW20733 Figure 34. CYW20733 9 × 9 FBGA Package Tray (1 of 2) Document No. 002-14859 Rev. *S Page 58 of 67...
  • Page 60 CYW20733 Figure 35. CYW20733 9 × 9 FBGA Package Tray (2 of 2) Document No. 002-14859 Rev. *S Page 59 of 67...
  • Page 61 CYW20733 Figure 36. CYW20733 8 × 8 FBGA Package Tray (1 of 2) Document No. 002-14859 Rev. *S Page 60 of 67...
  • Page 62 CYW20733 Figure 37. CYW20733 8 × 8 FBGA Package Tray (2 of 2) NOTES: 1. Tray shall conform to JEDEC CS-004 standard on thin matrix trays for MQFP package. 2. Tray surfaces to be free of seams. 3. IQA specification SAC-X042 shall apply. 4.

  • Page 63: Ordering Information

    CYW20733 5. Ordering Information Table 46. Ordering Information Part Number Package Ambient Operating Temperature CYW20733A3KFB1G Commercial 81-pin FBGA 0°C to 70°C CYW20733A3KFB2G Commercial 121-pin FBGA 0°C to 70°C CYW20733A3KML1G Commercial 56-pin QFN 0°C to 70°C 6. IoT Resources Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design.
  • Page 64 CYW20733 Acronym Description power-on reset pulse width modulation quadrature decoder random access memory radio frequency read-only memory RX/TX receive, transmit serial peripheral interface software UART universal asynchronous receiver/transmitter µ-processor interface universal serial bus watchdog Document No. 002-14859 Rev. *S Page 63 of 67...

  • Page 65: Document History

    CYW20733 Document History Document Title: CYW20733 Single-Chip Bluetooth Transceiver Wireless Input Devices Document Number: 002-14859 Orig. of Submis- Revision Description of Change Change sion Date 20733-DS00-R – – 07/23/2010 Initial release Updated: Table 10: “Pin Descriptions,” on page 35 and Table 11: “GPIO Pin Descriptions,” on page 38.
  • Page 66 CYW20733 Document Title: CYW20733 Single-Chip Bluetooth Transceiver Wireless Input Devices Document Number: 002-14859 20733-DS05-R Updated: Figure 1: “Functional Block Diagram,” on page 2 “GPIO Port” on page 25 “High Current I/O” on page 34 Table 10: “Pin Descriptions,” on page 36 Figure 13: “121-Pin FBGA Ball Map,”...
  • Page 67 CYW20733 Document Title: CYW20733 Single-Chip Bluetooth Transceiver Wireless Input Devices Document Number: 002-14859 20733-DS12-R Updated: – – 11/26/2012 Table 17: “Integrated Audio Amplifier Electrical Specifications,” on page 58. Table 21: “Current Consumption,” on page 61. 20733-DS13-R – – 01/21/2013 Updated: Table 12: “GPIO Pin Descriptions,”...

  • Page 68: Sales, Solutions, And Legal Information

    CYW20733 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. ® Products PSoC Solutions ®...

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