Active Technologies AT-1120 User Manual

High speed signal generator adapter module for ni flexrio

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AT-1120

1 Channel, 2 GS/s, 800 MHz Analog BW, 14 Bit

High Speed Signal Generator

Adapter Module for NI FlexRIO

User Manual

January, 2013 Rev. 1.3

Active Technologies S.r.l

Via Bela Bartok 29/B

44124 Ferrara, ITALY

Tel +39 0532 91456, Fax: +39 0532 970134

Internet:

www.activetechnologies.it

E-mail: info@activetechnologies.it

Active Technologies

AT-1120 User Guide and Specifications

www.activetechnologies.it

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Page 1 January, 2013 Rev. 1.3 Active Technologies S.r.l Via Bela Bartok 29/B 44124 Ferrara, ITALY Tel +39 0532 91456, Fax: +39 0532 970134 Internet: www.activetechnologies.it E-mail: info@activetechnologies.it © 2013 Active Technologies . All rights reserved AT-1120 User Guide and Specifications www.activetechnologies.it...
Page 2: Table Of Contents
DACModuleControl(Host).exe ....................18 GeneratePulse(Host).vi ......................21 DDS and Trigger Route.vi ......................22 Using Your AT-1120 with a LabVIEW FPGA Example VI .............. 23 Creating a Host VI on an FPGA Target ..................26 Running the Host VI ........................30 Creating a Custom FPGA Target ....................31 Running the Host VI ........................
Page 3 Configuration EEPROM Map ...................... 36 Electromagnetic Compatibility ....................36 CE Compliance ..........................37 Appendix: Installing EMI Controls ....................38 Installing PXI EMC Filler Panels ....................38 AT-1120 User Guide and Specifications - 3 - www.activetechnologies.it...
Page 4: At-1120 User Guide And Specifications
AT-1120 User Guide and Specifications The AT-1120 is a one-channel, 2 GS/s, 14-bit, 800 MHz Analog Bandwidth, High-Speed Signal Generator adapter module designed to work in conjunction with your NI FlexRIO™ FPGA module. This document contains signal information and specifications for the AT-1120R, which is composed of an NI FlexRIO FPGA module and the AT-1120.
Page 5: Electromagnetic Compatibility Guidelines
Appendix: Installing EMI Controls section of this document. Caution To ensure the specified EMC performance, operate this product only with shielded cables and accessories. Caution This product is sensitive to electrostatic discharge (ESD). AT-1120 User Guide and Specifications - 5 - www.activetechnologies.it...
Page 6: How To Use Your Ni Flexrio Documentation Set
Contains examples of how to run FPGA VIs and Host VIs on your device. Other Useful Information on ni.com ni.com/ipnet Contains LabVIEW FPGA functions and intellectual property to share. ni.com/flexrio Contains product information and data sheets for NI FlexRIO devices. AT-1120 User Guide and Specifications - 6 - www.activetechnologies.it...
Page 7 * These documents are also available at ni.com/manuals. AT-1120 User Guide and Specifications - 7 - www.activetechnologies.it...
Page 8: Front Panel And Connector Pinouts
Front Panel and Connector Pinouts Table 2 shows the front panel connectors and signal descriptions for AT-1120. Refer to the Specifications sheet for additional signal information. Caution To avoid permanent damage to the AT-1120, disconnect all signals connected to the AT-1120 before powering down the module, and connect signals only after the adapter module has been powered on by the NI FlexRIO FPGA module.
Page 9 Caution Connections that exceed any of the maximum ratings of any connector on the AT-1120R can damage the device and the chassis. Active Technologies is not liable for any damage resulting from such signal connections. For the maximum input and output ratings for each signal, refer to the Specifications sheet.
Page 10: At-1120 Component-Level Intellectual Property (Clip)
DRAM0 DRAM1 Figure 4. CLIP Relationship The AT-1120 ships with socketed CLIP items that are used to add module I/O to the LabVIEW project. The AT-1120 ships with the following CLIP item: AT_1120_IOModule_CLIP. AT-1120 User Guide and Specifications - 10 -...
Page 11: At-1120 Clip Design
The data read from the look up tables are serialized by the CLIP to provide the requested data rate to the DAC. Clip files: AT_1120_IOModule_CLIP.xml; AT_1120_IOModule_CLIP.vhd; PLL_125M.vhd; i2c_ctrl.vhd; OSerdes8_1.vhd; AT_1120_Constraints.ucf; AT1120_IOModule.tbc AT-1120 User Guide and Specifications - 10 - www.activetechnologies.it...
Page 12: Fpga I/O Interface
The user should set it to false if he needs to use the TCXO onboard clock or set it to true if he needs to use the clock coming from the AT-1120 User Guide and Specifications - 11 - www.activetechnologies.it...
Page 13: Clocking Scheme
Use any shielded 50 Ω coaxial cable with an SMA plug end to connect to the AO 0+, AO 0, TRIG IN, TRIG OUT and CLK IN connectors on the AT-1120 front panel. For more information about connecting I/O signals on your device, refer to the Specifications sheet.
Page 14: Labview Interface
The user has to load each look-up tables with the same waveform and the CLIP reads them updating the Start/Stop Address and Increment parameters to convey parallel data stream at the converter at high speeds. AT-1120 User Guide and Specifications - 13 - www.activetechnologies.it...
Page 15 Increment In Arbitrary mode the Increment is fixed at 16; in DDS it depends on the DAC sampling rate, the output frequency and on the number of samples. Please refer to AT-1120 User Guide and Specifications - 14 - www.activetechnologies.it...
Page 16 Increment parameter represents the value the accumulator is updated determining the frequency of the generated waveform. A more detailed description of DDS can be found in Understanding Direct Digital Synthesis (DDS) AT-1120 User Guide and Specifications - 15 - www.activetechnologies.it...
Page 17: Labview Interface Host Side
DAC A Aligned: if true the DAC has been correctly initialized and aligned Error out IMPORTANT NOTE: the user should NOT hit the ABORT button during the initialization. SetVocm.vi Set the Vocm voltage AT-1120 User Guide and Specifications - 16 - www.activetechnologies.it...
Page 18 Start the waveform generation on the selected channels. StartGeneration (Host).vi If Sync is true, the adapter modules waits for global software trigger (PXIe-DSTARB) to start the generation. StopGeneration (Host).vi Stop the waveform generation on the selected channels AT-1120 User Guide and Specifications - 17 - www.activetechnologies.it...
Page 19: Software Prerequisites
32-Bit Paths C:\Program Files \National Instruments\Shared\FlexRIO\IO Modules\AT 1120 C:\Program Files \National Instruments\Shared\FlexRIO\IO Modules\AT 1212 Example Code Review for AT-1120 adapter module DACModuleControl(Host).exe Software requirements: Labview 2012 + Modulation Toolkit This LabView application gives the user full access to all the main 1120/1212 features. The control panel provides a waveform generator style approach to the FAM, allowing to set the parameters of the signals that will be load and generated by the FAM.
Page 20 QAM modulation adding AWGN, IQ Impairments, Phase Noise to the output pattern.  Press the APPLY button to display the changes on the graph .  Press the LOAD WAVEFORM button to upload the data into the FPGA look-up tables. AT-1120 User Guide and Specifications - 19 - www.activetechnologies.it...
Page 21 DDS frequency, Sweep Freq.Incr and Sweep Freq.Max controls. It is also possible to generate a frequency sweep, setting the increment and the stop frequency and then pressing the SWEEP ON/OFF button. AT-1120 User Guide and Specifications - 20 - www.activetechnologies.it...
Page 22: Generatepulse(Host).Vi
Set the NumSamples: the samples number of the pulse waveform. It must be multiple of 16. Module Init OK: indicator that states if the module is properly initialized or not. SKIP INIT: if true, the FAM skips the initialization phase. AT-1120 User Guide and Specifications - 21 - www.activetechnologies.it...
Page 23: Dds And Trigger Route.vi
Fill the Destination Trigger Array with the PXIe_DSTARB global trigger routing connections. The FlexRIO boards will receive now the same trigger signal.  Press the Send Trigger button to send it to all connected FAMs. AT-1120 User Guide and Specifications - 22 - www.activetechnologies.it...
Page 24: Using Your At-1120 With A Labview Fpga Example Vi
Complete the following steps to run an example that generates a waveform on AO 0+ of the AT-1120. 1. Connect one end of an SMA cable to AO 0+ on the front panel of the AT-1120 and the other end of the cable to your oscilloscope input (50 Ω). Tap the unused output (AO 0-) with a 50 Ω...
Page 25 Select and open AT1120_1212_SignalGenerator.lvproj LabView project. In the Project Explorer window, open DACModuleControl (Host).exe under My Computer. 5. On the front panel, in the resource pull-down menu, select an AT-1120 resource that corresponds with the target configured in step 4.
Page 26 15. Press the RUN SELECTED CH. button to start the waveform generation 16. Press the STOP button to stop the generation 17. Press the EXIT VI button to stop the VI. AT-1120 User Guide and Specifications - 25 - www.activetechnologies.it...
Page 27: Creating A Host Vi On An Fpga Target
8. Place the GetFPGA1120Reference.vi to get the reference to the 1120 FPGA Target (AT_HS_Signal_Generator\FPGA Bitfiles\AT1120SignalGenerator_FPGATarget.lvbitx)   9. Connect resource name RIO Device IN and error in error in control 10. Place the InitModule1120(Host).vi, located on \AT_HS_Signal_Generator\1120Module folder AT-1120 User Guide and Specifications - 26 - www.activetechnologies.it...
Page 28 14. Samples 128, Amplitude 4000, Cycle 1, Phase 0, add 8192 to the waveform array and connect the samples array to the Waveform Graph. If the VI execution arrives at the second frame, it means that the adapter module has been AT-1120 User Guide and Specifications - 27 - www.activetechnologies.it...
Page 29 Connect the RIO Device and WavefArray like in the picture below 18. Add a Frame After in the stacked sequence: we will start the waveform generation 19. Add a Flat Sequence Structure AT-1120 User Guide and Specifications - 28 - www.activetechnologies.it...
Page 30 Connect the FPGA VI Reference IN  FPGA Reference and place Close FPGA VI Reference block located on FPGA Interface wiring it like in the picture below. The second frame contains the True constant to stop the VI. AT-1120 User Guide and Specifications - 29 - www.activetechnologies.it...
Page 31: Running The Host Vi
4. Click the Run button to run the VI. 5. Wait for module initialization. 6. The AT-1120 generates one 128 points sine waveform. 7. Click the STOP button on the front panel to stop the module and the VI. AT-1120 User Guide and Specifications - 30 - www.activetechnologies.it...
Page 32: Creating A Custom Fpga Target
7. Right-click IO Module in the Project Explorer window and select Properties. 8. Select the Active Technologies: AT-1120 from the IO Module list. The available CLIP items for the AT-1120 are displayed in the General category of the Component Level IP panel. If AT-1120 User Guide and Specifications - 31 - www.activetechnologies.it...
Page 33 General category is dimmed, select the Enable IO Module checkbox. 9. Select Active Technologies: AT-120 to use the connector-based CLIP. 10. Click on the Clock Selections category and select DStarA Clock as clockin and 40 MHz Onboard Clock as clockin40m.
Page 34 Memory Method node. Right-click on the Memory method, Select Memory>>Memory1. 21. Left-click on the Memory1 Memory Method and select the Read method. Insert a new shift register in the Timed Loop and wire the connectors like in the picture above. AT-1120 User Guide and Specifications - 33 - www.activetechnologies.it...
Page 35: Running The Host Vi
4. Click the Run button to run the VI. 5. Wait for module initialization. 6. Click the START CHANNELS button to start the waveform generation. 7. The AT-1120 generates one 2048 points sine waveform. AT-1120 User Guide and Specifications - 34 -...
Page 36: Filter Options
Filter Options If necessary, images and sample clock feed-through can be largely removed using a low-pass filter; Active Technologies suggests the following filters depending on the application and the user needs:  Mini Circuit RLP-470+  Mini Circuit SBPL-467 (Maximally Flat Group Delay) ...
Page 37: Specifications
Caution To avoid permanent damage to the AT-1120, disconnect all signals connected to the AT-1120 before powering down the module, and only connect signals after the module has been powered on by the NI FlexRIO FPGA module.
Page 38: Ce Compliance
Level: 1V/m mod. 1kHz AM 80% at 3m of distance - frequency range 2.0 ÷2.7 GHz. CE Compliance This product meets the essential requirements of applicable European Directives as follows:  2006/95/EC; Low-Voltage Directive (safety)  2004/108/EC; Electromagnetic Compatibility Directive (EMC) AT-1120 User Guide and Specifications - 37 - www.activetechnologies.it...
Page 39: Appendix: Installing Emi Controls
Figure 15. Make sure that the EMC gasket is on the right side of the PXI EMC filler panel. Captive Screw Covers Captive Mounting Screws EMC Gasket Figure 15. PXI EMC Filler Panels and Chassis AT-1120 User Guide and Specifications - 38 - www.activetechnologies.it...
Page 40 Do not over tighten screws (2.5 lb · in. maximum). For additional information about the use of PXI EMC filler panels in your PXI system, visit ni.com/info and enter emcpa AT-1120 User Guide and Specifications - 39 - www.activetechnologies.it...

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At-1120r