Summary of Contents for Memec Virtex-II V2MB1000
- Page 1 Virtex-II™ V2MB1000 Development Board User’s Guide Version 3.0 December 2002 PN# DS-MANUAL-V2MB1000...
- Page 2 Memec Design Development Kit Owners Certificate Thank you for purchasing your Memec Design development kit. As an owner of this kit, you can register for access to the Reference Design Center. In the Reference Design Center, you may download reference design examples for this particular kit, along with source code, and application notes.
- Page 3 Memec in connection with this product, all of which are provided “as is”, and this disclaimer shall apply to any implied warranties or conditions of merchantability, satisfactory or merchantable quality and fitness for a particular purpose, or those arising from a course of dealing or usage of trade.
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Page 4: Table Of Contents
Table of Contents OVERVIEW ........................1 THE VIRTEX-II SYSTEM BOARD ...................1 -II S ..............2 IRTEX YSTEM OARD ESCRIPTION -II D .....................2 IRTEX EVICE DDR M ......................3 EMORY ....................4 LOCK ENERATION ......................5 ESET IRCUIT ..................5 EGMENT ISPLAY 2.6.1 7-Segment Display Signal Description..............6 LED.......................6 (SW5, SW6) ............6... - Page 5 2.18.1 LVDS Interface ..................... 14 2.18.2 LVDS Port Signal Descriptions ..............17 2.18.3 Packet Over SONET Level 4 (PL4) application ..........19 2.19 (SW2) ..................20 ROGRAM WITCH 2.20 ................... 20 OLTAGE EGULATORS 2.20.1 Voltage Regulators Jumper Settings .............. 21 2.21 -II C ..............
- Page 6 Figures 1 – V -II S ..................1 IGURE IRTEX YSTEM OARD 2 – V -II S ..............2 IGURE IRTEX YSTEM OARD LOCK IAGRAM 3 – DDR I ......................3 IGURE NTERFACE 4 – R ......................5 IGURE ESET IRCUIT 5 - 7-S LED D .................5 IGURE...
- Page 7 Tables 1 - DDR M ............3 ABLE EMORY NTERFACE IGNAL ESCRIPTIONS 2 – V -II D ............4 ABLE IRTEX EVELOPMENT OARD ASTER LOCKS 3 - 7-S ..............6 ABLE EGMENT ISPLAY IGNAL ESCRIPTIONS 4 - U ............6 ABLE UTTON WITCH IGNAL SSIGNMENTS 5 - U DIP S...
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Page 8: Overview
An LVDS interface is provided with a 16-bit transmit and 16-bit receive port plus clock, status, and control signals for each. The board also supports the Memec Design P160 expansion module standard, allowing application specific expansion modules to be easily added. -
Page 9: Virtex-Ii System Board Description
Virtex-II System Board Description A high-level block diagram of the Virtex-II development board is shown in Figure 2 followed by a brief description of each sub-section. User User 7-Segment S w i t c h e s Display (2) P 1 6 0 M o d u l e User R S 2 3 2 L E D s... -
Page 10: Ddr Memory
DDR Memory The Virtex-II development board provides 32MB of DDR memory on the system board. This memory is implemented using the Micron MT46V16M16TG -75 16Mx16 DDR device. A high-level block diagram of the DDR interface is shown below followed by a table describing the DDR memory interface signals. -
Page 11: Clock Generation
Address 12 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 DQ10 Data 10 DQ11 Data 11 DQ12 Data 12 DQ13 Data 13 DQ14 Data 14 DQ15 Data 15 Bank Select 0 Bank Select 1 Low Write Mask... -
Page 12: Reset Circuit
Reset Circuit The Virtex-II system board uses the TI TPS3125 voltage supervisory device to monitor the Virtex- II FPGA core voltage (1.5V). This circuit asserts a reset signal (FPGA_RESETn) to the Virtex-II device when the 1.5V core voltage falls below its minimum specifications (1.425V). The reset signal to the FPGA is a fixed 100ms active low pulse. -
Page 13: 7-Segment Display Signal Description
2.6.1 7-Segment Display Signal Description The following table shows the 7-Segment LED display pin descriptions. Table 3 - 7-Segment Display Signal Descriptions Signal Name Virtex-II Pin # Description DISPLAY.1A 7-Segment LED Display1, Segment A DISPLAY.1B 7-Segment LED Display1, Segment B DISPLAY.1C 7-Segment LED Display1, Segment C DISPLAY.1D... -
Page 14: User Dip Switch Signal Assignments
S W 4 S w i t c h DIP8 DIP7 DIP6 DIP5 DIP4 DIP3 DIP2 DIP1 Figure 6 – User DIP Switch Interface 2.9.2 User DIP Switch Signal Assignments The following table shows the user switch pin assignments. Table 5 - User DIP Switch Signal Assignments Signal Name Virtex-II Pin # Description... -
Page 15: Rs232 Signal Descriptions
2.10.2 RS232 Signal Descriptions The following table shows the RS232 signals and their pin assignments to the Virtex-II FPGA. Table 6 - RS232 Signal Descriptions Signal Name Virtex-II Pin # Description Received Data, RD to DB9 Transmit Data, TD from DB9 2.11 JTAG Port The Virtex-II development board provides a JTAG connector that can be used to program the on- board ISP PROM and configure the Virtex-II FPGA. -
Page 16: Jtag Chain
2.11.3 JTAG Chain The following figure shows the JTAG chain on the Virtex-II development board. Jumper JP22 provides the ability to remove the ISP PROM from the JTAG chain for direct connection to the FPGA. J P 2 2 T D I T D I X C 1 8 V 0 4 Virtex-II... -
Page 17: Slave Selectmap
S e l e c t M a p / S l a v e S e r i a l C o n n e c t o r C S n DONE C C L K IN I T n P R O G R A M n R D / W n DOUT/BUSY... -
Page 18: Slave Serial Port
D[0:7] D[0:7] DONE C C L K C C L K RESET/OE INIT_B V i r t e x - I I X C 1 8 V 0 4 FPGA PROG_B J P 2 7 C S _ B J u m p e r RDWR_B Figure 13 –... -
Page 19: Virtex-Ii Power Down Mode
Table 8 - Bank I/O Voltage Jumper Settings Bank # Virtex-II VCCO Jumper I/O Voltage Pin # JP18 Closed Open 3.3V Open Closed 2.5V FIXED 2.5V JP26 Closed Open 3.3V Open Closed 2.5V FIXED 2.5V Closed Open 3.3V Open Closed 2.5V Closed Open... -
Page 20: Virtex-Ii Vbat
Virtex-II FPGA 3.3V P W R D W N _ B Figure 15 – Virtex-II Power Down Mode As shown in the above figure, the Virtex -II FPGA can be placed in the power-down mode on the Virtex-II system board by closing the JP16 jumper (permanently placing it in the power-down mode until the jumper is removed), or by forcing the pin 2 of the JP16 to a logic 0 under user control.
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