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TENX TECHNOLOGY TM59MA41 User Manual

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TM59MA41
User's Manual
tenx technology, inc.
tenx technology, inc.
0
Preliminary
Rev 1.2, 2008/05/19

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Summary of Contents for TENX TECHNOLOGY TM59MA41

  • Page 1 Advance Information TM59MA41 User’s Manual tenx technology, inc. tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 2: Table Of Contents

    11-1. 20-DIP Package Dimension ................61 11-2. 20-SOP Package Dimension................62 11-3. 20-SSOP Package Dimension ................63 11-4. 16-DIP Package Dimension ................64 11-5. 16-SOP Package Dimension................65 11-6. 16-SSOP Package Dimension ................66 tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 3: Chapter 1. Overview

    LVR Level Selection LVR/IVC control in STOP mode n Reset pin Selection Clock Source Selection Read protection control Reset vector: 000H Interrupt vector: 001H Power Down mode Package Types: 20-SOP, SSOP, DIP 16-SOP, SSOP, DIP tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 4 Advance Information UM-TM59MA41_E <Figure 1-1. System Block Diagram> <Figure 1-2. Pin Assignment Diagram _ Package Types: 20-Pin SOP/DIP/SSOP> tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 5 12-Bit high speed PWM output PA.7 T0OUT Timer0 match output PC.0 PA.0–PA.7 ADC0–ADC9 A/D converter input PC.5–PC.6 < Table 1-1. PIN Description > < I: Input; O: Output; I/O: Bi-direction; P: Power > tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 6: Clock Scheme And Instruction Cycle

    INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). Reading INDF itself indirectly (FSR=0) will produce 00h. Writing to the INDF register indirectly results in a no-operation. tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 7: Alu And Working (W) Register

    ADD instruction SUB instruction 1: a carry occurred from the MSB 1: no borrow 0: no carry 0: a borrow occurred from the MSB <Table 1-2. STATUS — System Flags Register (Address: 03H)> tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 8: Interrupt

    1-6. Interrupt The TM59MA41 has 1 level, 1 vector and 6 sources. Each interrupt source has its own enable control bit. An interrupt event will set its individual flag. Because TM59MA41 has only 1 vector, there is not a interrupt priority register.

  • Page 9: Power-Down Mode

    IVR/LVR reference voltage control in SYSL register. The default value of SYSL is 3FFFh. The 13th bit is code protection selection bit. If write this bit to 0, the data of ROM will be all 3FFFh, when user read ROM. tenx technology, inc. Preliminary...
  • Page 10 External RC Internal RC (4.6MHz in Vdd = 5.0V) Not Used LVR Enable bit Disable LVR at sleep mode Enable LVR at all time LVR level selection bit 3.9V 3.0V 2.3V Other Not Used tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 11: Instruction Set

    Working Register Zero Flag Carry Flag Decimal Carry Flag Program Counter Top Of Stack Global Interrupt Enable Flag (i-Flag) Option Field Contents Bit Field ← Assign direction < Table 1-3. OP-CODE Field Description > tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 12 Return with Literal "k" in W 01 1000 kkkk kkkk Go into standby mode, Clock SLEEP 00 0000 1000 1010 oscillation stops XORLW XOR Literal "k" with W 01 1111 kkkk kkkk < Table 1-4. Instruction Summary > tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 13 (f.b) ← 0 Status Affected OP-Code 01 000b bbff ffff Description Bit ’b’ in register ’f’ is cleared. Cycle Example BCF FLAG_REG, 7 B : FLAG_REG = 0xC7 A : FLAG_REG = 0x47 tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 14 The eleven-bit immediate address is loaded into PC bits <11:0>. CALL is a two-cycle instruction. Cycle Example LABEL1 CALL SUB1 B : PC = LABEL1 A : PC = SUB1, TOS = LABEL1+1 tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 15 Decrement register ‘f’. If ‘d’ is 0, the result is stored in the W register. If ‘d’ is 1, the result is stored back in register ‘f’. Cycle Example DECF CNT, 1 B : CNT = 0x01, Z = 0 A : CNT = 0x00, Z = 1 tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 16 1 or 2 Example LABEL1 INCFSZ CNT, 1 B : PC = LABEL1 GOTO LOOP A : CNT = CNT + 1 CONTINUE if CNT=0, PC = CONTINUE if CNT≠0, PC = LABEL1+1 tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 17 00 0000 1fff ffff Description Move data from W register to register ‘f’. Cycle Example MOVWF REG1 B : REG1 = 0xFF, W = 0x4F A : REG1 = 0x4F, W = 0x4F tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 18 Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Cycle Example RETURN A : PC = TOS tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 19 = 0111 0011, C = 0 SLEEP Go into standby mode, Clock oscillation stops Syntax SLEEP Operands Operation Status Affected OP-Code 00 0000 1000 1010 Description Go into SLEEP mode with the oscillator stopped. Cycle Example SLEEP tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 20 The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. Cycle Example XORLW 0xAF B : W = 0xB5 A : W = 0x1A tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 21 W register. If ‘d’ is 1, the result is stored back in register ‘f’. Cycle Example XORWF REG 1 B : REG = 0xAF, W = 0xB5 A : REG = 0x1A, W = 0xB5 tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 22: Chapter 2. Control Register

    PWM0CON PACONH PWM0DAT PBCON PWM1CON PCCONL PWM1DAT PCCONH PWM1EX PINTD T1CON INTCON T1DATA INTPND T0CON T0DATA BZCON ADCCON ADCDATL ADCDATH System Use Only GPR0 GPR1 GPR2 GPR3 GPR4 GPR5 2000 SYSL Hard ware tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 23 End-of-Conversion Status Bit A/D conversion is in progress A/D conversion complete (NOTE 1) Clock Source Selection Bit Conversion Start Bit No meaning A/D conversion start NOTE : Maximum ADC Input Clock is 4MHz. tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 24 — Buzzer Out Control Register Address: 15H Related Register Reset Value R/W R/W R/W R/W R/W R/W R/W R/W Description Input Clock Selection / 16 / 32 / 64 Buzzer Period Data XXXXXX Period Data tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 25 R/W R/W R/W R/W R/W R/W R/W R/W Description General Purpose Register GPR0-GPR5 are mirrored all bank. It is useful to pass arguments to SUB routine or backup Working register (W) and STATUS register in ISR or SUB routine. tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 26 No interrupt pending (read) / Pending bit clear (write) Interrupt is pending (read) / No effect (write) Port A.0 EXTINT0 Interrupt Pending Bit No interrupt pending (read) / Pending bit clear (write) Interrupt is pending (read) / No effect (write) tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 27 ADC1 Input (Schmitt trigger input off) Port A.0 Configuration Bits Schmitt trigger input (pull-up enable) / External Interrupt 0 Input Schmitt trigger input / External Interrupt 0 Input Push-pull output ADC0 Input (Schmitt trigger input off) tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 28 Schmitt trigger input (pull-up enable) Schmitt trigger input Push-pull output ADC5 Input (Schmitt trigger input off) Port A.4 Configuration Bits Schmitt trigger input (pull-up enable) Schmitt trigger input Push-pull output ADC4 Input (Schmitt trigger input off) tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 29 Port B.0 Configuration Bits Schmitt trigger input (pull-up enable) Schmitt trigger input Push-pull output Schmitt trigger input (pull-down) Open-drain Output Other Value Not Used PORTB.2 can be configured by System Config Register (SYSL). tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 30 Push-pull output Open-drain output Port C.1 Configuration Bits Schmitt trigger input (pull-up) Buzzer Out Push-pull output Open-drain output Port C.0 Configuration Bits Schmitt trigger input(pull-up) Schmitt trigger input Push-pull output T0 match output tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 31 Schmitt trigger input (pull-up) Schmitt trigger input Push-pull output Open-drain output — Port A Data Register Address: 05H Related Register Reset Value R/W R/W R/W R/W R/W R/W R/W R/W Description Port A.7-0 Data Bits tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 32 This register represents Lower 8-Bit of PC+1. The PC can be changed writing any value (00h~FFh) into this register. It is similar to GOTO instruction. But the branch instruction by PCL can access only higher address than PC. tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 33 Reload from 8-bit up counter overflow Reload from 6-bit up counter overflow PWM0 Counter Clear Bit (Auto Cleared) No effect Clear the PWM counter (when write) PWM0 Enable Bit Stop counter Start (Resume countering) tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 34 Reload from 12-bit up counter overflow Reload from 6-bit up counter overflow PWM1 Counter Clear Bit (Auto Cleared) No effect Clear the PWM counter (when write) PWM1 Enable Bit Stop counter Start (Resume counting) tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 35 − Description Power Down Control Register This register is not physical register. The device can enter STOP mode by writing any value into this register. The SLEEP instruction is equivalent to “MOVWF PWRDN”. tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 36 STOPCON — Stop Mode Control Register Address: 08H Related Register Reset Value R/W R/W R/W R/W R/W R/W R/W R/W Description Stop Mode Enable Bit 10100101 Enable STOP mode others Disable STOP mode tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 37 Address: 01H Related Register Reset Value Description Timer 0 Counter Value T0DATA — TIMER 0 Data Register Address: 14H Related Register Reset Value R/W R/W R/W R/W R/W R/W R/W R/W Description Period Data tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 38 Related Register Reset Value Description Timer 0 Counter Value T1DATA — TIMER 1 Data Register Bank 1, Address: 11H Related Register Reset Value R/W R/W R/W R/W R/W R/W R/W R/W Description Period Data tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 39 WatchDog Timer Control Register This register is not physical register. The WatchDog timer can be enabled and refreshed by CLRWDT or writing any value into this register. The CLRWDT instruction is equivalent to “MOVWF WDTE”. tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 40 NOTE: The IVC level must greater then or equal to .For example , if the = 4.5V then the IVC level must be 5.0V. if the = 3.6V then the IVC level must be 4.0V. tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 41: Chapter 3. Timer0,1

    UM-TM59MA41_E Chapter 3. Timer0,1 TM59MA41 has two timers (Timer 0,1). Timer 0,1 are used in one 16-bit timer or two 8-bit timers mode. Timer 0,1 has the following functional components: Clock frequency selector 8-bit counter (T0CNT), 8-bit comparator, 8-bit data register (T0DATA), and data buffer.
  • Page 42 Example 3-1> Timer 0 overflow time calculation CPU Clock ( ):8.192MHz Prescaler Ratio (T0CON.5-4):00 ( /256), Period Data (T0DATA.7-0):31 Timer 0 overflow freqency = 8.192M / 256 / (31+1) = 1000Hz Time = 1 / 1000Hz = 1ms tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 43 ; Set T0CON Control Register PCCONL,0 ; Select PC.0 match output. PCCONL,1 ; PCCONL Bit [1-0]:[11] is match output INTCON, 2 ; Timer0 Interrupt Enable T0CON,3 ; Timer0 Counter Clear T0CON,2 ; Start Timer 0 tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 44: Chapter 4. 8-Bit Pwm

    < Table 4-1 PWM output extended cycle > For example, if the value in the extension data register is '01B', the 2nd cycle will be one pulse longer than the other 3 cycles. (see Figure 4-2). tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 45 ; Data = 1, Extension = 1 CLRF PACONH PACONH,4 ; Select PACONH.54 '01' PWM0 Out. CLRF /64, 8-bit Overflow Reload, PWM Stop PWM0CON ; PWM0 Counter Clear PWM0CON,1 PWM0CON,0 ; PWM0 Start PWM0CON,0 ; PWM0 Stop tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 46: Chapter 5. 12-Bit Pwm

    (PWM1EX.7-2). This 6-bits is used to "extend" the duty cycle of the PWM output. The "extension" value is one extra clock period at specific cycles (see Table 5-1). PWM1EX.7-2 Extended Cycle 1,3,5,7,9,…,55,57,59,61,63 2,6,10,14,…,50,54,58,62 4,12,20,…,44,52,60 8,24,40,56 16,48 Not used Not used < Table 5-1 PWM output extended cycle > tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 47 PWM1DAT = 1 EXT Bit = 00b PWM1DAT = 1 EXT Bit = 01b PWM1DAT = 1 EXT Bit = 10b PWM1DAT = 1 EXT Bit = 11b < Figure 5-2 Extended Output > tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 48: Chapter 6. Analog To Digital Converter

    ; Configure PA.0 ADC Input 0 ADCCON, 0 ; Start Conversion ADC_LOOP: BTFSS ADCCON, 3 GOTO ADC_LOOP ; Wait until EOC bit is set ; Converted value can be read from ADDATL and ; ADDATH. tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 49 50 ADC clock Conversion Start ADDATA ADDATAH (8-bit) + ADDATAL (2-bit) 40 clock Conversion Time Set-up time 10 clock < Figure 6.2 A/D Conversion Timing Diagram > ※ Maximum ADC Input Clock is 4MHz. tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 50: Chapter 7. I/O Ports

    Advance Information UM-TM59MA41_E Chapter 7. I/O Ports The TM59MA41 has three I/O port, PORTA, PORTB and PORTC (MAX 18 Pin). These ports can be accessed directly by writing or reading port data register. Input/ PORT Pin No Pin Description Output...
  • Page 51 < Figure 7-1 Pin Circuit Type A > Pull-up Open-drain Control Enable Enable Register P-CH Alternative Data Output Port Data N-CH Output Disable (Input Mode) Digital Input Analog Input Enable < Figure 7-2 Pin Circuit Type B > tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 52 Analog Input Enable < Figure 7-3 Pin Circuit Type C > Open-drain Enable Pull-up Enable Port Data Output Disable (Input Mode) Pull-Down Enable Digital Input < Figure 7-4 Pin Circuit Type D > tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...
  • Page 53 PORTC Port C has 7-bit I/O Pins. It can be used for normal I/O (Schmitt trigger input, push-pull output, open-drain output) or some alternative function (ADC, Clock output, T0 clock output, Buzzer out). tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 54: Chapter 8. Buzzer Out

    Advance Information UM-TM59MA41_E Chapter 8. Buzzer Out The TM59MA41 has Buzzer driver that consist of 6-bit counter, clock divider, control register. It generates 50% duty square-wave and the frequency cover a wide range. Counter 6-Bit Buzzer Out Comparator Buzzer Data BZCON.5-0...
  • Page 55 Advance Information UM-TM59MA41_E Buzzer Counter Buzzer Data Buzzer Data Buzzer Buzzer Disable Change Change Enable Before > After Before < After Buffer Reload Buzzer Output < Figure 8-2 Timing Diagram > tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 56: Chapter 9. Flash Memory Interface

    Chapter 9. Flash Memory Interface The TM59MA41 has an on-chip Flash Memory (MTP) instead of OTP ROM. The Flash Memory can be accessed by serial format. The 5 pin are connected a programming by serial OTP/MTP Tools. The 12.5V programming power is supplied into the VPP pin.

  • Page 57: Chapter 10. Electrical Characteristics

    – = 2.6V = 0V Pull-Up Resistor = 5V Ports A, B, C kΩ Pull-Down Resistor = 0V Ports B = 5V NOTE: Output current high = -10mA Output current Low = 25mA tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 58: Clock Timing Constants

    NOTE: Tolerance: ±10 % at T = 25°C, Resister Value around 7.1K (ohm). Tolerance: ±20 % at T = 25°C External Oscillator Circuit External R-C Oscillator (Crystal or Ceramic) System Operating Frequency Range tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 59: External Interrupt Characteristics

    – (NOTE 2) Current = 5 V stop mode – NOTE: “Conversion time” is the time required from the moment a conversion operation starts until it ends. is operating current during A/D conversion. tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 60: Reset Timing Characteristics

    = – 40 ° C to + 85 ° C, V 10-7. LVR Circuit Characteristics (T = 2.0V to 5.5V) Parameter Symbol Unit LVR reference Voltage – – LVR Hysteresis Voltage – – ±0.3 HYST Low Voltage μs – – Detection time tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 61: Chapter 11. Packaging Information

    Advance Information UM-TM59MA41_E Chapter Packaging Information The TM59MA41 order information: “IC Type” “XX” “YY” “C” “Z”. 1. “IC TYPE”: TM59MA41 2. “XX”: Package Type • DIP Code: D • SOP Code: S • SSOP Code: SS 3. “YY”: IC Pin Number •...

  • Page 62: 20-Dip Package Dimension

    Advance Information UM-TM59MA41_E 11-1. 20-DIP Package Dimension 20 lead, Dual In-line Package Dimension in Millimeters tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 63: 20-Sop Package Dimension

    Advance Information UM-TM59MA41_E 11-2. 20-SOP Package Dimension 20 lead, Small Outline Package Dimension in Millimeters tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 64: 20-Ssop Package Dimension

    Advance Information UM-TM59MA41_E 11-3. 20-SSOP Package Dimension 20 lead, Shrink Small Outline Package Dimension in Millimeters tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 65: 16-Dip Package Dimension

    Advance Information UM-TM59MA41_E 11-4. 16-DIP Package Dimension 16 lead, Dual In-line Package Dimension in Millimeters tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 66: 16-Sop Package Dimension

    Advance Information UM-TM59MA41_E 11-5. 16-SOP Package Dimension 16 lead, Small Outline Package Dimension in Millimeters tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

  • Page 67: 16-Ssop Package Dimension

    Advance Information UM-TM59MA41_E 11-6. 16-SSOP Package Dimension 16 lead, Shrink Small Outline Package Dimension in Millimeters tenx technology, inc. Preliminary Rev 1.2, 2008/05/19...

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