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AEN (O)
"Address Enable" is used to degate the microprocessor and other
devices from the I/O channel to allow DMA transfers to take place.
When this line is active, the DMA controller has control of the address
bus, the data-bus Read command lines (memory and l/O), and the
Write command lines (memory and I/O)
-REFRESH (I/O)
This signal is used to indicate a refresh cycle and can be driven by a
microprocessor on the I/O channel.
T/C (0)
"Terminal Count" provides a pulse when the terminal count for any
DMA channel is reached.
SBHE (I/O)
"Bus High Enable" (system) indicates a transfer of data on the upper
byte of the data bus, SD8 through SD15. Sixteen-bit devices use "
SBHE" to condition data bus buffers tied to SD8 though SD15.
-MASTER (I)
This signal is used with a DRQ line to gain control of the system. A
processor or DMA controller on the I/O channel may issue a DRQ to a
DMA channel in cascade mode and receive a "-DACK". Upon receiving
the "-DACK", an I/O microprocessor may pull "-MASTER" low, which
will allow it to control the system address, data, and control lines (a
condition known as tri-state): After "-MASTER" is low, the I/O
microprocessor must wait one system clock period before driving the
address and data lines, two clock periods before driving the address
and data lines, and two clock periods before issuing a Read or Write
command. If this signal is held low for more than 15 microseconds,
system memory may be lost because of a lack of refresh.
-MEM CS16 (
)
I
"-MEM 16 Chip Select" signals the system board whether the present
data transfer is a 1 wait-state, 16-bit, memory cycle. It must be derived
from the decode of LA17 through LA23. "-MEM CS16" should be driven
with an open collector or tri-state driver capable of sinking 20 mA.
Chapter 6: Appendix
39
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