No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of E2V products. EXCEPT AS SET FORTH IN E2V'S TERMS AND CONDITIONS OF SALE LOCATED...
Since this Development Kit is intended to be used on an industrial workbench and mod- ified by the user to build his prototypes, NO WARRANTY OF ANY KIND can apply. NO LIABILITY will be accepted by e2v, whatsoever may arise as a result of the use of these boards.
FPGA 12V supply adapter (VIRTEX 6) The complete system is built with the e2v demo kit and an FPGA development kit. e2v Demo kit contains the following items : Quad 10-bit Demo kit with EV10AQ190CTPY ADC Cables & Power Supply –...
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ADC output data (FFT). Software and Graphical User Interface are provided with the Demo Kit. The provided software operates using Labview RunTime (no license required). EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
Quick Start Section 2 Quick Start Operating 1. Install the Software as described in section 4 Software Tools. Procedure 2. Install the FPGA code into ML605 Xilinx evaluation board (see Section 5.3 “FPGA Programming” 3. Turn OFF the ML605 Xilinx evaluation board. 4.
Note: check if test mode is OFF (see Section 4.5.2 TEST) Check if acquisition mode is correctly configured. Warning: if no windowing is used or if signal is non coherent, FFT of Figure 6 is obtained EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Quick Start Figure 2-2. FFT without Windowing or with non Coherent Signal Figure 2-3. FFT with Windowing Warning: if the Fin frequency has an exact value such as 250 MHz the FTT result is wrong that is why it is recommended to perform measurements with shift of few MHz e.g.
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Figure 2-5. RF Attenuator Added on SMA Connector Check that the junction temperature of QUAD 10-bit ADC is lower than 105°C and that heatsink is properly connected. Figure 2-6. Junction Temperature Monitoring with GUII EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Quick Start Check if acquisition is synchronous. The ADC RAMP test procedure will set the ADC to output a ramp on each channel these ramps are synchronous at the output of the ADC after a SYNC process has been completed. The FPGA RESET done during this procedure will always ensure that the 4 channels are acquired in the FPGA synchronously.
– For optimum performance this generator must have a low phase noise Please see Table 2-1 for example of signal generator. Cables & Power Supply (provided by e2v) – Universal 12V power Adapter & Cables – USB Cables to communicate with a PC (control of ADC settings and settings...
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Quick Start Option RF generator for clock input signal whose frequency is different than 2 GHz – The QUAD 10-bit Demo Kit provides clock signal at 2 GHz using its own PLL – The QUAD 10-bit Demo Kit could be tested with other clock frequency Please see Section 6.2 Clock selection Table 2-1.
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Quick Start EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
Main Functions Section 3 Main Functions Analog Input The user only needs to provide an analog signal at the input. Signal This signal is digitized by the ADC depending on the chosen operating mode: 4 channel mode (1 channel per ADC core) 2 channel mode (2 interleaved ADC cores) 1 channel mode (4 interleaved ADC cores) Each channel input is driven in different ways on the board:...
D channel Ext Clock 3.1.1 Analog Input The Analog input channel A uses a differential amplifier (ADC driver) from Analog Channel A Devices ref: ADA4960. Figure 3-2. Channel A : Schematic EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
Main Functions The ADA4960 is used in DC configuration with output common mode driven by ADC QUAD 10-bit. The input is biased at 2.5V since this is a requirement for best perfor- mance from the amplifier, this should be taken into account when using this input. Note: be careful that if a DC voltage is added after the RF generator output that this will not damage the generator.
Balun RF transformer (MABA-007159 MACOM). Note: for operation at different clock frequencies it is probable that the FPGA interface will need to be re-compiled using different timing constraints. Please see Section 6.2 Clock selection. EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
(with SPI signal). Please see Section 4.5 Operating Modes. Please refer to datasheet EV10AQ190x for more information. http://www.e2v.com/products-and-services/specialist-semiconductors/broadband-data- converters/datasheets/ By default the SPI signal is controlled by FX2 microcontroller but it could be driven by the FPGA. Please refer to Section 6.3 SPI Signal for more information.
) can be measured by the Demo Kit. Consumption Figure 3-9. ADC Measurement (Partial): Schematic Monitoring ADC currents (ICC, ICCO and ICCD) can also be monitored via the GUI. Please see Section 4.5.5 Power. EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
Main Functions ADC SYNC The QUAD 10-bit ADC requires a SYNC signal when the internal configuration is changed (for example Channel configuration, DMUX configuration, test mode ….). The Signal QUAD 10-bit Demo Kit performs this SYNC signal automatically when these modes are changed.
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Main Functions Figure 3-11. 3V3A Power Supplies Figure 3-12. 1.8V Power Supplies The amplifier and PLL power supply uses low noise LDO regulators from Linear Technology. LT3029EDE EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Main Functions Figure 3-13. EV10AQ190x-DK - User Guide 1067BX–BDC–12/11...
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Main Functions 3-10 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
The Demo Kit board can be plugged with XILINX VIRTEX 6 evaluation board EK-V6- ML605-G http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm e2v provides FPGA program to be used with Quad 10-bit Demo Kit. User Interface software The User Interface software is a Visual C++ compiled graphical interface that does not...
1. Install the Quad 10-bit Demo Kit application on your computer by launching the SetupEvalkitQuadAdc10Bits.exe installer (please refer to the latest version Installation available). The screen shown in Figure 4-2 is displayed: Figure 4-2. Quad 10-bit Demo Kit Application "Setup Wizard" Window EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Software Tools If you agree with the install configuration, press Install button. Now a new process of installation started Processing&Display for installing Labview RunTime (no license required. Please follow instructions. Warning: don't press finish button on "Completing Setup wizard" window. The screen shown in Figure 4-7 is displayed: 6.
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Figure 4-9. Quad 10-bit Demo Kit Processing&Display "Install the Application" The installation of the software is now completed but the Processing&Display software need to be launched. This installation is launched automatically. EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
The installation is normally fully automatic. If it is not launched automatically, please pro- ceed as described below: The window shown in Figure 4-13 will be displayed. Figure 4-13. Install Driver Software Please choose: Locate and install driver software (recommended) EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Software Tools Figure 4-14. Allow Windows to Search Driver Please choose: Yes, always search online (recommended) Figure 4-15. Browse the Driver Software Please choose: Browse my computer for driver software (advanced) EV10AQ190x-DK - User Guide 1067BX–BDC–12/11...
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Software Tools Figure 4-16. Choose the Folder Select C:\Program Files\E2V\EvalkitQuadAdc10Bits Figure 4-17. Warning: Installation Please choose: Install the driver software anyway A Data transfer has been beginning please wait. 4-10 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Software Tools Figure 4-18. END of New Driver Installation The new driver has been installed After the installation, the interface can be launched with the following file: C:\Program Files\E2V\EvalkitQuadAdc10Bits\EvalkitQuadAdc10Bits.bat EV10AQ190x-DK - User Guide 4-11 1067BX–BDC–12/11...
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Software Tools The window shown in Figure 4-19 will be displayed. Figure 4-19. User Interface Demo Kit 4-12 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
Software Tools Operating Modes The Quad 10-bit ADC software included with the Demo Kit provides a Graphical User Interface to configure the ADC. Push buttons, popup menus and capture windows allows easy: 1. Settings; 2. Test; 3. Gain / Offset / Phase; 4.
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On the bottom corner the software displays information about software and hardware revision. ChipId: revision of Quad 10-bit ADC Device: revision of FX2 software FPGA: revision of VHDL code Figure 4-25. Software and Hardware Revision 4-14 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
Software Tools 4.5.1 Settings Figure 4-26. User Interface Demo Kit In this window, 5 functions are available: ADC mode: General Standby Synchronization Reset EV10AQ190x-DK - User Guide 4-15 1067BX–BDC–12/11...
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A, B, C or D channel. Note: because of limitation of ML605 evaluation board (LVDS max 1GHz in speed grade -1) The capture of Quad 10-bit data is limited to 2 GSps. 4-16 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Software Tools Figure 4-29. ADC Mode: 1-channel Mode Simultaneous channel mode = the analog input signal of channel A or B or C or D is sent to the 4 ADCs work at the same clock (4 ADC with the same timing) with Fclock/2 sampling rate (where Fclock is the external clock signal frequency).
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Synchronization: programs the number of clock cycles prior to output clock restart after SYNC reset Figure 4-32. Extraclock Configuration Reset: Synchronization: programs the number of clock cycles prior to output clock restart after SYNC reset; Figure 4-33. Hard Reset 4-18 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
Software Tools 4.5.2 TEST In this window, the test mode is available: A ramp test is generated within each ADC and output Figure 4-34. Test Ramp Test Mode Note: this mode allows synchronizing the 4 channels of ADC with the FPGA RESET. The synchronizing procedure can be initiated by checking the Disable button and then the Apply button : Then check the ADC and Ramp button and then Apply.
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Figure 4-37. Gain / Offset / Phase Settings In this window, it is possible to adjust gain, offset and phase of the selected channel via the "channel select" button on the top left of the user interface. 4-20 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Software Tools A LED shows if the channel is ON (active - green LED) or OFF (not active - red LED) and if the same channel is ready (ready to receive gain, offset or phase orders - green LED) or busy (not ready to receive new calibration orders - red LED). Figure 4-38.
Software Tools Figure 4-40. Gain Write Send Sequence 4.5.3 Input Impedance Figure 4-41. User Interface Demo Kit - Input Impedance Settings 4-22 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Software Tools In this window, it is possible to re-adjust the internal input resistor, which should be matched to 50Ω. The procedure is similar to the previous ones: select the channel where you need to adjust the input impedance check that the channel is ON and READY (green LEDs) enter the resistor value push the WRITE button to write these values to the internal registers (you can retrieve the initial value of the impedance by clicking on the CANCEL button)
Figure 4-43. User Interface Demo Kit - Clock Settings Note: because of limitation of ML605 evaluation board (LVDS max 1GHz in speed grade -1). The capture of Quad 10-bit data is limited to 2 GSps. 4-24 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
Software Tools 4.5.5 Power This sheet allows measurement of the Quad 10-bit power consumption and the internal junction temperature. Figure 4-44. User Interface Demo Kit - Power EV10AQ190x-DK - User Guide 4-25 1067BX–BDC–12/11...
Software Tools 4.5.6 Acquisition Control This sheet controls the acquisition modes of the Quad 10-bit. Figure 4-45. User Interface Demo Kit - Acquisition Control 4-26 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Software Tools Sampling Nbr: Number of samples in acquisition Must be a 2n For FFT N=4X2n (n=number bit of ADC). For INL N=16X2n (n=number bit of ADC) Example for 10-bit ADC FFT must be computed with 4096 points and INL with 16384 points Nb Harmonics: Number of Harmonics considered for THD and SNR calculation (Default value is 10...
Figure 4-49. User Interface Demo Kit - Stream Function When an acquisition is launched several window results appear: CH_A => ADC channel A CH_B => ADC channel B CH_C => ADC channel C CH_D => ADC channel D 4-28 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Software Tools Figure 4-50. Sample Signal: Example of Signal in Simultaneous Channel Figure 4-51. INL Curve Example EV10AQ190x-DK - User Guide 4-29 1067BX–BDC–12/11...
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Software Tools Figure 4-52. FFT Spectrum Example Figure 4-53. FFT Parameters Example 4-30 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Software Tools Plot selection: one channel or several channels can be plotted for easier reading. Figure 4-54. Plot Selection Figure 4-55. Zoom Selection: Several Kinds of Zoom can be chosen Figure 4-56. Lock Selection EV10AQ190x-DK - User Guide 4-31 1067BX–BDC–12/11...
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Selection 0 => ADC Channel A Selection 1 => ADC Channel B Selection 2 => ADC Channel C Selection 3 => ADC Channel D Figure 4-58. FFF Selection 4-32 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Software Tools FFT Processing: For future calculations, we define: ∑ Sig = Signal power level ""spectrum setup.PeakWidth ∑ Ho = Power of the continuous component spectrum setup.PeakWidth ∑ H1 = Power of the fundamental spectrum setup.cal..Nbr of Harmonics ""setup.PeakWidth ∑ ∑...
Figure 4-59. Example of Context of the Demo Kit Warning: for each channel A B C D don't forget to push the SEND button to per- form this setting on each sheet (Setting, Gain/Offset/Phase, INL…). 4-34 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
Software Tools 4.5.9 Data Save File It is also possible to save the data of your acquisition (saving of all data samples and FFT result). This data is stored into an Excel file with different sheet: Sample signal: Data of Quad 10-bit ADC with channel A B C D in this order in columns INL curve of channel A B C D in this order in columns FTT parameters (SFDR, THD, SNR, SINAD, EBOB) of each Channel A B C D in line...
Software Tools 4.5.10 Regional and Use a control Regional Setting to check if decimal separator is configured with a dot ".". Language Options Figure 4-61. Regional and Language Options 4-36 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Software Tools Selection: Customize this format. Figure 4-62. Customize Regional Option Sheet Numbers The decimal separator must be configured with a dot "." EV10AQ190x-DK - User Guide 4-37 1067BX–BDC–12/11...
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Software Tools 4-38 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
FPGA CODE Section 5 FPGA CODE The FPGA code has been designed to be used with ML605 Xilinx Virtex 6 evaluation board. ® ® Figure 5-1. ML605 Xilinx VIRTEX 6 Evaluation Board Warning: Please configure your ML605 evaluation board with correct Switch configuration. Software XILINX configuration: VIRTEX-6 FPGA ML605 Evaluation Kit Xilinx ISE Design Suite version 12 or upper with IMPACT software...
Launch the iMPACT of ISE suite and load the CDROM\FPGA bin\bin\prog_q10.ipf Figure 5-3. Loading of DKQUAD10bit.ipf file Note: ensure that program into PROM is correctly programmed. Don't forget to program the CDROM\FPGA Bin\progQ10_V1.1.mcs file into PROM. EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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FPGA CODE Figure 5-4. Programming the File PROM\DKQUAD10bit.mcs Figure 5-5. Program Succeeded EV10AQ190x-DK - User Guide 1067BX–BDC–12/11...
Demo kit Hardware Configuration Section 6 Demo kit Hardware Configuration The Demo Kit could be hardware configured by changing manually some capacitor or resistance. This chapter describes all user settable hardware configurations. Channel D The Channel D could be used in DC configuration mode by replacing C126 and C127 by a 0Ω...
The selection between the two clocks is done manually with a resistor. Note: e2v doesn't provide the SPI controller FPGA code. Remove R93, R95, R97, R99 and R101 resistors and solder R94, R96, R98, R100 and R102 with a 0Ω.
FPGA. The selection between the two clocks is done manually with a resistor. Note: e2v doesn't provide the SYNC signal FPGA code. Remove R105 resistor and solder R106 with a 0Ω. Figure 6-6. SYNC Schematic Figure 6-7. Implantation of R105 and R106 Resistors...
Layout Information Section 7 Layout Information Figure 7-1. Top Side Layer 1 Figure 7-2. Bottom Side Layer 12 EV10AQ190x-DK - User Guide 1067BX–BDC–12/11...
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Layout Information EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
Mechanical Dimensions Section 8 Mechanical Dimensions The Demo Kit board with Quad 10-bit ADC dimension is 139 mm × 76.5 mm × 8 mm. It is compatible with VITA57 FMC standard. Figure 8-1. Mechanical Dimensions EV10AQ190x-DK - User Guide 1067BX–BDC–12/11...
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Mechanical Dimensions EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
Ordering Information Section 9 Ordering Information Table 9-1. Ordering Information Part Number Temperature Comments EV10AQ190TPY-DK Ambient ROHS compliant EV10AQ190x-DK - User Guide 1067BX–BDC–12/11...
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Ordering Information EV10AQ190x-DK - User Guide 1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its stan- dard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with informa- tion contained herein.
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1067BX–BDC–12/11 e2v semiconductors SAS 2011...
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