Ic Pin Function Description - Sony MDS-JE780 Service Manual

MDS-JE780

6-13. IC PIN FUNCTION DESCRIPTION

• IC101 CXA2523AR RF Amplifier (BD BOARD)
Pin No. Pin Name I/O
I
1 I I-V converted RF signal I input
2 J I I-V converted RF signal J input
3 VC O Middle point voltage generation output
I
4 - 9 A to F Signal input from the optical pick-up detector
I
10 PD Light amount monitor input
11 APC O Laser APC output
I
12 APCREF Reference voltage input for setting laser power
—
13 GND Ground
14 TEMPI I Temperature sensor connection
O
15 TEMPR Reference voltage output for the temperature sensor
I
16 SWDT Serial data input from the CXD2664R
17 SCLK I Serial clock input from the CXD2664R
I
18 XLAT Latch signal input from the CXD2664R "L": Latch
I
19 XSTBY Stand by signal input (Fixed at "H")
20 F0CNT I Center frequency control voltage input of BPF22, BPF3T, EQ from the CXD2664R
O
21 VREF Reference voltage output (Not used)
I
22 EQADJ Center frequency setting pin for the internal circuit EQ
23 3TADJ I Center frequency setting pin for the internal circuit BPF3T
—
24 Vcc Power supply
I
25 WBLADJ Center frequency setting pin for the internal circuit BPF22
26 TE O Tracking error signal output to the CXD2664R
—
27 CSLED External capacitor connection pin for the sled error signal LPF
O
28 SE Sled error signal output to the CXD2664R
29 ADFM O FM signal output of ADIP
I
30 ADIN ADIP signal comparator input ADFM is connected with AC coupling
—
31 ADAGC External capacitor connection pin for AGC of ADIP
32 ADFG O ADIP duplex signal output to the CXD2664R
O
33 AUX I signal/temperature signal output to the CXD2664R
3
O
34 FE Focus error signal output to the CXD2664R
35 ABCD O Light amount signal output to the CXD2664R
36 BOTM O RF/ABCD bottom hold signal output to the CXD2664R
O
37 PEAK RF/ABCD peak hold signal output to the CXD2664R
38 RF O RF equalizer output to the CXD2664R
39 RFAGC — External capacitor connection pin for the RF AGC circuit
I
40 AGCI The RF amplifier output is input with AC coupling
41 COMPO O User comparator output (Not used)
42 COMPP I User comparator input (Fixed at "L")
—
43 ADDC External capacitor pin for cutting the low band of the ADIP amplifier
44 OPO O User operation amplifier output (Not used)
45 OPN I User operation amplifier inversion input (Fixed at "L")
O
46 RFO RF amplifier output
47 MORFI I Groove RF signal is input with AC coupling
48 MORFO O Groove RF signal output
• Abbreviation
APC: Auto Power Control
AGC: Auto Gain Control
• IC201 CXD2664R Digital Signal Processor, Digital Servo Signal Processor (BD BOARD)
Description
* O (3) for 3-state output in the column I/O
46 46
Pin No. Pin Name I/O
Not used (open)
1
MNT0 (FOK) O
Track jump detection signal output to the system control
2
MNT1 (SHCK) O
In the state of executire command signal output
3 MNT2 (XBUSY) O
4 Not used (open)
MNT3 (SLOC) O
5 Power supply
VDC0 —
6 Serial data input from the system control
SWDT I
7 Serial clock signal input from the system control
SCLK I
8 Serial latch signal input from the system control
XLAT I
9 Ground
VSC0 —
10 Serial reading data output to the system control
SRDT O (3)
11 Internal status (SENSE) output to the system control
SENS O (3)
12 Reset signal input from the system control "L": Reset
XRST I
13 Subcode Q sync (SCOR) output to the system control
SQSY O
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system
14
DQSY O
control
15 Laser power switching input from the system control "H": Recording, "L": Playback
RPWR I
16 Interrupt status output to the system control
XINT O
17 Recording data output enable input from the system control
TX O
18 Power supply
VDIO0 —
19 System clock input (Fixed at "L")
OSCI I
20 System clock input (Input terminal during OSCN:"H" )
OSCO I/O
21 Internal oscillating circuit control signal input
OSCN I
22 Ground
VSIO0 —
23 System clock frequency setting (Fixed at "H")
XTSL I
24 Digital audio input (Optical input)
DIN0 I
25 Digital audio input (USB input)
DIN1 I
Digital audio output (Optical output)
26
DOUT O
Serial data input
27
DADTI I
LR clock input
28
LRCKI I
Serial data bit clock input
29
XBCKI I
Power supply
30 VDC1 —
31 Ground
VSC1 —
32 Data input from the A/D converter
ADDT I
33 Data output to the D/A converter
DADT O
34 LR clock output for the A/D and D/A converter
LRCK O
35 Bit clock output to the A/D and D/A converter
XBCK O
36 256Fs clock output (Not used)
FS256 O
37 Write enable signal output for DRAM
XWE O
38 Read enable output for DRAM
XOE O
39 Power supply
DRVDD0 —
40 — Ground
DRVSS0
41 O DRAM address output (Not used) (Open)
A11
42 I/O
D3
43 I/O
D0
Data input/output for DRAM
44 I/O
D2
45 I/O
D1
Description